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[Qemu-devel] [PATCH 9/9] target-sh4: add ftrv instruction
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 9/9] target-sh4: add ftrv instruction |
Date: |
Tue, 11 Jan 2011 22:01:38 +0100 |
Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-column
matrix XMTRX by the 4-dimensional vector FVn.
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-sh4/helper.h | 1 +
target-sh4/op_helper.c | 26 ++++++++++++++++++++++++++
target-sh4/translate.c | 11 +++++++++++
3 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/target-sh4/helper.h b/target-sh4/helper.h
index 74d839f..2e52768 100644
--- a/target-sh4/helper.h
+++ b/target-sh4/helper.h
@@ -49,5 +49,6 @@ DEF_HELPER_1(fsqrt_DT, i64, i64)
DEF_HELPER_1(ftrc_FT, i32, i32)
DEF_HELPER_1(ftrc_DT, i32, i64)
DEF_HELPER_2(fipr, void, i32, i32)
+DEF_HELPER_1(ftrv, void, i32)
#include "def-helper.h"
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index d7df3fe..267166b 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -787,3 +787,29 @@ void helper_fipr(uint32_t m, uint32_t n)
env->fregs[bank + n + 3] = r;
}
+
+void helper_ftrv(uint32_t n)
+{
+ int bank_matrix, bank_vector;
+ int i, j;
+ float32 r[4];
+ float32 p;
+
+ bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
+ bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
+ set_float_exception_flags(0, &env->fp_status);
+ for (i = 0 ; i < 4 ; i++) {
+ r[i] = float32_zero;
+ for (j = 0 ; j < 4 ; j++) {
+ p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
+ env->fregs[bank_vector + j],
+ &env->fp_status);
+ r[i] = float32_add(r[i], p, &env->fp_status);
+ }
+ }
+ update_fpscr(GETPC());
+
+ for (i = 0 ; i < 4 ; i++) {
+ env->fregs[bank_vector + i] = r[i];
+ }
+}
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 566ce23..9460a32 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1881,6 +1881,17 @@ static void _decode_opc(DisasContext * ctx)
return;
}
break;
+ case 0xf0fd: /* ftrv XMTRX,FVn */
+ CHECK_FPU_ENABLED
+ if ((ctx->opcode & 0x0300) == 0x0100 &&
+ (ctx->fpscr & FPSCR_PR) == 0) {
+ TCGv n;
+ n = tcg_const_i32((ctx->opcode >> 18) & 3);
+ gen_helper_ftrv(n);
+ tcg_temp_free(n);
+ return;
+ }
+ break;
}
#if 0
fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
--
1.7.2.3
- [Qemu-devel] target-sh4: improve FPU emulation, Aurelien Jarno, 2011/01/11
- [Qemu-devel] [PATCH 5/9] target-sh4: define FPSCR constants, Aurelien Jarno, 2011/01/11
- [Qemu-devel] [PATCH 9/9] target-sh4: add ftrv instruction,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 8/9] target-sh4: add fipr instruction, Aurelien Jarno, 2011/01/11
- [Qemu-devel] [PATCH 7/9] target-sh4: implement FPU exceptions, Aurelien Jarno, 2011/01/11
- [Qemu-devel] [PATCH 6/9] target-sh4: implement flush-to-zero, Aurelien Jarno, 2011/01/11
- [Qemu-devel] [PATCH 3/9] softfloat: fix default-NaN mode, Aurelien Jarno, 2011/01/11
- [Qemu-devel] [PATCH 2/9] softfloat: SH4 has the sNaN bit set, Aurelien Jarno, 2011/01/11