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[Qemu-devel] [PATCH 5/9] target-sh4: define FPSCR constants
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 5/9] target-sh4: define FPSCR constants |
Date: |
Tue, 11 Jan 2011 22:01:34 +0100 |
Define FPSCR constants for all field and use them instead of hardcoded
values.
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-sh4/cpu.h | 35 +++++++++++++++++++++++++++++++----
target-sh4/op_helper.c | 7 ++++---
target-sh4/translate.c | 4 ++--
3 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 8ccf25c..fe33b8a 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -61,10 +61,37 @@
#define SR_S (1 << 1)
#define SR_T (1 << 0)
-#define FPSCR_FR (1 << 21)
-#define FPSCR_SZ (1 << 20)
-#define FPSCR_PR (1 << 19)
-#define FPSCR_DN (1 << 18)
+#define FPSCR_MASK (0x003fffff)
+#define FPSCR_FR (1 << 21)
+#define FPSCR_SZ (1 << 20)
+#define FPSCR_PR (1 << 19)
+#define FPSCR_DN (1 << 18)
+#define FPSCR_CAUSE_MASK (0x3f << 12)
+#define FPSCR_CAUSE_SHIFT (12)
+#define FPSCR_CAUSE_E (1 << 17)
+#define FPSCR_CAUSE_V (1 << 16)
+#define FPSCR_CAUSE_Z (1 << 15)
+#define FPSCR_CAUSE_O (1 << 14)
+#define FPSCR_CAUSE_U (1 << 13)
+#define FPSCR_CAUSE_I (1 << 12)
+#define FPSCR_ENABLE_MASK (0x1f << 7)
+#define FPSCR_ENABLE_SHIFT (7)
+#define FPSCR_ENABLE_V (1 << 11)
+#define FPSCR_ENABLE_Z (1 << 10)
+#define FPSCR_ENABLE_O (1 << 9)
+#define FPSCR_ENABLE_U (1 << 8)
+#define FPSCR_ENABLE_I (1 << 7)
+#define FPSCR_FLAG_MASK (0x1f << 2)
+#define FPSCR_FLAG_SHIFT (2)
+#define FPSCR_FLAG_V (1 << 6)
+#define FPSCR_FLAG_Z (1 << 5)
+#define FPSCR_FLAG_O (1 << 4)
+#define FPSCR_FLAG_U (1 << 3)
+#define FPSCR_FLAG_I (1 << 2)
+#define FPSCR_RM_MASK (0x03 << 0)
+#define FPSCR_RM_NEAREST (0 << 0)
+#define FPSCR_RM_ZERO (1 << 0)
+
#define DELAY_SLOT (1 << 0)
#define DELAY_SLOT_CONDITIONAL (1 << 1)
#define DELAY_SLOT_TRUE (1 << 2)
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index d8d0bb4..9915e42 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -428,11 +428,12 @@ static inline void clr_t(void)
void helper_ld_fpscr(uint32_t val)
{
- env->fpscr = val & 0x003fffff;
- if (val & 0x01)
+ env->fpscr = val & FPSCR_MASK;
+ if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
set_float_rounding_mode(float_round_to_zero, &env->fp_status);
- else
+ } else {
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
+ }
}
uint32_t helper_fabs_FT(uint32_t t0)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 8d59bf9..bdfa31a 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -203,10 +203,10 @@ static void cpu_sh4_reset(CPUSH4State * env)
env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?!
*/
#else
- env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */
+ env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4
manual */
set_float_rounding_mode(float_round_to_zero, &env->fp_status);
#endif
- set_default_nan_mode(1, &env->vfp.fp_status);
+ set_default_nan_mode(1, &env->fp_status);
env->mmucr = 0;
}
--
1.7.2.3
- [Qemu-devel] target-sh4: improve FPU emulation, Aurelien Jarno, 2011/01/11
- [Qemu-devel] [PATCH 5/9] target-sh4: define FPSCR constants,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 9/9] target-sh4: add ftrv instruction, Aurelien Jarno, 2011/01/11
- [Qemu-devel] [PATCH 8/9] target-sh4: add fipr instruction, Aurelien Jarno, 2011/01/11
- [Qemu-devel] [PATCH 7/9] target-sh4: implement FPU exceptions, Aurelien Jarno, 2011/01/11
- [Qemu-devel] [PATCH 6/9] target-sh4: implement flush-to-zero, Aurelien Jarno, 2011/01/11
- [Qemu-devel] [PATCH 3/9] softfloat: fix default-NaN mode, Aurelien Jarno, 2011/01/11
- [Qemu-devel] [PATCH 2/9] softfloat: SH4 has the sNaN bit set, Aurelien Jarno, 2011/01/11