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Re: [Qemu-devel] [PATCH 4/4] target-arm: Fix decoding of Thumb preload a
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 4/4] target-arm: Fix decoding of Thumb preload and hint space |
Date: |
Thu, 3 Feb 2011 20:33:48 +0000 |
On 3 February 2011 19:43, Peter Maydell <address@hidden> wrote:
> @@ -8326,9 +8362,8 @@ static int disas_thumb2_insn(CPUState *env,
> DisasContext *s, uint16_t insn_hw1)
> imm = insn & 0xfff;
> tcg_gen_addi_i32(addr, addr, imm);
> } else {
> - op = (insn >> 8) & 7;
> imm = insn & 0xff;
> - switch (op) {
> + switch ((insn >> 8) & 7) {
> case 0: case 8: /* Shifted Register. */
> shift = (insn >> 4) & 0xf;
> if (shift > 3)
It's pretty obvious from the combination of "switch (something & 7)" with
"case 8:" that the load/store address decode logic here is bogus, but
since that's unrelated to the preload/hint space I'm going to address
it in a separate patchset later.
-- PMM
- [Qemu-devel] [PATCH 0/4] target-arm: Fix decoding of preload and hint insns, Peter Maydell, 2011/02/03
- [Qemu-devel] [PATCH 1/4] target-arm: Add CPU feature flag for v7MP, Peter Maydell, 2011/02/03
- [Qemu-devel] [PATCH 2/4] target-arm: Clean up handling of MPIDR, Peter Maydell, 2011/02/03
- [Qemu-devel] [PATCH 3/4] target-arm: Fix decoding of preload and memory hint space, Peter Maydell, 2011/02/03
- [Qemu-devel] [PATCH 4/4] target-arm: Fix decoding of Thumb preload and hint space, Peter Maydell, 2011/02/03
- Re: [Qemu-devel] [PATCH 4/4] target-arm: Fix decoding of Thumb preload and hint space,
Peter Maydell <=
- Re: [Qemu-devel] [PATCH 0/4] target-arm: Fix decoding of preload and hint insns, Aurelien Jarno, 2011/02/04