Re: [Qemu-devel] [PATCH 09/17] lm32: timer model

[Blue Swirl]

On Sat, Feb 12, 2011 at 12:29 AM, Michael Walle <address@hidden> wrote:
> Am Freitag 11 Februar 2011, 22:22:32 schrieb Blue Swirl:
>> > +static uint32_t timer_read(void *opaque, target_phys_addr_t addr)
>> > +{
>> > +    LM32TimerState *s = opaque;
>> > +    uint32_t r = 0;
>> > +
>> > +    addr >>= 2;
>> > +    switch (addr) {
>> > +    case R_SR:
>> > +    case R_CR:
>> > +    case R_PERIOD:
>> > +        r = s->regs[addr];
>> > +        break;
>> > +    case R_SNAPSHOT:
>> > +        r = (uint32_t)ptimer_get_count(s->ptimer);
>> > +        break;
>> > +
>> > +    default:
>> > +        hw_error("lm32_timer: read access to unkown register 0x"
>> > +                TARGET_FMT_plx, addr << 2);
>>
>> Insecure, please fix also others.
> Many devices in hw/ treat memory access to unknown registers in that way. Are
> there any 'good' example models, where i can look at?

I think Sparc32 devices are OK, though for example DMA handling is not so clean.

> I guess i should print a
> warning instead?

That's one way, but if there are a lot of warnings it becomes a
nuisance. Tracepoints are a bit more flexible, but then they'd have to
be enabled.