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Re: [Qemu-devel] [PATCH 2/3] target-arm: Fix soft interrupt in GIC distr


From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH 2/3] target-arm: Fix soft interrupt in GIC distributor
Date: Wed, 16 Feb 2011 13:50:23 +0000

On 15 February 2011 10:49, Adam Lackorzynski <address@hidden> wrote:
> Fix selection of target list filter mode.
>
> Signed-off-by: Adam Lackorzynski <address@hidden>
> ---
>  hw/arm_gic.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm_gic.c b/hw/arm_gic.c
> index e6b1953..0e934ec 100644
> --- a/hw/arm_gic.c
> +++ b/hw/arm_gic.c
> @@ -549,10 +549,10 @@ static void gic_dist_writel(void *opaque, 
> target_phys_addr_t offset,
>             mask = (value >> 16) & ALL_CPU_MASK;
>             break;
>         case 1:
> -            mask = 1 << cpu;
> +            mask = ALL_CPU_MASK ^ (1 << cpu);
>             break;
>         case 2:
> -            mask = ALL_CPU_MASK ^ (1 << cpu);
> +            mask = 1 << cpu;
>             break;
>         default:
>             DPRINTF("Bad Soft Int target filter\n");

This looks like a good fix based on the TRM; however I don't have an
A9-based image to hand to test with so I've asked a colleague to give
it a quick smoke test before I formally mark it as reviewed-by me
(probably some time next week).

thanks
-- PMM



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