qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-devel] [PATCH v3 0/7] Let boards state maximum RAM limits in QEMUM


From: Peter Maydell
Subject: [Qemu-devel] [PATCH v3 0/7] Let boards state maximum RAM limits in QEMUMachine struct
Date: Tue, 29 Mar 2011 15:08:17 +0100

This primary aim of this patchset is to add a new 'max_ram' field to the
QEMUMachine structure so that a board model can specify the maximum RAM it
will accept.  We can then produce a friendly diagnostic message when the
user tries to start qemu with a '-m' option asking for more RAM than that. 
(Currently most of the ARM devboard models respond with an obscure guest
crash when the guest tries to access RAM and finds device registers
instead.)

If no maximum size is specified we default to the old behaviour of
"do not impose any limit".

The bulk of the patchset is knock-on cleanup as a result, in particular
allowing QEMUMachine structs to be const and sun4m cleanup.

Changes in v3:
 * as suggested by Blue Swirl, new patch 3 to make qemu_register_machine
   take a const QEMUMachine * rather than a non-const one
 * this makes the sun4m patch (old 3, new 4) simpler as we don't have to
   move 'const' qualifiers around
 * new patch 7 which adds 'const' to all the board QEMUMachine definitions

Changes in v2:
 * use target_physaddr_t rather than ram_addr_t for max_ram, so
   we can specify maximum ram sizes for 64 bit target boards
 * new patches 3,4 which update sun4m to use the generic max_ram, so
   we can delete the sun4m-specific code which was doing the same job
 * patch 5 does some tidy-up of sun4m init functions; not strictly
   related but the assert() at least is enabled by the cleanup done
   in patch 3.


Peter Maydell (7):
  Allow boards to specify maximum RAM size
  hw: Add maximum RAM specifications for ARM devboard models
  vl.c: Fix machine registration so QEMUMachine structs can be const
  hw/sun4m: Move QEMUMachine structs into sun4*_hwdef structs
  hw/sun4m: Use the QEMUMachine max_ram to implement memory limit
  hw/sun4m: Use a macro to hide the repetitive board init functions
  hw: Make QEMUMachine structure definitions const

 hw/an5206.c                   |    2 +-
 hw/axis_dev88.c               |    2 +-
 hw/boards.h                   |    6 +-
 hw/dummy_m68k.c               |    2 +-
 hw/etraxfs.c                  |    2 +-
 hw/gumstix.c                  |    4 +-
 hw/integratorcp.c             |    3 +-
 hw/leon3.c                    |    2 +-
 hw/lm32_boards.c              |    4 +-
 hw/mainstone.c                |    2 +-
 hw/mcf5208.c                  |    2 +-
 hw/mips_fulong2e.c            |    2 +-
 hw/mips_jazz.c                |    4 +-
 hw/mips_malta.c               |    2 +-
 hw/mips_mipssim.c             |    2 +-
 hw/mips_r4k.c                 |    2 +-
 hw/musicpal.c                 |    2 +-
 hw/nseries.c                  |    4 +-
 hw/omap_sx1.c                 |    4 +-
 hw/palm.c                     |    2 +-
 hw/pc_piix.c                  |   12 +-
 hw/petalogix_ml605_mmu.c      |    2 +-
 hw/petalogix_s3adsp1800_mmu.c |    2 +-
 hw/ppc405_boards.c            |    4 +-
 hw/ppc440_bamboo.c            |    4 +-
 hw/ppc_newworld.c             |    2 +-
 hw/ppc_oldworld.c             |    2 +-
 hw/ppc_prep.c                 |    2 +-
 hw/ppce500_mpc8544ds.c        |    2 +-
 hw/r2d.c                      |    2 +-
 hw/realview.c                 |   19 ++-
 hw/s390-virtio.c              |    2 +-
 hw/shix.c                     |    2 +-
 hw/spitz.c                    |    8 +-
 hw/stellaris.c                |    4 +-
 hw/sun4m.c                    |  523 ++++++++++++++++-------------------------
 hw/sun4u.c                    |    6 +-
 hw/syborg.c                   |    2 +-
 hw/tosa.c                     |    2 +-
 hw/versatilepb.c              |    9 +-
 hw/virtex_ml507.c             |    2 +-
 hw/xen_machine_pv.c           |    2 +-
 vl.c                          |  115 ++++++----
 43 files changed, 363 insertions(+), 422 deletions(-)




reply via email to

[Prev in Thread] Current Thread [Next in Thread]