Re: [Qemu-devel] [PATCH 15/15] tcg: use ext op for deposit

[Aurelien Jarno]

On Mon, Apr 04, 2011 at 04:32:24PM +0200, Alexander Graf wrote:
> With the s390x target we use the deposit instruction to store 32bit values
> into 64bit registers without clobbering the upper 32 bits.
> 
> This specific operation can be optimized slightly by using the ext operation
> instead of an explicit and in the deposit instruction. This patch adds that
> special case to the generic deposit implementation.
> 
> Signed-off-by: Alexander Graf <address@hidden>
> ---
>  tcg/tcg-op.h |    6 +++++-
>  1 files changed, 5 insertions(+), 1 deletions(-)

Have you really measuring a difference here? This should already be
handled, at least on x86, by this code:

        if (TCG_TARGET_REG_BITS == 64) {
            if (val == 0xffffffffu) {
                tcg_out_ext32u(s, r0, r0);
                return;
            }
            if (val == (uint32_t)val) {
                /* AND with no high bits set can use a 32-bit operation.  */
                rexw = 0;
            }
        }

> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index 207a89f..88575e7 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -2124,7 +2124,11 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, 
> TCGv_i64 arg1,
>    uint64_t mask = (1ull << len) - 1;
>    TCGv_i64 t1 = tcg_temp_new_i64 ();
>  
> -  tcg_gen_andi_i64(t1, arg2, mask);
> +  if (len == 32) {
> +       tcg_gen_ext32u_i64(t1, arg2);
> +  } else {
> +      tcg_gen_andi_i64(t1, arg2, mask);
> +  }
>    tcg_gen_shli_i64(t1, t1, ofs);
>    tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
>    tcg_gen_or_i64(ret, ret, t1);
> -- 
> 1.6.0.2
> 
> 
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net