[Qemu-devel] Re: [PATCH] ioapic: when switches to level trigger mode, interrupts raised repeatedly.

[Jan Kiszka]

On 2011-04-04 04:15, Isaku Yamahata wrote:
> On Mon, Apr 04, 2011 at 08:42:07AM +0900, Isaku Yamahata wrote:
>> > Thank you for applying. But I found that the patch is wrong and
>> > I'm preparing the new one. Can you please revert it?
> Here is the corrected patch. The first wrong patch clears the interrupts
> bit unconditionally. Which caused losing interrupt.
> 
> From 5ed177d35ab14f3b070a0eba2c49400279a3a14b Mon Sep 17 00:00:00 2001
> Message-Id: <address@hidden>
> In-Reply-To: <address@hidden>
> References: <address@hidden>
> From: Isaku Yamahata <address@hidden>
> Date: Wed, 16 Mar 2011 14:00:13 +0900
> Subject: [PATCH 01/30] ioapic: when switches to level trigger mode, 
> interrupts raised repeatedly.
> 
> - the trigger mode is edge at first by reset.
> - During initializatoin, the interrupt is raised as edge which is masked.
>   The corresponding bit of irr is set.

...and that is the actual problem. The spec says: "Interrupt Mask—R/W.
When this bit is 1, the interrupt signal is masked. Edge-sensitive
interrupts signaled on a masked interrupt pin are ignored (i.e., not
delivered or held pending)."

So this should do the trick in a correct way (untested, please
validate):

diff --git a/hw/ioapic.c b/hw/ioapic.c
index 569327d..6663f41 100644
--- a/hw/ioapic.c
+++ b/hw/ioapic.c
@@ -161,7 +161,7 @@ static void ioapic_set_irq(void *opaque, int vector, int 
level)
             }
         } else {
             /* edge triggered */
-            if (level) {
+            if (level && !(entry & IOAPIC_LVT_MASKED)) {
                 s->irr |= mask;
                 ioapic_service(s);
             }

Jan

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