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[Qemu-devel] [PATCH 18/33] target-alpha: Add various symbolic constants.
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 18/33] target-alpha: Add various symbolic constants. |
Date: |
Thu, 28 Apr 2011 13:51:00 -0700 |
The EXC_M_* constants were being set for the EV6, not as set for
the Unix kernel entry point.
Use PS_USER_MODE instead of hard-coding access to the PS register.
Signed-off-by: Richard Henderson <address@hidden>
---
target-alpha/cpu.h | 56 +++++++++++++++++++++++++++++++++++----------
target-alpha/translate.c | 2 +-
2 files changed, 44 insertions(+), 14 deletions(-)
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 7e4c46f..50a8109 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -290,11 +290,6 @@ struct CPUAlphaState {
#define cpu_gen_code cpu_alpha_gen_code
#define cpu_signal_handler cpu_alpha_signal_handler
-static inline int cpu_mmu_index (CPUState *env)
-{
- return (env->ps >> 3) & 1;
-}
-
#include "cpu-all.h"
enum {
@@ -321,14 +316,49 @@ enum {
EXCP_STQ_C,
};
-/* Arithmetic exception */
-#define EXC_M_IOV (1<<16) /* Integer Overflow */
-#define EXC_M_INE (1<<15) /* Inexact result */
-#define EXC_M_UNF (1<<14) /* Underflow */
-#define EXC_M_FOV (1<<13) /* Overflow */
-#define EXC_M_DZE (1<<12) /* Division by zero */
-#define EXC_M_INV (1<<11) /* Invalid operation */
-#define EXC_M_SWC (1<<10) /* Software completion */
+/* Hardware interrupt (entInt) constants. */
+enum {
+ INT_K_IP,
+ INT_K_CLK,
+ INT_K_MCHK,
+ INT_K_DEV,
+ INT_K_PERF,
+};
+
+/* Memory management (entMM) constants. */
+enum {
+ MM_K_TNV,
+ MM_K_ACV,
+ MM_K_FOR,
+ MM_K_FOE,
+ MM_K_FOW
+};
+
+/* Arithmetic exception (entArith) constants. */
+enum {
+ EXC_M_SWC = 1, /* Software completion */
+ EXC_M_INV = 2, /* Invalid operation */
+ EXC_M_DZE = 4, /* Division by zero */
+ EXC_M_FOV = 8, /* Overflow */
+ EXC_M_UNF = 16, /* Underflow */
+ EXC_M_INE = 32, /* Inexact result */
+ EXC_M_IOV = 64 /* Integer Overflow */
+};
+
+/* Processor status constants. */
+enum {
+ /* Low 3 bits are interrupt mask level. */
+ PS_INT_MASK = 7,
+
+ /* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes;
+ The Unix PALcode only uses bit 4. */
+ PS_USER_MODE = 8
+};
+
+static inline int cpu_mmu_index (CPUState *env)
+{
+ return (env->ps & PS_USER_MODE) != 0;
+}
enum {
IR_V0 = 0,
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 09edb0f..42a80e6 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3359,7 +3359,7 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model)
env->amask = amask;
#if defined (CONFIG_USER_ONLY)
- env->ps = 1 << 3;
+ env->ps = PS_USER_MODE;
cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD
| FPCR_UNFD | FPCR_INED | FPCR_DNOD));
#else
--
1.7.4.4
- [Qemu-devel] [PATCH 10/33] target-alpha: Cleanup MMU modes., (continued)
- [Qemu-devel] [PATCH 10/33] target-alpha: Cleanup MMU modes., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 09/33] target-alpha: Rationalize internal processor registers., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 11/33] target-alpha: Fixup translation of PALmode instructions., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 13/33] target-alpha: Tidy up arithmetic exceptions., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 14/33] target-alpha: Use do_restore_state for arithmetic exceptions., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 15/33] target-alpha: Merge HW_REI and HW_RET implementations., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 12/33] target-alpha: Add IPRs to be used by the emulation PALcode., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 16/33] target-alpha: Implement do_interrupt for system mode., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 17/33] target-alpha: Swap shadow registers moving to/from PALmode., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 19/33] target-alpha: Use kernel mmu_idx for pal_mode., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 18/33] target-alpha: Add various symbolic constants.,
Richard Henderson <=
- [Qemu-devel] [PATCH 21/33] target-alpha: Disable interrupts properly., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 20/33] target-alpha: All ISA checks to use TB->FLAGS., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 22/33] target-alpha: Implement more CALL_PAL values inline., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 23/33] target-alpha: Implement cpu_alpha_handle_mmu_fault for system mode., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 24/33] target-alpha: Remap PIO space for 43-bit KSEG for EV6., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 25/33] target-alpha: Trap for unassigned and unaligned addresses., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 26/33] target-alpha: Include the PCC_OFS in the RPCC return value., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 27/33] target-alpha: Use a fixed frequency for the RPCC in system mode., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 28/33] target-alpha: Implement TLB flush primitives., Richard Henderson, 2011/04/28
- [Qemu-devel] [PATCH 31/33] target-alpha: Implement WAIT IPR., Richard Henderson, 2011/04/28