[Qemu-devel] [PATCH 1/3](Corrected version) linux-user:Support for MIPS64 user mode emulation in QEMU

[Khansa Butt]

From 52cca3fab46f65b493cd21096389ee459279cbb2 Mon Sep 17 00:00:00 2001

From: Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt <address@hidden>

Date: Fri, 29 Apr 2011 11:48:54 +0500

Subject: [PATCH 1/3] linux-user:Support for MIPS64 user mode emulation in QEMU

Signed-off-by: Khansa Butt <address@hidden>

---

 configure                             |    1 +

 default-configs/mips64-linux-user.mak |    1 +

 linux-user/main.c                     |   26 +++++++++++++++++++++++++-

 linux-user/mips64/syscall.h           |    3 +++

 linux-user/signal.c                   |    2 --

 linux-user/syscall.c                  |    5 +++++

 target-mips/mips-defs.h               |    2 ++

 target-mips/translate.c               |    1 +

 target-mips/translate_init.c          |   26 ++++++++++++++++++++++++++

 9 files changed, 64 insertions(+), 3 deletions(-)

 create mode 100644 default-configs/mips64-linux-user.mak

diff --git a/configure b/configure

index de44bac..631417b 100755

--- a/configure

+++ b/configure

@@ -1043,6 +1043,7 @@ m68k-linux-user \

 microblaze-linux-user \

 microblazeel-linux-user \

 mips-linux-user \

+mips64-linux-user \

 mipsel-linux-user \

 ppc-linux-user \

 ppc64-linux-user \

diff --git a/default-configs/mips64-linux-user.mak b/default-configs/mips64-linux-user.mak

new file mode 100644

index 0000000..1598bfc

--- /dev/null

+++ b/default-configs/mips64-linux-user.mak

@@ -0,0 +1 @@

+# Default configuration for mips64-linux-user

diff --git a/linux-user/main.c b/linux-user/main.c

index a1e37e4..253e796 100644

--- a/linux-user/main.c

+++ b/linux-user/main.c

@@ -2014,6 +2014,14 @@ static int do_store_exclusive(CPUMIPSState *env)

     int d;

 

     addr = env->lladdr;

+#if defined(TARGET_MIPS64)

+/* For MIPS64 on 32 bit host there is a need to make

+* the page accessible to which the above 'addr' is belonged */

+#if HOST_LONG_BITS == 32

+    int flag = PAGE_VALID | PAGE_READ | PAGE_WRITE | PAGE_WRITE_ORG;

+    page_set_flags(addr, addr + 4096, flag);

+#endif

+#endif

     page_addr = addr & TARGET_PAGE_MASK;

     start_exclusive();

     mmap_lock();

@@ -2055,7 +2063,8 @@ static int do_store_exclusive(CPUMIPSState *env)

 void cpu_loop(CPUMIPSState *env)

 {

     target_siginfo_t info;

-    int trapnr, ret;

+    int trapnr;

+    abi_long ret;

     unsigned int syscall_num;

 

     for(;;) {

@@ -2064,6 +2073,20 @@ void cpu_loop(CPUMIPSState *env)

         cpu_exec_end(env);

         switch(trapnr) {

         case EXCP_SYSCALL:

+#if defined(TARGET_MIPS64)

+            syscall_num = env->active_tc.gpr[2] - 5000;

+            env->active_tc.PC += 4;

+            /* MIPS64 has eight argument registers so there is

+             * no need to get arguments from stack

+             */

+            ret = do_syscall(env, env->active_tc.gpr[2],

+                             env->active_tc.gpr[4],

+                             env->active_tc.gpr[5],

+                             env->active_tc.gpr[6],

+                             env->active_tc.gpr[7],

+                             env->active_tc.gpr[8],

+                             env->active_tc.gpr[9]);

+#else

             syscall_num = env->active_tc.gpr[2] - 4000;

             env->active_tc.PC += 4;

             if (syscall_num >= sizeof(mips_syscall_args)) {

@@ -2092,6 +2115,7 @@ void cpu_loop(CPUMIPSState *env)

                                  env->active_tc.gpr[7],

                                  arg5, arg6/*, arg7, arg8*/);

             }

+#endif

             if (ret == -TARGET_QEMU_ESIGRETURN) {

                 /* Returning from a successful sigreturn syscall.

                    Avoid clobbering register state.  */

diff --git a/linux-user/mips64/syscall.h b/linux-user/mips64/syscall.h

index 668a2b9..ec65653 100644

--- a/linux-user/mips64/syscall.h

+++ b/linux-user/mips64/syscall.h

@@ -218,4 +218,7 @@ struct target_pt_regs {

 

 

 

+/* Nasty hack: define a fake errno value for use by sigreturn.  */

+#define TARGET_QEMU_ESIGRETURN 255

+

 #define UNAME_MACHINE "mips64"

diff --git a/linux-user/signal.c b/linux-user/signal.c

index ce033e9..66786db 100644

--- a/linux-user/signal.c

+++ b/linux-user/signal.c

@@ -2413,8 +2413,6 @@ void sparc64_get_context(CPUSPARCState *env)

 #endif

 #elif defined(TARGET_ABI_MIPSN64)

 

-# warning signal handling not implemented

-

 static void setup_frame(int sig, struct target_sigaction *ka,

  target_sigset_t *set, CPUState *env)

 {

diff --git a/linux-user/syscall.c b/linux-user/syscall.c

index bb0999d..cfa925e 100644

--- a/linux-user/syscall.c

+++ b/linux-user/syscall.c

@@ -7320,6 +7320,11 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,

     case TARGET_NR_set_thread_area:

 #if defined(TARGET_MIPS)

       ((CPUMIPSState *) cpu_env)->tls_value = arg1;

+      if (((CPUMIPSState *) cpu_env)->insn_flags & CPU_OCTEON) {

+          /* tls entry is moved to k0 so that this can be used later

+             currently this thing is tested only for Octeon */

+          ((CPUMIPSState *) cpu_env)->active_tc.gpr[26] = arg1;

+      }

       ret = 0;

       break;

 #elif defined(TARGET_CRIS)

diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h

index bf094a3..a93e863 100644

--- a/target-mips/mips-defs.h

+++ b/target-mips/mips-defs.h

@@ -44,6 +44,7 @@

 #define INSN_LOONGSON2E  0x20000000

 #define INSN_LOONGSON2F  0x40000000

 #define INSN_VR54XX 0x80000000

+#define INSN_OCTEON 0x10000000

 

 /* MIPS CPU defines. */

 #define CPU_MIPS1 (ISA_MIPS1)

@@ -53,6 +54,7 @@

 #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)

 #define CPU_LOONGSON2E  (CPU_MIPS3 | INSN_LOONGSON2E)

 #define CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F)

+#define CPU_OCTEON      (CPU_MIPS64R2 | INSN_OCTEON)

 

 #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)

 

diff --git a/target-mips/translate.c b/target-mips/translate.c

index 4eaa826..c88c3f9 100644

--- a/target-mips/translate.c

+++ b/target-mips/translate.c

@@ -12694,6 +12694,7 @@ void cpu_reset (CPUMIPSState *env)

         env->hflags |= MIPS_HFLAG_FPU;

     }

 #ifdef TARGET_MIPS64

+    env->hflags |=  MIPS_HFLAG_UX;

     if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {

         env->hflags |= MIPS_HFLAG_F64;

     }

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c

index 590e092..6a18995 100644

--- a/target-mips/translate_init.c

+++ b/target-mips/translate_init.c

@@ -451,6 +451,32 @@ static const mips_def_t mips_defs[] =

         .mmu_type = MMU_TYPE_R4000,

     },

     {

+        /* XXX: We will add some more features related to

+           Octeon's coprocessors */

+        .name = "octeon",

+        .CP0_PRid = 0x0d30,

+        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |

+                       (MMU_TYPE_R4000 << CP0C0_MT),

+        .CP0_Config1 = MIPS_CONFIG1 | (63 << CP0C1_MMU) |

+                       (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |

+                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |

+                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),

+         .CP0_Config2 = MIPS_CONFIG2,

+         .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),

+         .CP0_LLAddr_rw_bitmask = 0,

+         .CP0_LLAddr_shift = 0,

+         .SYNCI_Step = 32,

+         .CCRes = 2,

+         .CP0_Status_rw_bitmask = 0x36FBFFFF,

+         .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |

+                     (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |

+                     (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),

+         .SEGBITS = 49,

+         .PABITS = 49,

+         .insn_flags = CPU_OCTEON | ASE_MIPS3D,

+         .mmu_type = MMU_TYPE_R4000,

+    },

+    {

         .name = "Loongson-2E",

         .CP0_PRid = 0x6302,

         /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/

-- 

1.7.3.4