[Qemu-devel] xtensa: new target architecture for qemu

[Max Filippov]

Hello.

I'm developing support for new qemu target architecture: xtensa [1],
primarily because AFAIK there's no free/open simulator for this
architecture.

Essential ISA parts (like core opcodes, special registers, windowed
registers, exceptions and interrupts) are implemented, other (like
TLB, MMU, caches, coprocessors, rare opcodes) are not, although I'm
planning to implement them if/when needed.

I'm wondering if this target could be eligible for inclusion into qemu mainline.
If it is, could anyone please review the code [2]?

There are several known issues which I'm planning to address:
- mixed coding style;
- no copyrights/license (it is BSD);
- no direct TB linking;
- dummy cpu_halted/cpu_has_work.

If you see more, please report, especially if you know how to fix them (:

[1] http://en.wikipedia.org/wiki/Tensilica
[2] 
http://jcmvbkbc.spb.ru/git/?p=dumb/qemu-xtensa.git;a=shortlog;h=refs/heads/xtensa

Thanks.
-- Max