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[Qemu-devel] [RFC 04/28] target-xtensa: implement narrow instructions
From: |
Max Filippov |
Subject: |
[Qemu-devel] [RFC 04/28] target-xtensa: implement narrow instructions |
Date: |
Wed, 4 May 2011 04:59:04 +0400 |
Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long.
Signed-off-by: Max Filippov <address@hidden>
---
target-xtensa/translate.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 57 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 16efcfd..26fc28b 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -301,22 +301,79 @@ static void disas_xtensa_insn(DisasContext *dc)
case 7: /*B*/
break;
+#define gen_narrow_load_store(type) do { \
+ TCGv_i32 addr = tcg_temp_new_i32(); \
+ tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
+ tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, 0); \
+ tcg_temp_free(addr); \
+ } while (0)
+
case 8: /*L32I.Nn*/
+ gen_narrow_load_store(ld32u);
break;
case 9: /*S32I.Nn*/
+ gen_narrow_load_store(st32);
break;
+#undef gen_narrow_load_store
case 10: /*ADD.Nn*/
+ tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
break;
case 11: /*ADDI.Nn*/
+ tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
break;
case 12: /*ST2n*/
+ if (RRRN_T < 8) { /*MOVI.Nn*/
+ tcg_gen_movi_i32(cpu_R[RRRN_S],
+ RRRN_R | (RRRN_T << 4) |
+ ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
+ } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
+ int label = gen_new_label();
+ int inv = RRRN_T & 4;
+
+ tcg_gen_brcondi_i32(inv ? TCG_COND_EQ : TCG_COND_NE,
+ cpu_R[RRRN_S], 0, label);
+ gen_jumpi(dc, dc->pc + 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
+ gen_set_label(label);
+ gen_jumpi(dc, dc->pc + 2);
+ }
break;
case 13: /*ST3n*/
+ switch (RRRN_R) {
+ case 0: /*MOV.Nn*/
+ tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
+ break;
+
+ case 15: /*S3*/
+ switch (RRRN_T) {
+ case 0: /*RET.Nn*/
+ gen_jump(dc, cpu_R[0]);
+ break;
+
+ case 1: /*RETW.Nn*/
+ break;
+
+ case 2: /*BREAK.Nn*/
+ break;
+
+ case 3: /*NOP.Nn*/
+ break;
+
+ case 6: /*ILL.Nn*/
+ break;
+
+ default: /*reserved*/
+ break;
+ }
+ break;
+
+ default: /*reserved*/
+ break;
+ }
break;
default: /*reserved*/
--
1.7.3.4
- [Qemu-devel] [RFC 01/28] target-xtensa: add target stubs, Max Filippov, 2011/05/03
- [Qemu-devel] [RFC 02/28] target-xtensa: add target to the configure script, Max Filippov, 2011/05/03
- [Qemu-devel] [RFC 03/28] target-xtensa: implement disas_xtensa_insn, Max Filippov, 2011/05/03
- [Qemu-devel] [RFC 04/28] target-xtensa: implement narrow instructions,
Max Filippov <=
- [Qemu-devel] [RFC 05/28] target-xtensa: implement RT0 group, Max Filippov, 2011/05/03
- [Qemu-devel] [RFC 06/28] target-xtensa: add sample board, Max Filippov, 2011/05/03
- [Qemu-devel] [RFC 07/28] target-xtensa: add gdb support, Max Filippov, 2011/05/03
- [Qemu-devel] [RFC 08/28] target-xtensa: implement conditional jumps, Max Filippov, 2011/05/03
- [Qemu-devel] [RFC 09/28] target-xtensa: implement JX/RET0/CALLX, Max Filippov, 2011/05/03
- [Qemu-devel] [RFC 10/28] target-xtensa: add special and user registers, Max Filippov, 2011/05/03
- [Qemu-devel] [RFC 11/28] target-xtensa: implement RST3 group, Max Filippov, 2011/05/03
- [Qemu-devel] [RFC 12/28] target-xtensa: implement shifts (ST1 and RST1 groups), Max Filippov, 2011/05/03