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Re: [Qemu-devel] [RFC 20/28] target-xtensa: implement windowed registers
From: |
Blue Swirl |
Subject: |
Re: [Qemu-devel] [RFC 20/28] target-xtensa: implement windowed registers |
Date: |
Wed, 4 May 2011 22:35:01 +0300 |
On Wed, May 4, 2011 at 3:59 AM, Max Filippov <address@hidden> wrote:
> See ISA, 4.7.1 for details.
>
> Physical registers and currently visible window are separate fields in
> CPUEnv. Only current window is accessible to TCG. On operations that
> change window base helpers copy current window to and from physical
> registers.
I'm not sure how the register windows work, but maybe you could use
the same trick used for Sparc. There is a pool of registers
(env->regbase[]), a register window pointer (env->regwptr,
cpu_regwptr) tracks which are the currently accessible ones. The
advantage is to avoid copying (not entirely for Sparc due to the
window overlap).
- [Qemu-devel] [RFC 17/28] target-xtensa: implement CACHE group, (continued)
[Qemu-devel] [RFC 19/28] target-xtensa: implement RST2 group (32 bit mul/div/rem), Max Filippov, 2011/05/03
[Qemu-devel] [RFC 20/28] target-xtensa: implement windowed registers, Max Filippov, 2011/05/03
- Re: [Qemu-devel] [RFC 20/28] target-xtensa: implement windowed registers,
Blue Swirl <=
[Qemu-devel] [RFC 21/28] target-xtensa: implement loop option, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 22/28] target-xtensa: implement extended L32R, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 23/28] target-xtensa: implement unaligned exception option, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 24/28] target-xtensa: implement SIMCALL, Max Filippov, 2011/05/03
[Qemu-devel] [RFC 25/28] target-xtensa: implement interrupt option, Max Filippov, 2011/05/03