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Re: [Qemu-devel] TCG: AREG0 removal planning
From: |
Paul Brook |
Subject: |
Re: [Qemu-devel] TCG: AREG0 removal planning |
Date: |
Tue, 10 May 2011 23:57:17 +0100 |
User-agent: |
KMail/1.13.5 (Linux/2.6.38-2-amd64; KDE/4.4.5; x86_64; ; ) |
> While we're at it, let us change things a bit further to allow guest
> byte-swap load/store insns to be implemented more efficiently. For
> instance, currently a sparc load_asr (little-endian), as emulated on
> an x86 host, does the byte swap twice.
FWIW this also ends up interacting with the device and bus models. This is
partially implemented by the endian parameter of cpu_register_io_memory et.
al. This may also be a runtime property, either part of the CPU state (e.g.
ARM where instruction and data accesses may have different endianness), or
even a per-page TLB attribute (PPC?).
Paul
Re: [Qemu-devel] TCG: AREG0 removal planning, Stefan Weil, 2011/05/10
Re: [Qemu-devel] TCG: AREG0 removal planning, Richard Henderson, 2011/05/10