Re: [Qemu-devel] [RFC] Memory API

[Gleb Natapov]

On Sun, May 22, 2011 at 11:09:08AM +0300, Avi Kivity wrote:
> On 05/22/2011 11:06 AM, Gleb Natapov wrote:
> >On Sun, May 22, 2011 at 10:37:48AM +0300, Avi Kivity wrote:
> >>  On 05/20/2011 02:57 PM, Gleb Natapov wrote:
> >>  >On Fri, May 20, 2011 at 11:59:58AM +0300, Avi Kivity wrote:
> >>  >>   On 05/19/2011 07:27 PM, Gleb Natapov wrote:
> >>  >>   >>    Think of how a window manager folds windows with priorities 
> >> onto a
> >>  >>   >>    flat framebuffer.
> >>  >>   >>
> >>  >>   >>    You do a depth-first walk of the tree.  For each child list, 
> >> you
> >>  >>   >>    iterate it from the lowest to highest priority, allowing later
> >>  >>   >>    subregions override earlier subregions.
> >>  >>   >>
> >>  >>   >I do not think that window manager is a good analogy. Window can
> >>  >>   >overlap with only its siblings. In our memory tree each final node 
> >> may
> >>  >>   >overlap with any other node in the tree.
> >>  >>   >
> >>  >>
> >>  >>   Transparent windows.
> >>  >>
> >>  >No, still not that. Think about child windows that resides outside of its
> >>  >parent windows on screen. In our memory region terms think about PCI BAR
> >>  >is registered to overlap with RAM at address 0x1000 for instance. PCI
> >>  >BAR memory region and RAM memory region are on very different branches
> >>  >of the global tree.
> >>
> >>  Right.  But what's the problem with that?
> >>
> >None, unless you want to make PCI BAR visible at address 0x1000 (like what
> >will happen today) the case above.
> 
> There is no problem.  If the PCI bus priority is higher than RAM
> priority, then PCI BARs will override RAM.
> 
So if memory region has no subregion that covers part of the region
lower prio region is used? Now the same with the pictures:

-- root
  -- PCI 0x00000 - 0x2ffff (prio 0)
    -- BAR A 0x1000 - 0x1fff
    -- BAR B 0x20000 - 0x20fff
  -- RAM 0x00000 - 0x1ffff (prio 1)
  
In the tree above at address 0x0 PCI has higher priority, but since
there is no subregion at this range next prio region is used instead
(RAM). Is this correct? If yes how core knows that container is
transparent like that (RAM container is not)?

> >>  Which one takes precedence is determined by the priorities of the
> >>  RAM subregion vs. the PCI bus subregion.
> >>
> >Yes, and that is why PCI subsystem or platform code can't directly uses
> >memory API to register PCI memory region/RAM memory region respectively,
> >because they wouldn't know what priorities to specify. Only chipset code
> >knows, so the RAM/PCI memory registration should go through chipset
> >code,
> 
> Correct.  Chipset code creates RAM and PCI regions, and gives the
> PCI region to the PCI bus.  Devices give BAR subregions to the PCI
> bus.  The PCI bus does the registration.
OK. What happens if device tries to create subregion outside of PCI
region provided by chipset to PCI bus?

> 
> >  but even chipset code doesn't know everything. It knows nothing
> >about cpu local memory regions for instance, so all registrations should
> >go through system bus in the end. Is this how API suppose to be used?
> 
> Yes.  Every point where a decision is made on how to route memory
> accesses is a modelled as a container node.
> 
Excellent. I would argue that this is exactly the point where an
overlapping can be resolved too :)

--
                        Gleb.