Re: [Qemu-devel] Disable interrupts on Cortex M3 (lm3s6965evb)

[Peter Maydell]

On 5 June 2011 15:17, Sebastian Huber
<address@hidden> wrote:
> On 05/06/11 15:44, Peter Maydell wrote:

>> In any case, M profile exception priority handling is sufficiently
>> complicated that any change which only looks at PRIMASK (which is
>> effectively what the change to look at CPSR_I here is doing) is
>> almost certainly wrong. I think that whatever is raising the
>> interrupt should be looking at the CPU priority and not raising it
>> in the first place.

> Yes.  Please have a look at:
>
> http://lists.nongnu.org/archive/html/qemu-devel/2011-05/msg03132.html

That patch does correct an error in the decode of the basepri
registers (and so we might as well apply it), but it does not
affect the fact that the underlying v7m.basepri field is not
actually used for anything.

>> (It looks suspiciously as if most of the v7M priority handling
>> is simply missing from QEMU, ie you have bigger problems than
>> can be fixed by a small patch like this...)

> Yes, but the current behaviour is definitely not right.  Since the
> PRIMASK is mapped to the I bit in the CPSR I guessed that this was the
> right place to fix it.

I agree that the current behaviour is not right. However, to fix
this problem you need to work on a larger scale than attempting
to apply two line patches which fix your particular use case.

-- PMM