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[Qemu-devel] [PATCH 6/6] mips: eabi syscall support for 64-bit args


From: Wesley W. Terpstra
Subject: [Qemu-devel] [PATCH 6/6] mips: eabi syscall support for 64-bit args
Date: Fri, 8 Jul 2011 15:08:28 +0200

mips uses the eabi calling convention. For 64-bit values this means
some registers are skipped. This patch replicates the behaviour of
arm/eabi for mips targets.
This affects ftruncate64, creating insane sized fails (or just failing).

Signed-off-by: Wesley W. Terpstra <address@hidden>
---

diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index fed7a8f..0b0a3d0 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -4367,6 +4367,10 @@
         arg3 = arg4;
       }
 #endif
+#ifdef TARGET_MIPS
+    arg2 = arg3;
+    arg3 = arg4;
+#endif
     return get_errno(truncate64(arg1, target_offset64(arg2, arg3)));
 }
 #endif
@@ -4384,6 +4388,10 @@
         arg3 = arg4;
       }
 #endif
+#ifdef TARGET_MIPS
+    arg2 = arg3;
+    arg3 = arg4;
+#endif
     return get_errno(ftruncate64(arg1, target_offset64(arg2, arg3)));
 }
 #endif
@@ -6841,6 +6849,9 @@
         if (((CPUARMState *)cpu_env)->eabi)
             arg4 = arg5;
 #endif
+#ifdef TARGET_MIPS
+        arg4 = arg5;
+#endif
         if (!(p = lock_user(VERIFY_WRITE, arg2, arg3, 0)))
             goto efault;
         ret = get_errno(pread(arg1, p, arg3, arg4));
@@ -6851,6 +6862,9 @@
         if (((CPUARMState *)cpu_env)->eabi)
             arg4 = arg5;
 #endif
+#ifdef TARGET_MIPS
+        arg4 = arg5;
+#endif
         if (!(p = lock_user(VERIFY_READ, arg2, arg3, 1)))
             goto efault;
         ret = get_errno(pwrite(arg1, p, arg3, arg4));
@@ -7609,6 +7623,11 @@
             arg4 = arg5;
         }
 #endif
+#ifdef TARGET_MIPS
+        arg2 = arg3;
+        arg3 = arg4;
+        arg4 = arg5;
+#endif
         ret = get_errno(readahead(arg1, ((off64_t)arg3 << 32) | arg2, arg4));
 #else
         ret = get_errno(readahead(arg1, arg2, arg3));

Attachment: 05-mips-eabi.patch
Description: Text Data


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