Re: [Qemu-devel] [PATCH] pci: Length-align config space accesses

[Michael S. Tsirkin]

On Wed, Jul 20, 2011 at 04:36:51PM +0200, Jan Kiszka wrote:
> > A 4 byte access at address 255 would wrap around to 0 with this,
> > while previously we ignored high bits on write and returned
> > 0 on read.
> 
> The question is rather what the spec or real hw demand from us. Do you
> have any insights on this? I didn't find hints which behavior is more
> compliant. It looks like such access patterns are deep into bug land anyway.

For the express side, we don't need to support accesses that cross a 4
byte boundary - but guests might be able to generate them.
Just in case, I'd prefer keeping the current behaviour WRT that.
Paul, do you know which guests can do this?

However, as far as I can tell accesses within a dword can have
any bytes enabled. So our interface for passing that info to
devices isn't all that good, and I'm not 100% sure splitting
up to length aligned transactions is better.
Maybe passing in a byte_enable mask is a better idea.


For example, as far as I an tell sysfs let you write/read
any length (it splits it up internally ATM) so
it seems somewhat useless to do that work in
userspace as well.
We will, however, have to see how does the code look in the end.



-- 
MST