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[Qemu-devel] [PATCH v2 18/31] target-xtensa: implement RST2 group (32 bi
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH v2 18/31] target-xtensa: implement RST2 group (32 bit mul/div/rem) |
Date: |
Sun, 24 Jul 2011 21:10:56 +0400 |
Signed-off-by: Max Filippov <address@hidden>
---
target-xtensa/translate.c | 60 ++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 59 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 1fe212d..52a76e1 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -878,7 +878,65 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 2: /*RST2*/
- TBD();
+ if (_OP2 >= 12) {
+ HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
+ int label = gen_new_label();
+ tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
+ gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
+ gen_set_label(label);
+ }
+
+ switch (_OP2) {
+ case 8: /*MULLi*/
+ HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
+ tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
+
+ case 10: /*MULUHi*/
+ case 11: /*MULSHi*/
+ HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
+ {
+ TCGv_i64 r = tcg_temp_new_i64();
+ TCGv_i64 s = tcg_temp_new_i64();
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ if (_OP2 == 10) {
+ tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
+ tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
+ } else {
+ tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
+ tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
+ }
+ tcg_gen_mul_i64(r, s, t);
+ tcg_gen_shri_i64(r, r, 32);
+ tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
+
+ tcg_temp_free_i64(r);
+ tcg_temp_free_i64(s);
+ tcg_temp_free_i64(t);
+ }
+ break;
+
+ case 12: /*QUOUi*/
+ tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
+
+ case 13: /*QUOSi*/
+ tcg_gen_div_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
+
+ case 14: /*REMUi*/
+ tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
+
+ case 15: /*REMSi*/
+ tcg_gen_rem_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
+
+ default: /*reserved*/
+ RESERVED();
+ break;
+ }
break;
case 3: /*RST3*/
--
1.7.3.4
- [Qemu-devel] [PATCH v2 05/31] target-xtensa: implement RT0 group, (continued)
- [Qemu-devel] [PATCH v2 05/31] target-xtensa: implement RT0 group, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 06/31] target-xtensa: add sample board, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 07/31] target-xtensa: implement conditional jumps, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 08/31] target-xtensa: implement JX/RET0/CALLX, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 09/31] target-xtensa: add special and user registers, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 10/31] target-xtensa: implement RST3 group, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 13/31] target-xtensa: mark reserved and TBD opcodes, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 15/31] target-xtensa: implement CACHE group, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 17/31] target-xtensa: implement exceptions, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 16/31] target-xtensa: add PS register and access control, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 18/31] target-xtensa: implement RST2 group (32 bit mul/div/rem),
Max Filippov <=
- [Qemu-devel] [PATCH v2 20/31] target-xtensa: implement loop option, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 21/31] target-xtensa: implement extended L32R, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 23/31] target-xtensa: implement SIMCALL, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 22/31] target-xtensa: implement unaligned exception option, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 25/31] target-xtensa: implement accurate window check, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 26/31] target-xtensa: implement CPENABLE and PRID SRs, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 24/31] target-xtensa: implement interrupt option, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 28/31] target-xtensa: add gdb support, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 30/31] target-xtensa: add dc232b core and board, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 27/31] target-xtensa: implement relocatable vectors, Max Filippov, 2011/07/24