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[Qemu-devel] [PATCH v2 26/31] target-xtensa: implement CPENABLE and PRID
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH v2 26/31] target-xtensa: implement CPENABLE and PRID SRs |
Date: |
Sun, 24 Jul 2011 21:11:04 +0400 |
Signed-off-by: Max Filippov <address@hidden>
---
hw/xtensa_sample.c | 1 +
target-xtensa/cpu.h | 2 ++
target-xtensa/translate.c | 7 +++++++
3 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/xtensa_sample.c b/hw/xtensa_sample.c
index 9f7733b..c2ad48a 100644
--- a/hw/xtensa_sample.c
+++ b/hw/xtensa_sample.c
@@ -51,6 +51,7 @@ static void xtensa_init(ram_addr_t ram_size,
exit(1);
}
qemu_register_reset(xtensa_sample_reset, env);
+ env->sregs[PRID] = n;
}
ram_offset = qemu_ram_alloc(NULL, "xtensa.dram", 0x10000);
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 9a805d4..a1d4e6d 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -118,12 +118,14 @@ enum {
DEPC = 192,
EPS2 = 194,
EXCSAVE1 = 209,
+ CPENABLE = 224,
INTSET = 226,
INTCLEAR = 227,
INTENABLE = 228,
PS = 230,
EXCCAUSE = 232,
CCOUNT = 234,
+ PRID = 235,
EXCVADDR = 238,
CCOMPARE = 240,
};
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 6d6ad1b..83e4a4f 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -101,12 +101,14 @@ static const char * const sregnames[256] = {
[EXCSAVE1 + 4] = "EXCSAVE5",
[EXCSAVE1 + 5] = "EXCSAVE6",
[EXCSAVE1 + 6] = "EXCSAVE7",
+ [CPENABLE] = "CPENABLE",
[INTSET] = "INTSET",
[INTCLEAR] = "INTCLEAR",
[INTENABLE] = "INTENABLE",
[PS] = "PS",
[EXCCAUSE] = "EXCCAUSE",
[CCOUNT] = "CCOUNT",
+ [PRID] = "PRID",
[EXCVADDR] = "EXCVADDR",
[CCOMPARE] = "CCOMPARE0",
[CCOMPARE + 1] = "CCOMPARE1",
@@ -447,6 +449,10 @@ static void gen_wsr_ps(DisasContext *dc, uint32_t sr,
TCGv_i32 v)
gen_jumpi_check_loop_end(dc, -1);
}
+static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+{
+}
+
static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
TCGv_i32 id = tcg_const_i32(sr - CCOMPARE);
@@ -469,6 +475,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32
s)
[WINDOW_BASE] = gen_wsr_windowbase,
[WINDOW_START] = gen_wsr_windowstart,
[PS] = gen_wsr_ps,
+ [PRID] = gen_wsr_prid,
[CCOMPARE] = gen_wsr_ccompare,
[CCOMPARE + 1] = gen_wsr_ccompare,
[CCOMPARE + 2] = gen_wsr_ccompare,
--
1.7.3.4
- [Qemu-devel] [PATCH v2 13/31] target-xtensa: mark reserved and TBD opcodes, (continued)
- [Qemu-devel] [PATCH v2 13/31] target-xtensa: mark reserved and TBD opcodes, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 15/31] target-xtensa: implement CACHE group, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 17/31] target-xtensa: implement exceptions, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 16/31] target-xtensa: add PS register and access control, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 18/31] target-xtensa: implement RST2 group (32 bit mul/div/rem), Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 20/31] target-xtensa: implement loop option, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 21/31] target-xtensa: implement extended L32R, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 23/31] target-xtensa: implement SIMCALL, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 22/31] target-xtensa: implement unaligned exception option, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 25/31] target-xtensa: implement accurate window check, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 26/31] target-xtensa: implement CPENABLE and PRID SRs,
Max Filippov <=
- [Qemu-devel] [PATCH v2 24/31] target-xtensa: implement interrupt option, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 28/31] target-xtensa: add gdb support, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 30/31] target-xtensa: add dc232b core and board, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 27/31] target-xtensa: implement relocatable vectors, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 31/31] MAINTAINERS: add xtensa maintainer, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 29/31] target-xtensa: implement memory protection options, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 11/31] target-xtensa: implement shifts (ST1 and RST1 groups), Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 14/31] target-xtensa: implement SYNC group, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 12/31] target-xtensa: implement LSAI group, Max Filippov, 2011/07/24
- [Qemu-devel] [PATCH v2 19/31] target-xtensa: implement windowed registers, Max Filippov, 2011/07/24