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[Qemu-devel] [PATCH 13/15] onenand: Handle various ID fields separately
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 13/15] onenand: Handle various ID fields separately |
Date: |
Fri, 29 Jul 2011 16:35:26 +0100 |
From: Juha Riihimäki <address@hidden>
Handle the manufacturer, device and version IDs separately rather than
smooshing them all together into a single uint32_t. Note that the ID
registers are actually 16 bit, even though typically the top bits are 0
and the Read Identification Data command only returns the bottom 8 bits.
Signed-off-by: Juha Riihimäki <address@hidden>
[Riku Voipio: Fixes and restructuring patchset]
Signed-off-by: Riku Voipio <address@hidden>
[Peter Maydell: More fixes and cleanups for upstream submission]
Signed-off-by: Peter Maydell <address@hidden>
---
hw/flash.h | 3 ++-
hw/nseries.c | 5 +++--
hw/onenand.c | 29 ++++++++++++++++++-----------
3 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/hw/flash.h b/hw/flash.h
index 1aae43d..1064fd0 100644
--- a/hw/flash.h
+++ b/hw/flash.h
@@ -38,7 +38,8 @@ uint32_t nand_getbuswidth(DeviceState *dev);
/* onenand.c */
void onenand_base_update(void *opaque, target_phys_addr_t new);
void onenand_base_unmap(void *opaque);
-void *onenand_init(BlockDriverState *bdrv, uint32_t id,
+void *onenand_init(BlockDriverState *bdrv,
+ uint16_t man_id, uint16_t dev_id, uint16_t ver_id,
int regshift, qemu_irq irq);
void *onenand_raw_otp(void *opaque);
diff --git a/hw/nseries.c b/hw/nseries.c
index 96cc490..7cdba25 100644
--- a/hw/nseries.c
+++ b/hw/nseries.c
@@ -167,8 +167,9 @@ static void n8x0_nand_setup(struct n800_s *s)
DriveInfo *dinfo;
dinfo = drive_get(IF_MTD, 0, 0);
- /* Either ec40xx or ec48xx are OK for the ID */
- s->nand = onenand_init(dinfo ? dinfo->bdrv : 0, 0xec4800, 1,
+ /* Either 0x40 or 0x48 are OK for the device ID */
+ s->nand = onenand_init(dinfo ? dinfo->bdrv : 0,
+ NAND_MFR_SAMSUNG, 0x48, 0, 1,
qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
onenand_base_unmap, s->nand);
diff --git a/hw/onenand.c b/hw/onenand.c
index 3a19d7f..9f02736 100644
--- a/hw/onenand.c
+++ b/hw/onenand.c
@@ -31,7 +31,11 @@
#define BLOCK_SHIFT (PAGE_SHIFT + 6)
typedef struct {
- uint32_t id;
+ struct {
+ uint16_t man;
+ uint16_t dev;
+ uint16_t ver;
+ } id;
int shift;
target_phys_addr_t base;
qemu_irq intr;
@@ -453,12 +457,12 @@ static uint32_t onenand_read(void *opaque,
target_phys_addr_t addr)
return lduw_le_p(s->boot[0] + addr);
case 0xf000: /* Manufacturer ID */
- return (s->id >> 16) & 0xff;
+ return s->id.man;
case 0xf001: /* Device ID */
- return (s->id >> 8) & 0xff;
- /* TODO: get the following values from a real chip! */
+ return s->id.dev;
case 0xf002: /* Version ID */
- return (s->id >> 0) & 0xff;
+ return s->id.ver;
+ /* TODO: get the following values from a real chip! */
case 0xf003: /* Data Buffer size */
return 1 << PAGE_SHIFT;
case 0xf004: /* Boot Buffer size */
@@ -541,8 +545,8 @@ static void onenand_write(void *opaque, target_phys_addr_t
addr,
case 0x0090: /* Read Identification Data */
memset(s->boot[0], 0, 3 << s->shift);
- s->boot[0][0 << s->shift] = (s->id >> 16) & 0xff;
- s->boot[0][1 << s->shift] = (s->id >> 8) & 0xff;
+ s->boot[0][0 << s->shift] = s->id.man & 0xff;
+ s->boot[0][1 << s->shift] = s->id.dev & 0xff;
s->boot[0][2 << s->shift] = s->wpstatus & 0xff;
break;
@@ -615,21 +619,24 @@ static CPUWriteMemoryFunc * const onenand_writefn[] = {
onenand_write,
};
-void *onenand_init(BlockDriverState *bdrv, uint32_t id,
+void *onenand_init(BlockDriverState *bdrv,
+ uint16_t man_id, uint16_t dev_id, uint16_t ver_id,
int regshift, qemu_irq irq)
{
OneNANDState *s = (OneNANDState *) qemu_mallocz(sizeof(*s));
- uint32_t size = 1 << (24 + ((id >> 12) & 7));
+ uint32_t size = 1 << (24 + ((dev_id >> 4) & 7));
void *ram;
s->shift = regshift;
s->intr = irq;
s->rdy = NULL;
- s->id = id;
+ s->id.man = man_id;
+ s->id.dev = dev_id;
+ s->id.ver = ver_id;
s->blocks = size >> BLOCK_SHIFT;
s->secs = size >> 9;
s->blockwp = qemu_malloc(s->blocks);
- s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0;
+ s->density_mask = (dev_id & 0x08) ? (1 << (6 + ((dev_id >> 4) & 7))) : 0;
s->iomemtype = cpu_register_io_memory(onenand_readfn,
onenand_writefn, s, DEVICE_NATIVE_ENDIAN);
s->bdrv = bdrv;
--
1.7.1
- [Qemu-devel] [PATCH 14/15] onenand: Ignore zero writes to boot command space, (continued)
- [Qemu-devel] [PATCH 14/15] onenand: Ignore zero writes to boot command space, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 01/15] hw/omap_l4.c: Add helper function omap_l4_region_base, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 08/15] hw/nand: Support devices wider than 8 bits, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 02/15] hw/omap_gpio.c: Don't complain about some writes to r/o registers, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 11/15] hw/nand: qdevify, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 15/15] hw/onenand: program actions can only clear bits, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 09/15] hw/nand: Support multiple reads following READ STATUS, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 13/15] onenand: Handle various ID fields separately,
Peter Maydell <=
- [Qemu-devel] [PATCH 04/15] hw/omap_gpio.c: Convert to qdev, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 07/15] hw/nand: Support large NAND devices, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 05/15] lm832x: Take DeviceState pointer in lm832x_key_event(), Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 12/15] onenand: Pass BlockDriverState to init function, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 03/15] hw/omap_clk: Add the clock for the OMAP2430-specific fifth GPIO module, Peter Maydell, 2011/07/29