qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] modelling omap_gpmc with the hierarchical memory API


From: Peter Maydell
Subject: Re: [Qemu-devel] modelling omap_gpmc with the hierarchical memory API
Date: Wed, 3 Aug 2011 10:10:32 +0100

On 3 August 2011 03:25, Anthony Liguori <address@hidden> wrote:
> On 08/02/2011 04:28 PM, Peter Maydell wrote:
>> Typically in the latter case the device we're talking to will
>> also provide some gpio or irq signals, which will be routed in
>> a totally different direction having nothing to do with the GPMC.
>> So it's important that we should be able to take an existing
>> device model and route its registers through the GPMC and its
>> GPIO elsewhere.
>
> So I think the modelling disconnect here is that you're trying to model the
> wire connections to hook up arbitrary devices to a OMAP SOC.

Yes. This is how hardware works... If our device model lets
us wire up connections at a fairly low level, then we can always
implement more strongly typed and more bus like connections in
terms of that. If we only provide strongly typed connections then
it's not possible to model lower level wiring in terms of those.

This is IMHO exactly why so many things end up as sysbus devices --
they're the closest thing we have to "just get out of my way and
let me connect this device model up the way it needs to be connected".

> Unless you're modelling each pin (which I don't think you're doing), I think
> it makes more sense to treat this as a bus and model accordingly.

I think the "bus" like thing is the "I am providing an addressible
section of memory" part. I think we need that as a low level
fundamental kind of connection in the same way as a single GPIO
signal is a low level fundamental connection. At the moment the
closest thing we have to that is to model it as a complete sysbus,
which seems like overkill (we don't want the GPIO bits of sysbus
for just the memory connection) but will work.

[*] I did convince myself that you do want a sysbus bus on each
chip select, because in theory in the hardware you could put an
external address decoder on the gpmc_a[] bus and hang multiple
devices off one chipselect. So that's a sysbus, really.

-- PMM



reply via email to

[Prev in Thread] Current Thread [Next in Thread]