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[Qemu-devel] [PATCH] Remove unused is_softmmu parameter from cpu_handle_
|
From: |
Blue Swirl |
|
Subject: |
[Qemu-devel] [PATCH] Remove unused is_softmmu parameter from cpu_handle_mmu_fault |
|
Date: |
Wed, 3 Aug 2011 18:00:50 +0000 |
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)
is not used in cpu_*_handle_mmu_fault() functions, remove them
and adjust callers.
Signed-off-by: Blue Swirl <address@hidden>
---
target-alpha/cpu.h | 2 +-
target-alpha/helper.c | 4 ++--
target-alpha/op_helper.c | 2 +-
target-arm/cpu.h | 2 +-
target-arm/helper.c | 4 ++--
target-arm/op_helper.c | 2 +-
target-cris/cpu.h | 2 +-
target-cris/helper.c | 11 +++++------
target-cris/op_helper.c | 2 +-
target-i386/cpu.h | 2 +-
target-i386/helper.c | 4 ++--
target-i386/op_helper.c | 2 +-
target-lm32/cpu.h | 2 +-
target-lm32/helper.c | 2 +-
target-lm32/op_helper.c | 2 +-
target-m68k/cpu.h | 2 +-
target-m68k/helper.c | 4 ++--
target-m68k/op_helper.c | 2 +-
target-microblaze/cpu.h | 2 +-
target-microblaze/helper.c | 4 ++--
target-microblaze/op_helper.c | 2 +-
target-mips/cpu.h | 2 +-
target-mips/helper.c | 6 +++---
target-mips/op_helper.c | 2 +-
target-ppc/cpu.h | 2 +-
target-ppc/helper.c | 4 ++--
target-ppc/op_helper.c | 2 +-
target-s390x/cpu.h | 2 +-
target-s390x/helper.c | 12 ++++++------
target-s390x/op_helper.c | 2 +-
target-sh4/cpu.h | 2 +-
target-sh4/helper.c | 4 ++--
target-sh4/op_helper.c | 2 +-
target-sparc/cpu.h | 2 +-
target-sparc/helper.c | 6 +++---
target-sparc/op_helper.c | 2 +-
target-unicore32/cpu.h | 2 +-
target-unicore32/helper.c | 2 +-
user-exec.c | 2 +-
39 files changed, 59 insertions(+), 60 deletions(-)
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 919be12..c2e7bb3 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -426,7 +426,7 @@ int cpu_alpha_exec(CPUAlphaState *s);
int cpu_alpha_signal_handler(int host_signum, void *pinfo,
void *puc);
int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw,
- int mmu_idx, int is_softmmu);
+ int mmu_idx);
#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
void do_interrupt (CPUState *env);
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index 7049c80..06d2565 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -160,7 +160,7 @@ void cpu_alpha_store_fpcr (CPUState *env, uint64_t val)
#if defined(CONFIG_USER_ONLY)
int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
env->exception_index = EXCP_MMFAULT;
env->trap_arg0 = address;
@@ -316,7 +316,7 @@ target_phys_addr_t
cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
}
int cpu_alpha_handle_mmu_fault(CPUState *env, target_ulong addr, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
target_ulong phys;
int prot, fail;
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index c2bb679..38be234 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -1344,7 +1344,7 @@ void tlb_fill (target_ulong addr, int is_write,
int mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
- ret = cpu_alpha_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
+ ret = cpu_alpha_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
do_restore_state(retaddr);
/* Exception index and error code are already set */
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index adef427..f17fd6b 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -244,7 +244,7 @@ uint32_t do_arm_semihosting(CPUARMState *env);
int cpu_arm_signal_handler(int host_signum, void *pinfo,
void *puc);
int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmuu);
+ int mmu_idx);
#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ae4f334..1ee199d 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -542,7 +542,7 @@ void do_interrupt (CPUState *env)
}
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
if (rw == 2) {
env->exception_index = EXCP_PREFETCH_ABORT;
@@ -1254,7 +1254,7 @@ static inline int get_phys_addr(CPUState *env,
uint32_t address,
}
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
- int access_type, int mmu_idx, int is_softmmu)
+ int access_type, int mmu_idx)
{
uint32_t phys_addr;
target_ulong page_size;
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 57e4977..37b77e1 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -86,7 +86,7 @@ void tlb_fill (target_ulong addr, int is_write, int
mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
- ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
+ ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index ecb0df1..8ae0ce3 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -226,7 +226,7 @@ static inline int cpu_mmu_index (CPUState *env)
}
int cpu_cris_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu);
+ int mmu_idx);
#define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)
diff --git a/target-cris/helper.c b/target-cris/helper.c
index 962d214..75f0035 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -47,7 +47,7 @@ void do_interrupt (CPUState *env)
}
int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
env->exception_index = 0xaa;
env->pregs[PR_EDA] = address;
@@ -68,7 +68,7 @@ static void cris_shift_ccs(CPUState *env)
}
int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
struct cris_mmu_result res;
int prot, miss;
@@ -104,10 +104,9 @@ int cpu_cris_handle_mmu_fault (CPUState *env,
target_ulong address, int rw,
r = 0;
}
if (r > 0)
- D_LOG("%s returns %d irqreq=%x addr=%x"
- " phy=%x ismmu=%d vec=%x pc=%x\n",
- __func__, r, env->interrupt_request,
- address, res.phy, is_softmmu, res.bf_vec, env->pc);
+ D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
+ __func__, r, env->interrupt_request, address, res.phy,
+ res.bf_vec, env->pc);
return r;
}
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index 246f08f..0cfe1b1 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -70,7 +70,7 @@ void tlb_fill (target_ulong addr, int is_write, int
mmu_idx, void *retaddr)
D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__,
env->pc, env->debug1, retaddr);
- ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
+ ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index dd6c5fa..ae0e4b1 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -889,7 +889,7 @@ void host_cpuid(uint32_t function, uint32_t count,
/* helper.c */
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
- int is_write, int mmu_idx, int is_softmmu);
+ int is_write, int mmu_idx);
#define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
void cpu_x86_set_a20(CPUX86State *env, int a20_state);
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 182009a..3384520 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -546,7 +546,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
#if defined(CONFIG_USER_ONLY)
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
- int is_write, int mmu_idx, int is_softmmu)
+ int is_write, int mmu_idx)
{
/* user mode only emulation */
is_write &= 1;
@@ -573,7 +573,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env,
target_ulong addr,
1 = generate PF fault
*/
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
- int is_write1, int mmu_idx, int is_softmmu)
+ int is_write1, int mmu_idx)
{
uint64_t ptep, pte;
target_ulong pde_addr, pte_addr;
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index 1380934..1bbc3b5 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -5009,7 +5009,7 @@ void tlb_fill(target_ulong addr, int is_write,
int mmu_idx, void *retaddr)
saved_env = env;
env = cpu_single_env;
- ret = cpu_x86_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
+ ret = cpu_x86_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (ret) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 876b5be..037ef52 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -205,7 +205,7 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value);
#define CPU_SAVE_VERSION 1
int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu);
+ int mmu_idx);
#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index e79428d..48c402e 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -26,7 +26,7 @@
#include "host-utils.h"
int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
int prot;
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index 32b9a03..557da6c 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -87,7 +87,7 @@ void tlb_fill(target_ulong addr, int is_write, int
mmu_idx, void *retaddr)
saved_env = env;
env = cpu_single_env;
- ret = cpu_lm32_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
+ ret = cpu_lm32_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index e0f9b32..0667f82 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -231,7 +231,7 @@ static inline int cpu_mmu_index (CPUState *env)
}
int cpu_m68k_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu);
+ int mmu_idx);
#define cpu_handle_mmu_fault cpu_m68k_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index a936fe7..7ca75fb 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -344,7 +344,7 @@ void m68k_switch_sp(CPUM68KState *env)
#if defined(CONFIG_USER_ONLY)
int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
env->exception_index = EXCP_ACCESS;
env->mmu.ar = address;
@@ -362,7 +362,7 @@ target_phys_addr_t
cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
}
int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
int prot;
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 764b6a0..c66fa0c 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -66,7 +66,7 @@ void tlb_fill (target_ulong addr, int is_write, int
mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
- ret = cpu_m68k_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
+ ret = cpu_m68k_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 76f4fc4..a81da62 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -309,7 +309,7 @@ static inline int cpu_mmu_index (CPUState *env)
}
int cpu_mb_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu);
+ int mmu_idx);
#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
#if defined(CONFIG_USER_ONLY)
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 299259c..2cf2802 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -37,7 +37,7 @@ void do_interrupt (CPUState *env)
}
int cpu_mb_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
env->exception_index = 0xaa;
cpu_dump_state(env, stderr, fprintf, 0);
@@ -47,7 +47,7 @@ int cpu_mb_handle_mmu_fault(CPUState * env,
target_ulong address, int rw,
#else /* !CONFIG_USER_ONLY */
int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
unsigned int hit;
unsigned int mmu_available;
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 189c59c..8a7deac 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -54,7 +54,7 @@ void tlb_fill (target_ulong addr, int is_write, int
mmu_idx, void *retaddr)
saved_env = env;
env = cpu_single_env;
- ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
+ ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 030f499..c5f70fa 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -636,7 +636,7 @@ void cpu_mips_soft_irq(CPUState *env, int irq, int level);
/* helper.c */
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu);
+ int mmu_idx);
#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
void do_interrupt (CPUState *env);
#if !defined(CONFIG_USER_ONLY)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index ecf6182..024caa2 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -266,7 +266,7 @@ target_phys_addr_t
cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
#endif
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
#if !defined(CONFIG_USER_ONLY)
target_phys_addr_t physical;
@@ -278,8 +278,8 @@ int cpu_mips_handle_mmu_fault (CPUState *env,
target_ulong address, int rw,
#if 0
log_cpu_state(env, 0);
#endif
- qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d
mmu_idx %d smmu %d\n",
- __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
+ qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d\n",
+ __func__, env->active_tc.PC, address, rw, mmu_idx);
rw &= 1;
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 185ae40..056011f 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2017,7 +2017,7 @@ void tlb_fill (target_ulong addr, int is_write,
int mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
- ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
+ ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (ret) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index d903366..024eb6f 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1022,7 +1022,7 @@ void cpu_ppc_close (CPUPPCState *s);
int cpu_ppc_signal_handler (int host_signum, void *pinfo,
void *puc);
int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu);
+ int mmu_idx);
#define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
#if !defined(CONFIG_USER_ONLY)
int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 176128a..adcd23e 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -78,7 +78,7 @@ void (*cpu_ppc_hypercall)(CPUState *);
#if defined(CONFIG_USER_ONLY)
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
int exception, error_code;
@@ -1658,7 +1658,7 @@ static void
booke206_update_mas_tlb_miss(CPUState *env, target_ulong address,
/* Perform address translation */
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
mmu_ctx_t ctx;
int access_type;
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 6e100d9..c5e0601 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -3725,7 +3725,7 @@ void tlb_fill (target_ulong addr, int is_write,
int mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
- ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
+ ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
if (likely(retaddr)) {
/* now we have a real cpu fault */
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index d48a9b7..f8f0c82 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -280,7 +280,7 @@ void do_interrupt (CPUState *env);
int cpu_s390x_signal_handler(int host_signum, void *pinfo,
void *puc);
int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong
address, int rw,
- int mmu_idx, int is_softmuu);
+ int mmu_idx);
#define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 1ce7079..ce8d97d 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -110,10 +110,10 @@ void do_interrupt (CPUState *env)
}
int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
- /* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d is_softmmu %d\n",
- __FUNCTION__, address, rw, mmu_idx, is_softmmu); */
+ /* fprintf(stderr,"%s: address 0x%lx rw %d mmu_idx %d\n",
+ __FUNCTION__, address, rw, mmu_idx); */
env->exception_index = EXCP_ADDR;
env->__excp_addr = address; /* FIXME: find out how this works on
a real machine */
return 1;
@@ -394,14 +394,14 @@ out:
}
int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong _vaddr, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
uint64_t asc = env->psw.mask & PSW_MASK_ASC;
target_ulong vaddr, raddr;
int prot;
- DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d is_softmmu %d\n",
- __FUNCTION__, _vaddr, rw, mmu_idx, is_softmmu);
+ DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
+ __FUNCTION__, _vaddr, rw, mmu_idx);
_vaddr &= TARGET_PAGE_MASK;
vaddr = _vaddr;
diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
index 25a1e81..b3ac630 100644
--- a/target-s390x/op_helper.c
+++ b/target-s390x/op_helper.c
@@ -63,7 +63,7 @@ void tlb_fill (target_ulong addr, int is_write, int
mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
- ret = cpu_s390x_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
+ ret = cpu_s390x_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
if (likely(retaddr)) {
/* now we have a real cpu fault */
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 00e32f2..7d7fdde 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -194,7 +194,7 @@ int cpu_sh4_exec(CPUSH4State * s);
int cpu_sh4_signal_handler(int host_signum, void *pinfo,
void *puc);
int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu);
+ int mmu_idx);
#define cpu_handle_mmu_fault cpu_sh4_handle_mmu_fault
void do_interrupt(CPUSH4State * env);
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 20e9b13..5a1e15e 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -34,7 +34,7 @@ void do_interrupt (CPUState *env)
}
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
env->tea = address;
env->exception_index = -1;
@@ -440,7 +440,7 @@ static int get_physical_address(CPUState * env,
target_ulong * physical,
}
int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
target_ulong physical;
int prot, ret, access_type;
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 568bf0d..163858f 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -64,7 +64,7 @@ void tlb_fill(target_ulong addr, int is_write, int
mmu_idx, void *retaddr)
generated code */
saved_env = env;
env = cpu_single_env;
- ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
+ ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (ret) {
/* now we have a real cpu fault */
cpu_restore_state_from_retaddr(retaddr);
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index a51863c..8654f26 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -490,7 +490,7 @@ CPUSPARCState *cpu_sparc_init(const char *cpu_model);
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong
address, int rw,
- int mmu_idx, int is_softmmu);
+ int mmu_idx);
#define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index efab885..47110a5 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -42,7 +42,7 @@ static int cpu_sparc_find_by_name(sparc_def_t
*cpu_def, const char *cpu_model);
#if defined(CONFIG_USER_ONLY)
int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
if (rw & 2)
env1->exception_index = TT_TFAULT;
@@ -212,7 +212,7 @@ static int get_physical_address(CPUState *env,
target_phys_addr_t *physical,
/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
target_phys_addr_t paddr;
target_ulong vaddr;
@@ -638,7 +638,7 @@ static int get_physical_address(CPUState *env,
target_phys_addr_t *physical,
/* Perform address translation */
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
target_ulong virt_addr, vaddr;
target_phys_addr_t paddr;
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 5aeca2b..d1a8dd9 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -4237,7 +4237,7 @@ void tlb_fill(target_ulong addr, int is_write,
int mmu_idx, void *retaddr)
saved_env = env;
env = cpu_single_env;
- ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
+ ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx);
if (ret) {
cpu_restore_state2(retaddr);
cpu_loop_exit(env);
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 9817607..b4e72cf 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -130,7 +130,7 @@ CPUState *uc32_cpu_init(const char *cpu_model);
int uc32_cpu_exec(CPUState *s);
int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmuu);
+ int mmu_idx);
#define CPU_SAVE_VERSION 2
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 02707d5..8edfcb7 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -104,7 +104,7 @@ void do_interrupt(CPUState *env)
}
int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
- int mmu_idx, int is_softmmu)
+ int mmu_idx)
{
env->exception_index = UC32_EXCP_TRAP;
env->cp0.c4_faultaddr = address;
diff --git a/user-exec.c b/user-exec.c
index 14c0f25..abf6885 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -102,7 +102,7 @@ static inline int handle_cpu_signal(unsigned long
pc, unsigned long address,
}
/* see if it is an MMU fault */
- ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
+ ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX);
if (ret < 0) {
return 0; /* not an MMU fault */
}
--
1.6.2.4
- [Qemu-devel] [PATCH] Remove unused is_softmmu parameter from cpu_handle_mmu_fault,
Blue Swirl <=