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Re: [Qemu-devel] [PATCH 2/4] Octeon cpu definitions in target-mips and O


From: Khansa Butt
Subject: Re: [Qemu-devel] [PATCH 2/4] Octeon cpu definitions in target-mips and Octeon specific changes in set_thread_area syscall
Date: Wed, 17 Aug 2011 12:00:04 +0500



On Mon, Aug 15, 2011 at 8:43 PM, Richard Henderson <address@hidden> wrote:
On 08/15/2011 04:25 AM, address@hidden wrote:
>        ((CPUMIPSState *) cpu_env)->tls_value = arg1;
> +      if (((CPUMIPSState *) cpu_env)->insn_flags & CPU_OCTEON) {
> +          /* tls entry is moved to k0 so that this can be used later
> +             currently this thing is tested only for Octeon */
> +          ((CPUMIPSState *) cpu_env)->active_tc.gpr[26] = arg1;
> +      }

You wanted INSN_OCTEON, not CPU_OCTEON, which includes CPU_MIPS64R2.

That said, this is *not* in the current linux kernel.  And I question
the wisdom of changing the user-space ABI for TLS for a single CPU.

I think you'd better leave this out until it's actually accepted upstream.

with out above fix Octeon user mode binary can not be correctly run on QEMU.
This was the behavior on actual hardware which we noticed when we were debugging the 
user mode binary on Octeon board. 
(there are instructions in user mode ELF of Octeon which read k0 and k1 values) 


r~


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