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[Qemu-devel] [PATCH 054/111] m68k: Added ULL to 64 bit integer in helper
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 054/111] m68k: Added ULL to 64 bit integer in helper.c |
Date: |
Wed, 17 Aug 2011 15:46:59 -0500 |
From: Peter Bjørn Jørgensen <address@hidden>
Signed-off-by: Peter Bjørn Jørgensen <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/helper.c | 48 ++++++++++++++++++++++++------------------------
1 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 21dfcc7..875ff45 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -977,30 +977,30 @@ HELPER_ROXL(uint32_t, 32)
/* FPU helpers. */
static const floatx80 fpu_rom[128] = {
- [0x00] = { .high = 0x4000, .low = 0xc90fdaa22168c235 }, /* Pi */
-
- [0x0b] = { .high = 0x3ffd, .low = 0x9a209a84fbcff798 }, /* Log10(2) */
- [0x0c] = { .high = 0x4000, .low = 0xadf85458a2bb4a9a }, /* e */
- [0x0d] = { .high = 0x3fff, .low = 0xb8aa3b295c17f0bc }, /* Log2(e) */
- [0x0e] = { .high = 0x3ffd, .low = 0xde5bd8a937287195 }, /* Log10(e) */
- [0x0f] = { .high = 0x0000, .low = 0x0000000000000000 }, /* Zero */
-
- [0x30] = { .high = 0x3ffe, .low = 0xb17217f7d1cf79ac }, /* ln(2) */
- [0x31] = { .high = 0x4000, .low = 0x935d8dddaaa8ac17 }, /* ln(10) */
- [0x32] = { .high = 0x3fff, .low = 0x8000000000000000 }, /* 10^0 */
- [0x33] = { .high = 0x4002, .low = 0xa000000000000000 }, /* 10^1 */
- [0x34] = { .high = 0x4005, .low = 0xc800000000000000 }, /* 10^2 */
- [0x35] = { .high = 0x400c, .low = 0x9c40000000000000 }, /* 10^4 */
- [0x36] = { .high = 0x4019, .low = 0xbebc200000000000 }, /* 10^8 */
- [0x37] = { .high = 0x4034, .low = 0x8e1bc9bf04000000 }, /* 10^16 */
- [0x38] = { .high = 0x4069, .low = 0x9dc5ada82b70b59e }, /* 10^32 */
- [0x39] = { .high = 0x40d3, .low = 0xc2781f49ffcfa6d5 }, /* 10^64 */
- [0x3a] = { .high = 0x41a8, .low = 0x93ba47c980e98ce0 }, /* 10^128 */
- [0x3b] = { .high = 0x4351, .low = 0xaa7eebfb9df9de8e }, /* 10^256 */
- [0x3c] = { .high = 0x46a3, .low = 0xe319a0aea60e91c7 }, /* 10^512 */
- [0x3d] = { .high = 0x4d48, .low = 0xc976758681750c17 }, /* 10^1024 */
- [0x3e] = { .high = 0x5a92, .low = 0x9e8b3b5dc53d5de5 }, /* 10^2048 */
- [0x3f] = { .high = 0x7525, .low = 0xc46052028a20979b }, /* 10^4096 */
+ [0x00] = { .high = 0x4000, .low = 0xc90fdaa22168c235ULL }, /* Pi */
+
+ [0x0b] = { .high = 0x3ffd, .low = 0x9a209a84fbcff798ULL }, /* Log10(2) */
+ [0x0c] = { .high = 0x4000, .low = 0xadf85458a2bb4a9aULL }, /* e */
+ [0x0d] = { .high = 0x3fff, .low = 0xb8aa3b295c17f0bcULL }, /* Log2(e) */
+ [0x0e] = { .high = 0x3ffd, .low = 0xde5bd8a937287195ULL }, /* Log10(e) */
+ [0x0f] = { .high = 0x0000, .low = 0x0000000000000000ULL }, /* Zero */
+
+ [0x30] = { .high = 0x3ffe, .low = 0xb17217f7d1cf79acULL }, /* ln(2) */
+ [0x31] = { .high = 0x4000, .low = 0x935d8dddaaa8ac17ULL }, /* ln(10) */
+ [0x32] = { .high = 0x3fff, .low = 0x8000000000000000ULL }, /* 10^0 */
+ [0x33] = { .high = 0x4002, .low = 0xa000000000000000ULL }, /* 10^1 */
+ [0x34] = { .high = 0x4005, .low = 0xc800000000000000ULL }, /* 10^2 */
+ [0x35] = { .high = 0x400c, .low = 0x9c40000000000000ULL }, /* 10^4 */
+ [0x36] = { .high = 0x4019, .low = 0xbebc200000000000ULL }, /* 10^8 */
+ [0x37] = { .high = 0x4034, .low = 0x8e1bc9bf04000000ULL }, /* 10^16 */
+ [0x38] = { .high = 0x4069, .low = 0x9dc5ada82b70b59eULL }, /* 10^32 */
+ [0x39] = { .high = 0x40d3, .low = 0xc2781f49ffcfa6d5ULL }, /* 10^64 */
+ [0x3a] = { .high = 0x41a8, .low = 0x93ba47c980e98ce0ULL }, /* 10^128 */
+ [0x3b] = { .high = 0x4351, .low = 0xaa7eebfb9df9de8eULL }, /* 10^256 */
+ [0x3c] = { .high = 0x46a3, .low = 0xe319a0aea60e91c7ULL }, /* 10^512 */
+ [0x3d] = { .high = 0x4d48, .low = 0xc976758681750c17ULL }, /* 10^1024 */
+ [0x3e] = { .high = 0x5a92, .low = 0x9e8b3b5dc53d5de5ULL }, /* 10^2048 */
+ [0x3f] = { .high = 0x7525, .low = 0xc46052028a20979bULL }, /* 10^4096 */
};
float64 HELPER(const_f64)(CPUState *env, uint32_t offset)
--
1.7.2.3
- [Qemu-devel] [PATCH 062/111] m68k: FPU rework (draft), (continued)
- [Qemu-devel] [PATCH 062/111] m68k: FPU rework (draft), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 076/111] m68k: register source operand is always in extended size, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 074/111] m68k: add ftwotox instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 060/111] m68k: remove dead code, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 045/111] m68k: improve subx, negx instructions Add (byte, word) opsize Add memory access (subx), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 070/111] m68k: initialize FRegs, define pickNaN(), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 042/111] m68k: set X flag according size of operand Set X flag correctly for addsub, arith_im, addsubq., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 085/111] m68k: add fatan instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 073/111] m68k: add cmpm instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 055/111] m68k: Correct bfclr in register case., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 054/111] m68k: Added ULL to 64 bit integer in helper.c,
Bryce Lanham <=
- [Qemu-devel] [PATCH 040/111] m68k: add sbcd instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 082/111] m68k: add fmod instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 068/111] m68k: correct addsubq, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 053/111] m68k: for bitfield opcodes, correct operands corruption, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 057/111] m68k: correctly compute divsl, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 027/111] m68k: add DBcc instruction., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 083/111] m68k: flush flags before negx instruction., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 084/111] m68k: correct fmovemx FP registers order., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 047/111] m68k: use read_imm1() when it is possible, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 079/111] m68k: add fsin instruction, Bryce Lanham, 2011/08/17