[Qemu-devel] [PATCH 040/111] m68k: add sbcd instruction

[Bryce Lanham]

From: Laurent Vivier <address@hidden>

Signed-off-by: Laurent Vivier <address@hidden>
---
 target-m68k/helper.c    |   45 +++++++++++++++++++++++++++++++++++++++++++++
 target-m68k/helpers.h   |    1 +
 target-m68k/translate.c |   32 ++++++++++++++++++++++++++++++++
 3 files changed, 78 insertions(+), 0 deletions(-)

diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 7d99326..0fa59c8 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -1324,3 +1324,48 @@ uint32_t HELPER(abcd_cc)(CPUState *env, uint32_t src, 
uint32_t dest)
 
     return dest;
 }
+
+uint32_t HELPER(sbcd_cc)(CPUState *env, uint32_t src, uint32_t dest)
+{
+    uint16_t hi, lo;
+    uint16_t res;
+    uint32_t flags;
+    int bcd = 0, carry = 0;
+
+    flags = env->cc_dest;
+    flags &= ~(CCF_C|CCF_X);
+
+    if (env->cc_x)
+        carry = 1;
+
+    lo = (dest & 0x0f) - (src & 0x0f) - carry;
+    hi = (dest & 0xf0) - (src & 0xf0);
+
+    res = hi + lo;
+    if (lo & 0xf0) {
+        res -= 0x06;
+        bcd = 0x06;
+    }
+
+    if ((((dest & 0xff) - (src & 0xff) - carry) & 0x100) > 0xff) {
+        res -= 0x60;
+    }
+
+    /* C and X flags: set if decimal carry, cleared otherwise */
+
+    if ((((dest & 0xff) - (src & 0xff) - (bcd + carry)) & 0x300) > 0xff) {
+        flags |= CCF_C|CCF_X;
+    }
+
+    /* Z flag: cleared if nonzero */
+
+    if (res & 0xff)
+        flags &= ~CCF_Z;
+
+    dest = (dest & 0xffffff00) | (res & 0xff);
+
+    env->cc_x = (flags & CCF_X) != 0;
+    env->cc_dest = flags;
+
+    return dest;
+}
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index f299752..76d3063 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -83,4 +83,5 @@ DEF_HELPER_3(bitfield_load, i64, i32, i32, i32);
 DEF_HELPER_4(bitfield_store, void, i32, i32, i32, i64);
 
 DEF_HELPER_3(abcd_cc, i32, env, i32, i32);
+DEF_HELPER_3(sbcd_cc, i32, env, i32, i32);
 #include "def-helper.h"
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 231d87a..7aef2f6 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1095,6 +1095,36 @@ DISAS_INSN(abcd_mem)
     gen_store(s, OS_BYTE, addr_dest, dest);
 }
 
+DISAS_INSN(sbcd_reg)
+{
+    TCGv src;
+    TCGv dest;
+
+    src = DREG(insn, 0);
+    dest = DREG(insn, 9);
+    gen_helper_sbcd_cc(dest, cpu_env, src, dest);
+}
+
+DISAS_INSN(sbcd_mem)
+{
+    TCGv src;
+    TCGv addr_src;
+    TCGv dest;
+    TCGv addr_dest;
+
+    addr_src = AREG(insn, 0);
+    tcg_gen_subi_i32(addr_src, addr_src, OS_BYTE);
+    src = gen_load(s, OS_BYTE, addr_src, 0);
+
+    addr_dest = AREG(insn, 9);
+    tcg_gen_subi_i32(addr_dest, addr_dest, OS_BYTE);
+    dest = gen_load(s, OS_BYTE, addr_dest, 0);
+
+    gen_helper_sbcd_cc(dest, cpu_env, src, dest);
+
+    gen_store(s, OS_BYTE, addr_dest, dest);
+}
+
 DISAS_INSN(addsub)
 {
     TCGv reg;
@@ -3909,6 +3939,8 @@ void register_m68k_insns (CPUM68KState *env)
     INSN(or,        8000, f000, M68000);
     INSN(divw,      80c0, f0c0, CF_ISA_A);
     INSN(divw,      80c0, f0c0, M68000);
+    INSN(sbcd_reg,  8100, f1f8, M68000);
+    INSN(sbcd_mem,  8108, f1f8, M68000);
     INSN(addsub,    9000, f000, CF_ISA_A);
     INSN(addsub,    9000, f000, M68000);
     INSN(undef,     90c0, f0c0, CF_ISA_A);
-- 
1.7.2.3