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[Qemu-devel] [PATCH 039/111] m68k: add abcd instruction
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 039/111] m68k: add abcd instruction |
Date: |
Wed, 17 Aug 2011 15:46:44 -0500 |
From: Laurent Vivier <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/helper.c | 38 ++++++++++++++++++++++++++++++++++++++
target-m68k/helpers.h | 2 ++
target-m68k/translate.c | 32 ++++++++++++++++++++++++++++++++
3 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index dfa7c10..7d99326 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -1286,3 +1286,41 @@ void HELPER(bitfield_store)(uint32_t addr, uint32_t
offset, uint32_t width,
cpu_physical_memory_rw(addr, data, size, 1);
#endif
}
+
+uint32_t HELPER(abcd_cc)(CPUState *env, uint32_t src, uint32_t dest)
+{
+ uint16_t hi, lo;
+ uint16_t res;
+ uint32_t flags;
+
+ flags = env->cc_dest;
+ flags &= ~(CCF_C|CCF_X);
+
+ lo = (src & 0x0f) + (dest & 0x0f);
+ if (env->cc_x)
+ lo ++;
+ hi = (src & 0xf0) + (dest & 0xf0);
+
+ res = hi + lo;
+ if (lo > 9)
+ res += 0x06;
+
+ /* C and X flags: set if decimal carry, cleared otherwise */
+
+ if ((res & 0x3F0) > 0x90) {
+ res += 0x60;
+ flags |= CCF_C|CCF_X;
+ }
+
+ /* Z flag: cleared if nonzero */
+
+ if (res & 0xff)
+ flags &= ~CCF_Z;
+
+ dest = (dest & 0xffffff00) | (res & 0xff);
+
+ env->cc_x = (flags & CCF_X) != 0;
+ env->cc_dest = flags;
+
+ return dest;
+}
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index 4bfb149..f299752 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -81,4 +81,6 @@ DEF_HELPER_1(raise_exception, void, i32)
DEF_HELPER_3(bitfield_load, i64, i32, i32, i32);
DEF_HELPER_4(bitfield_store, void, i32, i32, i32, i64);
+
+DEF_HELPER_3(abcd_cc, i32, env, i32, i32);
#include "def-helper.h"
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index ab2073a..231d87a 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1065,6 +1065,36 @@ DISAS_INSN(divl)
s->cc_op = CC_OP_FLAGS;
}
+DISAS_INSN(abcd_reg)
+{
+ TCGv src;
+ TCGv dest;
+
+ src = DREG(insn, 0);
+ dest = DREG(insn, 9);
+ gen_helper_abcd_cc(dest, cpu_env, src, dest);
+}
+
+DISAS_INSN(abcd_mem)
+{
+ TCGv src;
+ TCGv addr_src;
+ TCGv dest;
+ TCGv addr_dest;
+
+ addr_src = AREG(insn, 0);
+ tcg_gen_subi_i32(addr_src, addr_src, OS_BYTE);
+ src = gen_load(s, OS_BYTE, addr_src, 0);
+
+ addr_dest = AREG(insn, 9);
+ tcg_gen_subi_i32(addr_dest, addr_dest, OS_BYTE);
+ dest = gen_load(s, OS_BYTE, addr_dest, 0);
+
+ gen_helper_abcd_cc(dest, cpu_env, src, dest);
+
+ gen_store(s, OS_BYTE, addr_dest, dest);
+}
+
DISAS_INSN(addsub)
{
TCGv reg;
@@ -3915,6 +3945,8 @@ void register_m68k_insns (CPUM68KState *env)
INSN(and, c000, f000, M68000);
INSN(mulw, c0c0, f0c0, CF_ISA_A);
INSN(mulw, c0c0, f0c0, M68000);
+ INSN(abcd_reg, c100, f1f8, M68000);
+ INSN(abcd_mem, c108, f1f8, M68000);
INSN(addsub, d000, f000, CF_ISA_A);
INSN(addsub, d000, f000, M68000);
INSN(undef, d0c0, f0c0, CF_ISA_A);
--
1.7.2.3
- [Qemu-devel] [PATCH 016/111] m68k: add 64bit divide., (continued)
- [Qemu-devel] [PATCH 016/111] m68k: add 64bit divide., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 014/111] m68k: add DBcc instruction., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 018/111] m68k: add word data size for suba/adda, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 017/111] m68k: add 32bit and 64bit multiply, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 019/111] m68k: add fpu, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 020/111] m68k: add "byte", "word" and memory shift, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 022/111] m68k: add bitfield_mem, bitfield_reg, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 029/111] m68k: allow fpu to manage double data type with fmove to <ea>, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 030/111] m68k: add FScc instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 031/111] m68k: add single data type to gen_ea, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 039/111] m68k: add abcd instruction,
Bryce Lanham <=
- [Qemu-devel] [PATCH 035/111] m68k: improve CC_OP_LOGIC, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 037/111] Correct invalid use of "const void *" with "const uint8_t *", Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 041/111] mm68k: add nbcd instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 050/111] m68k: lsl/lsr, clear C flag if shift count is 0, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 043/111] m68k: on 0 bit shift, don't update X flag, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 075/111] m68k: better fpu traces, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 062/111] m68k: FPU rework (draft), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 076/111] m68k: register source operand is always in extended size, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 074/111] m68k: add ftwotox instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 060/111] m68k: remove dead code, Bryce Lanham, 2011/08/17