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[Qemu-devel] [PATCH 053/111] m68k: for bitfield opcodes, correct operand
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 053/111] m68k: for bitfield opcodes, correct operands corruption |
Date: |
Wed, 17 Aug 2011 15:46:58 -0500 |
From: Laurent Vivier <address@hidden>
This patch doesn't modify values inside operand "shift" and "offset",
instead copy them in a TCG temp.
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/translate.c | 7 ++++---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 4f2a5ee..e0c6fa3 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2693,7 +2693,8 @@ static void bitfield_param(uint16_t ext, TCGv *offset,
TCGv *width, TCGv *mask)
/* offset */
if (ext & 0x0800) {
- *offset = DREG(ext, 6);
+ *offset = tcg_temp_new_i32();
+ tcg_gen_mov_i32(*offset, DREG(ext, 6));
} else {
*offset = tcg_temp_new_i32();
tcg_gen_movi_i32(*offset, (ext >> 6) & 31);
@@ -2702,8 +2703,8 @@ static void bitfield_param(uint16_t ext, TCGv *offset,
TCGv *width, TCGv *mask)
/* width */
if (ext & 0x0020) {
- *width = DREG(ext, 0);
- tcg_gen_subi_i32(*width, *width, 1);
+ *width = tcg_temp_new_i32();
+ tcg_gen_subi_i32(*width, DREG(ext, 0), 1);
tcg_gen_andi_i32(*width, *width, 31);
tcg_gen_addi_i32(*width, *width, 1);
} else {
--
1.7.2.3
- [Qemu-devel] [PATCH 045/111] m68k: improve subx, negx instructions Add (byte, word) opsize Add memory access (subx), (continued)
- [Qemu-devel] [PATCH 045/111] m68k: improve subx, negx instructions Add (byte, word) opsize Add memory access (subx), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 070/111] m68k: initialize FRegs, define pickNaN(), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 042/111] m68k: set X flag according size of operand Set X flag correctly for addsub, arith_im, addsubq., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 085/111] m68k: add fatan instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 073/111] m68k: add cmpm instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 055/111] m68k: Correct bfclr in register case., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 054/111] m68k: Added ULL to 64 bit integer in helper.c, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 040/111] m68k: add sbcd instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 082/111] m68k: add fmod instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 068/111] m68k: correct addsubq, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 053/111] m68k: for bitfield opcodes, correct operands corruption,
Bryce Lanham <=
- [Qemu-devel] [PATCH 057/111] m68k: correctly compute divsl, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 027/111] m68k: add DBcc instruction., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 083/111] m68k: flush flags before negx instruction., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 084/111] m68k: correct fmovemx FP registers order., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 047/111] m68k: use read_imm1() when it is possible, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 079/111] m68k: add fsin instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 087/111] m68k: fcmp correctly compares infinity., Bryce Lanham, 2011/08/17
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Anthony Liguori, 2011/08/17