[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 067/111] m68k: add fscale
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 067/111] m68k: add fscale |
Date: |
Wed, 17 Aug 2011 15:47:12 -0500 |
From: Laurent Vivier <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
---
.gitignore | 1 +
target-m68k/helper.c | 17 +++++++++++++++++
target-m68k/helpers.h | 1 +
target-m68k/translate.c | 4 ++++
tests/m68k/Makefile | 2 +-
tests/m68k/fscale.S | 9 +++++++++
6 files changed, 33 insertions(+), 1 deletions(-)
create mode 100644 tests/m68k/fscale.S
diff --git a/.gitignore b/.gitignore
index ef339f5..fed07c5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -79,3 +79,4 @@ tests/m68k/fmovem
tests/m68k/fmul
tests/m68k/fsub
tests/m68k/fgetexp
+tests/m68k/fscale
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 2be3355..77d88e7 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -1292,6 +1292,23 @@ void HELPER(getexp_FP0)(CPUState *env)
floatx80_to_FP0(env, res);
}
+void HELPER(scale_FP0_FP1)(CPUState *env)
+{
+ int32_t scale;
+ int32_t exp;
+
+ DBG_FPU("getexp_FP0(%Lg)\n", LDOUBLE(FP0_to_floatx80(env)));
+
+ DBG_FPU(" fp0h 0x%08x fp0l 0x%016" PRIx64 "\n", env->fp0h, env->fp0l);
+
+ scale = floatx80_to_int32(FP0_to_floatx80(env), &env->fp_status);
+
+ exp = (env->fp1h & 0x7fff) + scale;
+
+ env->fp0h = (env->fp1h & 0x8000) | (exp & 0x7fff);
+ env->fp0l = env->fp1l;
+}
+
void HELPER(add_FP0_FP1)(CPUState *env)
{
floatx80 res;
diff --git a/target-m68k/helpers.h b/target-m68k/helpers.h
index 0b4c0cb..f6578ee 100644
--- a/target-m68k/helpers.h
+++ b/target-m68k/helpers.h
@@ -68,6 +68,7 @@ DEF_HELPER_1(sqrt_FP0, void, env)
DEF_HELPER_1(abs_FP0, void, env)
DEF_HELPER_1(chs_FP0, void, env)
DEF_HELPER_1(getexp_FP0, void, env)
+DEF_HELPER_1(scale_FP0_FP1, void, env)
DEF_HELPER_1(add_FP0_FP1, void, env)
DEF_HELPER_1(sub_FP0_FP1, void, env)
DEF_HELPER_1(mul_FP0_FP1, void, env)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index d09e325..93f9973 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3666,6 +3666,10 @@ DISAS_INSN(fpu)
gen_op_load_fpr_FP1(REG(ext, 7));
gen_helper_div_FP0_FP1(cpu_env);
break;
+ case 0x26: /* fscale */
+ gen_op_load_fpr_FP1(REG(ext, 7));
+ gen_helper_scale_FP0_FP1(cpu_env);
+ break;
case 0x27: /* fsglmul */
gen_op_load_fpr_FP1(REG(ext, 7));
gen_helper_mul_FP0_FP1(cpu_env);
diff --git a/tests/m68k/Makefile b/tests/m68k/Makefile
index a7a59ac..28a998f 100644
--- a/tests/m68k/Makefile
+++ b/tests/m68k/Makefile
@@ -1,4 +1,4 @@
-TESTS=fmovecr fmove fmovem fsub fdiv fmul fabs fgetexp
+TESTS=fmovecr fmove fmovem fsub fdiv fmul fabs fgetexp fscale
all: $(TESTS)
diff --git a/tests/m68k/fscale.S b/tests/m68k/fscale.S
new file mode 100644
index 0000000..f6a5c62
--- /dev/null
+++ b/tests/m68k/fscale.S
@@ -0,0 +1,9 @@
+ .include "trap.i"
+
+ .text
+ .globl _start
+_start:
+ fmove.l #2, %fp0
+ fmovecr.x #0x00,%fp1
+ fscale.x %fp0, %fp1
+ exit 0
--
1.7.2.3
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, (continued)
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Laurent Vivier, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
[Qemu-devel] [PATCH 086/111] m68k: correct bfins instruction, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 025/111] m68k: add cas, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 067/111] m68k: add fscale,
Bryce Lanham <=
[Qemu-devel] [PATCH 033/111] m68k: Add fmovecr, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 058/111] m68k: correctly compute divul, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 069/111] m68k: add fetox and flogn, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 048/111] m68k: correct shift side effect for roxrl and roxll, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 065/111] m68k: correct compute gen_bitfield_cc(), Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 049/111] m68k: asl/asr, clear C flag if shift count is 0, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 044/111] m68k: improve addx instructions Add (byte, word) opsize Add memory access, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 046/111] m68k: improve asl/asr evaluate correclty the missing V flag, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 023/111] m68k: add variable offset/width to bitfield_reg/bitfield_mem, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 081/111] m68k: correct fpcr update, Bryce Lanham, 2011/08/17