[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 049/111] m68k: asl/asr, clear C flag if shift count
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 049/111] m68k: asl/asr, clear C flag if shift count is 0 |
Date: |
Wed, 17 Aug 2011 15:46:54 -0500 |
From: Laurent Vivier <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/helper.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index a3a6108..5800a4f 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -808,7 +808,7 @@ uint32_t HELPER(glue(glue(sal, bits),_cc))(CPUState *env,
uint32_t val, uint32_t
}\
if (shift == 0) { \
result = (type)val; \
- cf = env->cc_src & CCF_C; \
+ cf = 0; \
} else if (shift < bits) { \
result = (type)val << shift; \
cf = ((type)val >> (bits - shift)) & 1; \
@@ -837,7 +837,7 @@ uint32_t HELPER(glue(glue(sar, bits), _cc))(CPUState *env,
uint32_t val, uint32_
shift &= 63; \
if (shift == 0) { \
result = (type)val; \
- cf = (env->cc_src & CCF_C) != 0; \
+ cf = 0; \
} else if (shift < bits) { \
result = (type)val >> shift; \
cf = ((type)val >> (shift - 1)) & 1; \
--
1.7.2.3
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, (continued)
- [Qemu-devel] [PATCH 086/111] m68k: correct bfins instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 025/111] m68k: add cas, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 067/111] m68k: add fscale, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 033/111] m68k: Add fmovecr, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 058/111] m68k: correctly compute divul, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 069/111] m68k: add fetox and flogn, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 048/111] m68k: correct shift side effect for roxrl and roxll, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 065/111] m68k: correct compute gen_bitfield_cc(), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 049/111] m68k: asl/asr, clear C flag if shift count is 0,
Bryce Lanham <=
- [Qemu-devel] [PATCH 044/111] m68k: improve addx instructions Add (byte, word) opsize Add memory access, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 046/111] m68k: improve asl/asr evaluate correclty the missing V flag, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 023/111] m68k: add variable offset/width to bitfield_reg/bitfield_mem, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 081/111] m68k: correct fpcr update, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 063/111] m68k: some FPU debugging macros, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 066/111] m68k: add fgetexp, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 051/111] m68k: correct divs.w and divu.w, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 071/111] m68k: correct cmpa comparison datatype, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 061/111] m68k: remove useless file m68k-qreg.h, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 059/111] m68k: add m68030 definition, Bryce Lanham, 2011/08/17