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[Qemu-devel] [PATCH v3 18/32] target-xtensa: implement RST2 group (32 bi
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH v3 18/32] target-xtensa: implement RST2 group (32 bit mul/div/rem) |
Date: |
Thu, 1 Sep 2011 01:57:09 +0400 |
Signed-off-by: Max Filippov <address@hidden>
---
v2 -> v3 changes:
- handle integer overflow for QUOS/REMS.
---
target-xtensa/translate.c | 77 ++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 76 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 1fe212d..949c7f5 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -878,7 +878,82 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 2: /*RST2*/
- TBD();
+ if (_OP2 >= 12) {
+ HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
+ int label = gen_new_label();
+ tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
+ gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
+ gen_set_label(label);
+ }
+
+ switch (_OP2) {
+ case 8: /*MULLi*/
+ HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
+ tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
+
+ case 10: /*MULUHi*/
+ case 11: /*MULSHi*/
+ HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
+ {
+ TCGv_i64 r = tcg_temp_new_i64();
+ TCGv_i64 s = tcg_temp_new_i64();
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ if (_OP2 == 10) {
+ tcg_gen_extu_i32_i64(s, cpu_R[RRR_S]);
+ tcg_gen_extu_i32_i64(t, cpu_R[RRR_T]);
+ } else {
+ tcg_gen_ext_i32_i64(s, cpu_R[RRR_S]);
+ tcg_gen_ext_i32_i64(t, cpu_R[RRR_T]);
+ }
+ tcg_gen_mul_i64(r, s, t);
+ tcg_gen_shri_i64(r, r, 32);
+ tcg_gen_trunc_i64_i32(cpu_R[RRR_R], r);
+
+ tcg_temp_free_i64(r);
+ tcg_temp_free_i64(s);
+ tcg_temp_free_i64(t);
+ }
+ break;
+
+ case 12: /*QUOUi*/
+ tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
+
+ case 13: /*QUOSi*/
+ case 15: /*REMSi*/
+ {
+ int label1 = gen_new_label();
+ int label2 = gen_new_label();
+
+ tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
+ label1);
+ tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
+ label1);
+ tcg_gen_movi_i32(cpu_R[RRR_R],
+ _OP2 == 13 ? 0x80000000 : 0);
+ tcg_gen_br(label2);
+ gen_set_label(label1);
+ if (_OP2 == 13) {
+ tcg_gen_div_i32(cpu_R[RRR_R],
+ cpu_R[RRR_S], cpu_R[RRR_T]);
+ } else {
+ tcg_gen_rem_i32(cpu_R[RRR_R],
+ cpu_R[RRR_S], cpu_R[RRR_T]);
+ }
+ gen_set_label(label2);
+ }
+ break;
+
+ case 14: /*REMUi*/
+ tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
+ break;
+
+ default: /*reserved*/
+ RESERVED();
+ break;
+ }
break;
case 3: /*RST3*/
--
1.7.6
- [Qemu-devel] [PATCH v3 05/32] target-xtensa: implement RT0 group, (continued)
- [Qemu-devel] [PATCH v3 05/32] target-xtensa: implement RT0 group, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 14/32] target-xtensa: implement SYNC group, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 08/32] target-xtensa: implement JX/RET0/CALLX, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 02/32] target-xtensa: add target to the configure script, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 26/32] target-xtensa: implement CPENABLE and PRID SRs, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 04/32] target-xtensa: implement narrow instructions, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 15/32] target-xtensa: implement CACHE group, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 09/32] target-xtensa: add special and user registers, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 16/32] target-xtensa: add PS register and access control, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 06/32] target-xtensa: add sample board, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 18/32] target-xtensa: implement RST2 group (32 bit mul/div/rem),
Max Filippov <=
- [Qemu-devel] [PATCH v3 21/32] target-xtensa: implement extended L32R, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 12/32] target-xtensa: implement LSAI group, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 07/32] target-xtensa: implement conditional jumps, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 10/32] target-xtensa: implement RST3 group, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 22/32] target-xtensa: implement unaligned exception option, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 27/32] target-xtensa: implement relocatable vectors, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 20/32] target-xtensa: implement loop option, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 13/32] target-xtensa: mark reserved and TBD opcodes, Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 11/32] target-xtensa: implement shifts (ST1 and RST1 groups), Max Filippov, 2011/08/31
- [Qemu-devel] [PATCH v3 23/32] target-xtensa: implement SIMCALL, Max Filippov, 2011/08/31