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[Qemu-devel] [PATCH v5 09/33] target-xtensa: add special and user regist
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH v5 09/33] target-xtensa: add special and user registers |
Date: |
Tue, 6 Sep 2011 03:55:33 +0400 |
Special Registers hold the majority of the state added to the processor
by the options. See ISA, 5.3 for details.
User Registers hold state added in support of designer's TIE and in some
cases of options that Tensilica provides. See ISA, 5.4 for details.
Only registers mapped in sregnames or uregnames are considered valid.
Signed-off-by: Max Filippov <address@hidden>
---
target-xtensa/cpu.h | 7 ++++++
target-xtensa/translate.c | 49 +++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index c323891..8c3fe2e 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -99,6 +99,12 @@ enum {
XTENSA_OPTION_TRACE_PORT,
};
+enum {
+ THREADPTR = 231,
+ FCR = 232,
+ FSR = 233,
+};
+
typedef struct XtensaConfig {
const char *name;
uint64_t options;
@@ -109,6 +115,7 @@ typedef struct CPUXtensaState {
uint32_t regs[16];
uint32_t pc;
uint32_t sregs[256];
+ uint32_t uregs[256];
CPU_COMMON
} CPUXtensaState;
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 78fffc5..358ea96 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -52,9 +52,20 @@ typedef struct DisasContext {
static TCGv_ptr cpu_env;
static TCGv_i32 cpu_pc;
static TCGv_i32 cpu_R[16];
+static TCGv_i32 cpu_SR[256];
+static TCGv_i32 cpu_UR[256];
#include "gen-icount.h"
+static const char * const sregnames[256] = {
+};
+
+static const char * const uregnames[256] = {
+ [THREADPTR] = "THREADPTR",
+ [FCR] = "FCR",
+ [FSR] = "FSR",
+};
+
void xtensa_translate_init(void)
{
static const char * const regnames[] = {
@@ -74,6 +85,22 @@ void xtensa_translate_init(void)
offsetof(CPUState, regs[i]),
regnames[i]);
}
+
+ for (i = 0; i < 256; ++i) {
+ if (sregnames[i]) {
+ cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUState, sregs[i]),
+ sregnames[i]);
+ }
+ }
+
+ for (i = 0; i < 256; ++i) {
+ if (uregnames[i]) {
+ cpu_UR[i] = tcg_global_mem_new_i32(TCG_AREG0,
+ offsetof(CPUState, uregs[i]),
+ uregnames[i]);
+ }
+ }
#define GEN_HELPER 2
#include "helpers.h"
}
@@ -784,9 +811,27 @@ void gen_intermediate_code_pc(CPUState *env,
TranslationBlock *tb)
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
int flags)
{
- int i;
+ int i, j;
+
+ cpu_fprintf(f, "PC=%08x\n\n", env->pc);
+
+ for (i = j = 0; i < 256; ++i) {
+ if (sregnames[i]) {
+ cpu_fprintf(f, "%s=%08x%c", sregnames[i], env->sregs[i],
+ (j++ % 4) == 3 ? '\n' : ' ');
+ }
+ }
+
+ cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
+
+ for (i = j = 0; i < 256; ++i) {
+ if (uregnames[i]) {
+ cpu_fprintf(f, "%s=%08x%c", uregnames[i], env->uregs[i],
+ (j++ % 4) == 3 ? '\n' : ' ');
+ }
+ }
- cpu_fprintf(f, "PC=%08x\n", env->pc);
+ cpu_fprintf(f, (j % 4) == 0 ? "\n" : "\n\n");
for (i = 0; i < 16; ++i) {
cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
--
1.7.6
- [Qemu-devel] [PATCH v5 13/33] target-xtensa: mark reserved and TBD opcodes, (continued)
- [Qemu-devel] [PATCH v5 13/33] target-xtensa: mark reserved and TBD opcodes, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 18/33] target-xtensa: implement RST2 group (32 bit mul/div/rem), Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 30/33] target-xtensa: implement boolean option, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 23/33] target-xtensa: implement SIMCALL, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 22/33] target-xtensa: implement unaligned exception option, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 26/33] target-xtensa: implement CPENABLE and PRID SRs, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 16/33] target-xtensa: add PS register and access control, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 20/33] target-xtensa: implement loop option, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 32/33] MAINTAINERS: add xtensa maintainer, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 19/33] target-xtensa: implement windowed registers, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 09/33] target-xtensa: add special and user registers,
Max Filippov <=
- [Qemu-devel] [PATCH v5 27/33] target-xtensa: implement relocatable vectors, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 15/33] target-xtensa: implement CACHE group, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 17/33] target-xtensa: implement exceptions, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 29/33] target-xtensa: implement memory protection options, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 21/33] target-xtensa: implement extended L32R, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 25/33] target-xtensa: implement accurate window check, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 28/33] target-xtensa: add gdb support, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 24/33] target-xtensa: implement interrupt option, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 31/33] target-xtensa: add dc232b core and board, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 33/33] target-xtensa: add regression testsuite, Max Filippov, 2011/09/05