Re: [Qemu-devel] [PATCH] pci: add standard bridge device

[Wen Congyang]

At 08/19/2011 11:26 PM, Avi Kivity Write:
> On 08/18/2011 10:12 PM, Wen Congyang wrote:
>> >>
>> >>  The following patch can fix this problem, but I'm not sure whether it
>> >>  is right.
>> >
>> >  It's correct but insufficient, the filtering code (pci_bridge_filter)
>> >  needs to be updated to use the memory API.
>>
>> I read the function pci_bridge_filter(), and the function only read
>> PCI bridge's config space(command, base and limit). If base>  limit,
>> it will set addr to PCI_BAR_UNMAPPED.
>>
>> I do not find anything that needs to updated to use the memory API.
> 
> Currently it doesn't do any filtering at all.  Bridges need to create a
> new address space, then attach aliases of this region (corresponding to
> the filtered area and to the legacy vga space) to the parent bus'
> address space.
> 
>> I add a scsi controller on pci bus1, and a scsi disk on this controller.
>> I can read and write this disk, and I do not meet any problem.
>>
> 
> However, filtering doesn't work.  You could put a BAR outside the
> filtered area and it would be visible to the guest.
> 

I test it on real hardware. If I put a BAR outside the filterer area, and
then run 'lspci -vv', the BAR does not change:
# lspci -vv
...
00:1c.1 PCI bridge: Intel Corporation N10/ICH 7 Family PCI Express Port 2 (rev 
01) (prog-if 00 [Normal decode])
...
        Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
        I/O behind bridge: 0000d000-0000dfff
        Memory behind bridge: fea00000-feafffff
        Prefetchable memory behind bridge: 0000000080400000-00000000805fffff
...
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev e1) (prog-if 01 
[Subtractive decode])
...
        Bus: primary=00, secondary=03, subordinate=03, sec-latency=32
        I/O behind bridge: 0000e000-0000efff
        Memory behind bridge: feb00000-febfffff
        Prefetchable memory behind bridge: 0000000080600000-00000000806fffff
...
03:01.0 Ethernet controller: Realtek Semiconductor Co., Ltd. 
RTL-8139/8139C/8139C+ (rev 10)
...
        Region 0: I/O ports at a800 [size=256]
        Region 1: Memory at febfbc00 (32-bit, non-prefetchable) [size=256]
        Expansion ROM at 80600000 [disabled] [size=128K]
...

# od -t x1 /sys/bus/pci/devices/0000\:03\:01.0/config
0000000 ec 10 39 81 03 00 90 82 10 00 00 02 00 00 00 00
0000020 01 a8 00 00 00 bc af fe 00 00 00 00 00 00 00 00
0000040 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
0000060 00 00 bc fe 50 00 00 00 00 00 00 00 06 01 20 40
0000100 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000120 01 00 02 76 00 00 00 00 00 00 00 00 00 00 00 00
0000140 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*
0000400
The BAR1 is feafbc00, and it is in the bus2's range.
I map the BAR(mmap /sys/bus/pci/devices/0000\:03\:01.0/resource1), and find
I can read and write the memory.

Thanks
Wen Congyang