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Re: [Qemu-devel] [PATCH 11/22] i8259: Update IRQ state after reset


From: Blue Swirl
Subject: Re: [Qemu-devel] [PATCH 11/22] i8259: Update IRQ state after reset
Date: Sun, 2 Oct 2011 20:18:38 +0000

On Sun, Oct 2, 2011 at 8:14 PM, Avi Kivity <address@hidden> wrote:
>> >
>> > Say the target device's output has an AND connecting #RESET and an
>> > input, to the output.  When #RESET is asserted, the input is
>> > driven low.  The output is connected to a counter.
>> >
>> > When #RESET is asserted, the source device's A and B are raised
>> > high, with delay Da and Db.  If they are different, the XNOR gate
>> > generates a pulse with delay Dx.  If Dx is smaller than the AND
>> > gate's delay Drm, then the counter will count.
>>
>> On a real device, the reset and clocks are the few global signals
>> available, distributed to most places. The counter would be
>> constructed of JK flip flops and the reset line would be connected to
>> the clear line of the flip flops. Then the counters don't count while
>> reset is active.
>>
>>
>
> You could have a momentary count if the RESET input's gate delay to the 
> counter is slower than the other inputs.  It would be cleared immediately 
> afterwards (when phase 1 sweeps into the counter as well).
>
> What I'm saying is that RESET order isn't defined on real hardware either, 
> due to signal propagation effects.

Yes, but there the millions of reset cycles help immensely to suppress
the effects.



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