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Re: [Qemu-devel] [PATCH 11/22] i8259: Update IRQ state after reset


From: Blue Swirl
Subject: Re: [Qemu-devel] [PATCH 11/22] i8259: Update IRQ state after reset
Date: Sun, 2 Oct 2011 20:30:33 +0000

On Sun, Oct 2, 2011 at 8:21 PM, Avi Kivity <address@hidden> wrote:
>> >
>> > What I'm saying is that RESET order isn't defined on real hardware
>> > either, due to signal propagation effects.
>>
>> Yes, but there the millions of reset cycles help immensely to
>> suppress
>> the effects.
>>
>
> That's modeled correctly.  After the end of phase 1, everything is settled.  
> During phase 1, you can see some spikes, but you can see them on real 
> hardware as well.

No. With two phase reset (like I understood it), at the beginning of
phase, everything internal is settled (registers reset), no I/O. After
the phase 1, starting the external I/O activities cause spikes but
these are not suppressed.

In my 3-phase version, the reset would be held during phase 2 just to
handle the spikes (registers continue to be reset as needed).



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