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[Qemu-devel] [PATCH 23/22] ppc: Alter CPU state to mask out TCG unimplem
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 23/22] ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriate |
Date: |
Mon, 31 Oct 2011 05:12:05 +0100 |
From: David Gibson <address@hidden>
The CPU state contains two bitmaps, initialized from the CPU spec
which describes which instructions are implemented on the CPU. A
couple of bits are defined which cover instructions (VSX and DFP)
which are not currently implemented in TCG. So far, these are only
used to handle the case of -cpu host because a KVM guest can use
the instructions when the host CPU supports them.
However, it's a mild layering violation to simply not include those
bits in the CPU descriptions for those CPUs that do support them,
just because we can't handle them in TCG. This patch corrects the
situation, so that the instruction bits _are_ shown correctly in the
cpu spec table, but are masked out from the cpu state in the non-KVM
case.
Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/cpu.h | 26 ++++++++++++++++++++++++++
target-ppc/translate_init.c | 20 +++++++++++++++++---
2 files changed, 43 insertions(+), 3 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 3ef4eba..e84108c 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1856,6 +1856,30 @@ enum {
/* popcntw and popcntd instructions */
PPC_POPCNTWD = 0x8000000000000000ULL,
+#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
+ | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
+ | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
+ | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
+ | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
+ | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
+ | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
+ | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
+ | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
+ | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
+ | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
+ | PPC_MEM_SYNC | PPC_MEM_EIEIO \
+ | PPC_CACHE | PPC_CACHE_ICBI \
+ | PPC_CACHE_DCBZ | PPC_CACHE_DCBZT \
+ | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
+ | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
+ | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
+ | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
+ | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
+ | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
+ | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
+ | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
+ | PPC_POPCNTWD)
+
/* extended type values */
/* BookE 2.06 PowerPC specification */
@@ -1864,6 +1888,8 @@ enum {
PPC2_VSX = 0x0000000000000002ULL,
/* Decimal Floating Point (DFP) */
PPC2_DFP = 0x0000000000000004ULL,
+
+#define PPC_TCG_INSNS2 (PPC2_BOOKE206)
};
/*****************************************************************************/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4dfd7f3..8a7233f 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -6519,9 +6519,7 @@ static void init_proc_970MP (CPUPPCState *env)
PPC_64B | PPC_ALTIVEC | \
PPC_SEGMENT_64B | PPC_SLBI | \
PPC_POPCNTB | PPC_POPCNTWD)
-/* FIXME: Should also have PPC2_VSX and PPC2_DFP, but we don't
- * implement those in TCG yet */
-#define POWERPC_INSNS2_POWER7 (PPC_NONE)
+#define POWERPC_INSNS2_POWER7 (PPC2_VSX | PPC2_DFP)
#define POWERPC_MSRM_POWER7 (0x800000000204FF36ULL)
#define POWERPC_MMU_POWER7 (POWERPC_MMU_2_06)
#define POWERPC_EXCP_POWER7 (POWERPC_EXCP_POWER7)
@@ -9848,6 +9846,22 @@ int cpu_ppc_register_internal (CPUPPCState *env, const
ppc_def_t *def)
env->bus_model = def->bus_model;
env->insns_flags = def->insns_flags;
env->insns_flags2 = def->insns_flags2;
+ if (!kvm_enabled()) {
+ /* TCG doesn't (yet) emulate some groups of instructions that
+ * are implemented on some otherwise supported CPUs (e.g. VSX
+ * and decimal floating point instructions on POWER7). We
+ * remove unsupported instruction groups from the cpu state's
+ * instruction masks and hope the guest can cope. For at
+ * least the pseries machine, the unavailability of these
+ * instructions can be advertise to the guest via the device
+ * tree.
+ *
+ * FIXME: we should have a similar masking for CPU features
+ * not accessible under KVM, but so far, there aren't any of
+ * those. */
+ env->insns_flags &= PPC_TCG_INSNS;
+ env->insns_flags2 &= PPC_TCG_INSNS2;
+ }
env->flags = def->flags;
env->bfd_mach = def->bfd_mach;
env->check_pow = def->check_pow;
--
1.6.0.2
- [Qemu-devel] [PATCH 11/22] ppc: Remove broken partial PVR matching, (continued)
- [Qemu-devel] [PATCH 11/22] ppc: Remove broken partial PVR matching, Alexander Graf, 2011/10/30
- [Qemu-devel] [PATCH 21/22] KVM: PPC: Override host vmx/vsx/dfp only when information known, Alexander Graf, 2011/10/30
- [Qemu-devel] [PATCH 14/22] pseries: Under kvm use guest cpu = host cpu by default, Alexander Graf, 2011/10/30
- [Qemu-devel] [PATCH 08/22] ppc: Generalize the kvmppc_get_clockfreq() function, Alexander Graf, 2011/10/30
- [Qemu-devel] [PATCH 22/22] pseries: Allow writes to KVM accelerated TCE table, Alexander Graf, 2011/10/30
- [Qemu-devel] [PATCH 12/22] ppc: First cut implementation of -cpu host, Alexander Graf, 2011/10/30
- [Qemu-devel] [PATCH 19/22] pseries: Correct vmx/dfp handling in both KVM and TCG cases, Alexander Graf, 2011/10/30
- [Qemu-devel] [PATCH 20/22] ppc: Fix up usermode only builds, Alexander Graf, 2011/10/30
- [Qemu-devel] [PATCH 16/22] PPC: Disable non-440 CPUs for ppcemb target, Alexander Graf, 2011/10/30
- [Qemu-devel] [PATCH 10/22] pseries: Update SLOF firmware image, Alexander Graf, 2011/10/30
- [Qemu-devel] [PATCH 23/22] ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriate,
Alexander Graf <=
- [Qemu-devel] [PATCH 24/22] pseries: Add partial support for PCI, Alexander Graf, 2011/10/31
- Re: [Qemu-devel] [PULL 00/22] ppc patch queue 2011-10-30, Alexander Graf, 2011/10/31