From ff9f5fa760c676c92e64b1aab9de1391c5d282e1 Mon Sep 17 00:00:00 2001 Message-Id: In-Reply-To: References: From: Blue Swirl Date: Mon, 1 Aug 2011 09:20:58 +0000 Subject: [PATCH 2/9] Sparc: avoid AREG0 for softint op helpers and Leon cache control Make softint op helpers and Leon cache irq manager take a parameter for CPUState instead of relying on global env. Move the functions to int{32,64}_helper.c. Signed-off-by: Blue Swirl --- target-sparc/cpu.h | 31 +++++++++++--- target-sparc/helper.h | 6 +- target-sparc/int32_helper.c | 47 +++++++++++++++++++++- target-sparc/int64_helper.c | 40 ++++++++++++++++++ target-sparc/op_helper.c | 94 ------------------------------------------- target-sparc/translate.c | 6 +- 6 files changed, 117 insertions(+), 107 deletions(-) diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 6bf9275..ce1e668 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -335,6 +335,27 @@ enum { #define SFSR_CT_NOTRANS (3ULL << 4) #define SFSR_CT_MASK (3ULL << 4) +/* Leon3 cache control */ + +/* Cache control: emulate the behavior of cache control registers but without + any effect on the emulated */ + +#define CACHE_STATE_MASK 0x3 +#define CACHE_DISABLED 0x0 +#define CACHE_FROZEN 0x1 +#define CACHE_ENABLED 0x3 + +/* Cache Control register fields */ + +#define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ +#define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ +#define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ +#define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ +#define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ +#define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ +#define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ +#define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ + typedef struct SparcTLBEntry { uint64_t tag; uint64_t tte; @@ -478,7 +499,7 @@ typedef struct CPUSPARCState { sparc_def_t *def; void *irq_manager; - void (*qemu_irq_ack) (void *irq_manager, int intno); + void (*qemu_irq_ack)(CPUState *env, void *irq_manager, int intno); /* Leon3 cache control */ uint32_t cache_control; @@ -523,8 +544,9 @@ int cpu_cwp_inc(CPUState *env1, int cwp); int cpu_cwp_dec(CPUState *env1, int cwp); void cpu_set_cwp(CPUState *env1, int new_cwp); -/* op_helper.c */ -void leon3_irq_manager(void *irq_manager, int intno); +/* int_helper.c */ +void do_interrupt(CPUState *env); +void leon3_irq_manager(CPUState *env, void *irq_manager, int intno); /* sun4m.c, sun4u.c */ void cpu_check_irqs(CPUSPARCState *env); @@ -721,9 +743,6 @@ static inline bool tb_am_enabled(int tb_flags) #endif } -/* helper.c */ -void do_interrupt(CPUState *env); - static inline bool cpu_has_work(CPUState *env1) { return (env1->interrupt_request & CPU_INTERRUPT_HARD) && diff --git a/target-sparc/helper.h b/target-sparc/helper.h index b18cbc6..943b4ba 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -24,9 +24,9 @@ DEF_HELPER_4(ldf_asi, void, tl, int, int, int) DEF_HELPER_4(stf_asi, void, tl, int, int, int) DEF_HELPER_4(cas_asi, tl, tl, tl, tl, i32) DEF_HELPER_4(casx_asi, tl, tl, tl, tl, i32) -DEF_HELPER_1(set_softint, void, i64) -DEF_HELPER_1(clear_softint, void, i64) -DEF_HELPER_1(write_softint, void, i64) +DEF_HELPER_2(set_softint, void, env, i64) +DEF_HELPER_2(clear_softint, void, env, i64) +DEF_HELPER_2(write_softint, void, env, i64) DEF_HELPER_2(tick_set_count, void, ptr, i64) DEF_HELPER_1(tick_get_count, i64, ptr) DEF_HELPER_2(tick_set_limit, void, ptr, i64) diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c index 219a6c6..1c6ba6d 100644 --- a/target-sparc/int32_helper.c +++ b/target-sparc/int32_helper.c @@ -20,6 +20,14 @@ #include "cpu.h" //#define DEBUG_PCALL +//#define DEBUG_CACHE_CONTROL + +#ifdef DEBUG_CACHE_CONTROL +#define DPRINTF_CACHE_CONTROL(fmt, ...) \ + do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0) +#else +#define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0) +#endif #ifdef DEBUG_PCALL static const char * const excp_names[0x80] = { @@ -119,7 +127,44 @@ void do_interrupt(CPUState *env) #if !defined(CONFIG_USER_ONLY) /* IRQ acknowledgment */ if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) { - env->qemu_irq_ack(env->irq_manager, intno); + env->qemu_irq_ack(env, env->irq_manager, intno); } #endif } + +#if !defined(CONFIG_USER_ONLY) +static void leon3_cache_control_int(CPUState *env) +{ + uint32_t state = 0; + + if (env->cache_control & CACHE_CTRL_IF) { + /* Instruction cache state */ + state = env->cache_control & CACHE_STATE_MASK; + if (state == CACHE_ENABLED) { + state = CACHE_FROZEN; + DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n"); + } + + env->cache_control &= ~CACHE_STATE_MASK; + env->cache_control |= state; + } + + if (env->cache_control & CACHE_CTRL_DF) { + /* Data cache state */ + state = (env->cache_control >> 2) & CACHE_STATE_MASK; + if (state == CACHE_ENABLED) { + state = CACHE_FROZEN; + DPRINTF_CACHE_CONTROL("Data cache: freeze\n"); + } + + env->cache_control &= ~(CACHE_STATE_MASK << 2); + env->cache_control |= (state << 2); + } +} + +void leon3_irq_manager(CPUState *env, void *irq_manager, int intno) +{ + leon3_irq_ack(irq_manager, intno); + leon3_cache_control_int(env); +} +#endif diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c index 2bb1910..c9c5e0e 100644 --- a/target-sparc/int64_helper.c +++ b/target-sparc/int64_helper.c @@ -18,8 +18,17 @@ */ #include "cpu.h" +#include "helper.h" //#define DEBUG_PCALL +//#define DEBUG_PSTATE + +#ifdef DEBUG_PSTATE +#define DPRINTF_PSTATE(fmt, ...) \ + do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0) +#else +#define DPRINTF_PSTATE(fmt, ...) do {} while (0) +#endif #ifdef DEBUG_PCALL static const char * const excp_names[0x80] = { @@ -162,3 +171,34 @@ trap_state *cpu_tsptr(CPUState* env) { return &env->ts[env->tl & MAXTL_MASK]; } + +static void do_modify_softint(CPUState *env, const char *operation, + uint32_t value) +{ + if (env->softint != value) { + env->softint = value; + DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint); +#if !defined(CONFIG_USER_ONLY) + if (cpu_interrupts_enabled(env)) { + cpu_check_irqs(env); + } +#endif + } +} + +void helper_set_softint(CPUState *env, uint64_t value) +{ + do_modify_softint(env, "helper_set_softint", + env->softint | (uint32_t)value); +} + +void helper_clear_softint(CPUState *env, uint64_t value) +{ + do_modify_softint(env, "helper_clear_softint", + env->softint & (uint32_t)~value); +} + +void helper_write_softint(CPUState *env, uint64_t value) +{ + do_modify_softint(env, "helper_write_softint", (uint32_t)value); +} diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index cb0bf2e..e0a13fd 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -11,7 +11,6 @@ //#define DEBUG_UNALIGNED //#define DEBUG_UNASSIGNED //#define DEBUG_ASI -//#define DEBUG_PSTATE //#define DEBUG_CACHE_CONTROL #ifdef DEBUG_MMU @@ -33,13 +32,6 @@ do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0) #endif -#ifdef DEBUG_PSTATE -#define DPRINTF_PSTATE(fmt, ...) \ - do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0) -#else -#define DPRINTF_PSTATE(fmt, ...) do {} while (0) -#endif - #ifdef DEBUG_CACHE_CONTROL #define DPRINTF_CACHE_CONTROL(fmt, ...) \ do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0) @@ -60,27 +52,6 @@ #define QT0 (env->qt0) #define QT1 (env->qt1) -/* Leon3 cache control */ - -/* Cache control: emulate the behavior of cache control registers but without - any effect on the emulated */ - -#define CACHE_STATE_MASK 0x3 -#define CACHE_DISABLED 0x0 -#define CACHE_FROZEN 0x1 -#define CACHE_ENABLED 0x3 - -/* Cache Control register fields */ - -#define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ -#define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ -#define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ -#define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ -#define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ -#define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ -#define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ -#define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ - #if !defined(CONFIG_USER_ONLY) static void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, int is_asi, int size); @@ -384,35 +355,6 @@ static void dump_asi(const char *txt, target_ulong addr, int asi, int size, /* Leon3 cache control */ -static void leon3_cache_control_int(void) -{ - uint32_t state = 0; - - if (env->cache_control & CACHE_CTRL_IF) { - /* Instruction cache state */ - state = env->cache_control & CACHE_STATE_MASK; - if (state == CACHE_ENABLED) { - state = CACHE_FROZEN; - DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n"); - } - - env->cache_control &= ~CACHE_STATE_MASK; - env->cache_control |= state; - } - - if (env->cache_control & CACHE_CTRL_DF) { - /* Data cache state */ - state = (env->cache_control >> 2) & CACHE_STATE_MASK; - if (state == CACHE_ENABLED) { - state = CACHE_FROZEN; - DPRINTF_CACHE_CONTROL("Data cache: freeze\n"); - } - - env->cache_control &= ~(CACHE_STATE_MASK << 2); - env->cache_control |= (state << 2); - } -} - static void leon3_cache_control_st(target_ulong addr, uint64_t val, int size) { DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n", @@ -477,12 +419,6 @@ static uint64_t leon3_cache_control_ld(target_ulong addr, int size) return ret; } -void leon3_irq_manager(void *irq_manager, int intno) -{ - leon3_irq_ack(irq_manager, intno); - leon3_cache_control_int(); -} - uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) { uint64_t ret = 0; @@ -2455,36 +2391,6 @@ void helper_stqf(target_ulong addr, int mem_idx) #endif } -#ifdef TARGET_SPARC64 -static void do_modify_softint(const char *operation, uint32_t value) -{ - if (env->softint != value) { - env->softint = value; - DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint); -#if !defined(CONFIG_USER_ONLY) - if (cpu_interrupts_enabled(env)) { - cpu_check_irqs(env); - } -#endif - } -} - -void helper_set_softint(uint64_t value) -{ - do_modify_softint("helper_set_softint", env->softint | (uint32_t)value); -} - -void helper_clear_softint(uint64_t value) -{ - do_modify_softint("helper_clear_softint", env->softint & (uint32_t)~value); -} - -void helper_write_softint(uint64_t value) -{ - do_modify_softint("helper_write_softint", (uint32_t)value); -} -#endif - #if !defined(CONFIG_USER_ONLY) static void do_unaligned_access(target_ulong addr, int is_write, int is_user, diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 01849a6..714808b 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3412,19 +3412,19 @@ static void disas_sparc_insn(DisasContext * dc) if (!supervisor(dc)) goto illegal_insn; tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); - gen_helper_set_softint(cpu_tmp64); + gen_helper_set_softint(cpu_env, cpu_tmp64); break; case 0x15: /* Softint clear */ if (!supervisor(dc)) goto illegal_insn; tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); - gen_helper_clear_softint(cpu_tmp64); + gen_helper_clear_softint(cpu_env, cpu_tmp64); break; case 0x16: /* Softint write */ if (!supervisor(dc)) goto illegal_insn; tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); - gen_helper_write_softint(cpu_tmp64); + gen_helper_write_softint(cpu_env, cpu_tmp64); break; case 0x17: /* Tick compare */ #if !defined(CONFIG_USER_ONLY) -- 1.7.2.5