Re: [Qemu-devel] [PATCH 08/15] hw/arm_gic.c: lower IRQ only on changing of enable bit.

[Paul Brook]

> In previous version IRQ was lowered every time if enable bits were
> not set. If platform has splitted IRQ source to pass IRQ to two
> identical GICs simultaneously in first of which IRQ passing is
> enabled but in second is disabled, handling IRQ by second GIC would
> lower IRQ previously raised by first GIC.
> Linux kernel v3.0 faces this problem.
> The problem is avoided if IRQ is only lowered as result of
> transitioning enable bits to zeroes.

This is almost certainly wrong.  IRQ lines are state based, not event based. 
Re-asserting an existing level should always be a no-op.

My guess is your real bug it that your IRQ wiring is broken, and you have 
multiple outputs connected to a single input. Don't do that. Ever.  If you 
need to connent multiple output pins to a single input pin then you need an 
explicit device (e.g. an or gate) in between.

Paul