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[Qemu-devel] [PATCH 4/8] hw/mpcore.c: Use the GIC memory regions for the
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 4/8] hw/mpcore.c: Use the GIC memory regions for the CPU interface |
Date: |
Mon, 12 Dec 2011 10:47:45 +0000 |
Switch to using the GIC memory regions for the CPU interface
rather than hand implementing them as a subcase of mpcore_priv_read()
and mpcore_priv_write().
Signed-off-by: Peter Maydell <address@hidden>
---
hw/mpcore.c | 35 ++++++++++-------------------------
1 files changed, 10 insertions(+), 25 deletions(-)
diff --git a/hw/mpcore.c b/hw/mpcore.c
index 3d64609..a0af1ad 100644
--- a/hw/mpcore.c
+++ b/hw/mpcore.c
@@ -41,7 +41,7 @@ static uint64_t mpcore_priv_read(void *opaque,
target_phys_addr_t offset,
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
int id;
- offset &= 0xfff;
+ offset &= 0xff;
if (offset < 0x100) {
/* SCU */
switch (offset) {
@@ -57,17 +57,6 @@ static uint64_t mpcore_priv_read(void *opaque,
target_phys_addr_t offset,
default:
goto bad_reg;
}
- } else if (offset < 0x600) {
- /* Interrupt controller. */
- if (offset < 0x200) {
- id = gic_get_current_cpu();
- } else {
- id = (offset - 0x200) >> 8;
- if (id >= s->num_cpu) {
- return 0;
- }
- }
- return gic_cpu_read(&s->gic, id, offset & 0xff);
}
bad_reg:
hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
@@ -78,8 +67,7 @@ static void mpcore_priv_write(void *opaque,
target_phys_addr_t offset,
uint64_t value, unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
- int id;
- offset &= 0xfff;
+ offset &= 0xff;
if (offset < 0x100) {
/* SCU */
switch (offset) {
@@ -92,16 +80,6 @@ static void mpcore_priv_write(void *opaque,
target_phys_addr_t offset,
default:
goto bad_reg;
}
- } else if (offset < 0x600) {
- /* Interrupt controller. */
- if (offset < 0x200) {
- id = gic_get_current_cpu();
- } else {
- id = (offset - 0x200) >> 8;
- }
- if (id < s->num_cpu) {
- gic_cpu_write(&s->gic, id, offset & 0xff, value);
- }
}
return;
bad_reg:
@@ -129,8 +107,15 @@ static void mpcore_priv_map_setup(mpcore_priv_state *s)
SysBusDevice *busdev = sysbus_from_qdev(s->mptimer);
memory_region_init(&s->container, "mpcode-priv-container", 0x2000);
memory_region_init_io(&s->iomem, &mpcore_priv_ops, s, "mpcode-priv",
- 0x1000);
+ 0x100);
memory_region_add_subregion(&s->container, 0, &s->iomem);
+ /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
+ * at 0x200, 0x300...
+ */
+ for (i = 0; i < (s->num_cpu + 1); i++) {
+ target_phys_addr_t offset = 0x100 + (i * 0x100);
+ memory_region_add_subregion(&s->container, offset,
&s->gic.cpuiomem[i]);
+ }
/* Add the regions for timer and watchdog for "current CPU" and
* for each specific CPU.
*/
--
1.7.1
- [Qemu-devel] [PULL 0/8] arm-devs queue, Peter Maydell, 2011/12/12
- [Qemu-devel] [PATCH 8/8] hw/mpcore.c: Merge with hw/arm11mpcore.c, Peter Maydell, 2011/12/12
- [Qemu-devel] [PATCH 2/8] hw/arm_mptimer.c: Turn ARM MPcore private timers into qdev devices, Peter Maydell, 2011/12/12
- [Qemu-devel] [PATCH 5/8] hw/realview_gic: Use GIC memory region for the CPU interface, Peter Maydell, 2011/12/12
- [Qemu-devel] [PATCH 4/8] hw/mpcore.c: Use the GIC memory regions for the CPU interface,
Peter Maydell <=
- [Qemu-devel] [PATCH 3/8] hw/arm_gic: Expose GIC CPU interfaces as sysbus memory regions, Peter Maydell, 2011/12/12
- [Qemu-devel] [PATCH 1/8] Fix sp804 dual-timer, Peter Maydell, 2011/12/12
- [Qemu-devel] [PATCH 7/8] hw/a9mpcore.c: Implement A9MP peripherals rather than 11MPcore ones, Peter Maydell, 2011/12/12
- [Qemu-devel] [PATCH 6/8] hw/mpcore: Clean up mpcore_priv_read/write as they are now SCU only, Peter Maydell, 2011/12/12
- Re: [Qemu-devel] [PULL 0/8] arm-devs queue, Anthony Liguori, 2011/12/12