Re: [Qemu-devel] [PATCH v4 04/11] ARM: exynos4210: IRQ subsystem support.

[Peter Maydell]

On 22 December 2011 12:50, Evgeny Voevodin <address@hidden> wrote:
> Do you mean to use s->gic.cpuiomem[NCPU+1] as in a9mpcore.c a9mp_priv_init()
> done?

It depends what you want. If you need a memory region
which behaves like "CPU interface for whatever the core
making this read/write is", that is cpuiomem[0]. If you
need a memory region which behaves like "CPU interface
for core 0" regardless of which core accesses it, that
is cpuiomem[1]. For "CPU interface for core 1", cpuiomem[2].

11MPCore uses all of these. A9MP's built in GIC only
needs cpuiomem[0].

If you need any of these at more than one address in the
memory map, you need to create a memory region alias.

> What should we use if we need the same for distributor which is represented
> as gic.iomem?
> Extend distributor in the same way?

Your current wrapper functions for the distributor read/write
routines don't do anything to pass a specific CPU number
into the underlying GIC distributor read/write functions.
So it should be sufficient to just map the distributor's
existing memory region (again, if you need it in more than
one place in the address space then create an alias memory
region for it).

-- PMM