[Qemu-devel] [PATCH v5 4/7] arm: add dummy gic security registers

[Mark Langsdorf]

From: Rob Herring <address@hidden>

Implement handling for the RAZ/WI gic security registers.

Signed-off-by: Rob Herring <address@hidden>
Signed-off-by: Mark Langsdorf <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
Changes from v2, v3, v4
        None
Changes from v1
        Moved handling back inside the 0-0x100 block
        Added more clarifying comments

 hw/arm_gic.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 9b52119..0339cf5 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -282,6 +282,10 @@ static uint32_t gic_dist_readb(void *opaque, 
target_phys_addr_t offset)
             return ((GIC_NIRQ / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
         if (offset < 0x08)
             return 0;
+        if (offset >= 0x80) {
+            /* Interrupt Security , RAZ/WI */
+            return 0;
+        }
 #endif
         goto bad_reg;
     } else if (offset < 0x200) {
@@ -413,6 +417,8 @@ static void gic_dist_writeb(void *opaque, 
target_phys_addr_t offset,
             DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
         } else if (offset < 4) {
             /* ignored.  */
+        } else if (offset >= 0x80) {
+            /* Interrupt Security Registers, RAZ/WI */
         } else {
             goto bad_reg;
         }
-- 
1.7.5.4