[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH] Rename target_phys_addr_t to Phys
|
From: |
Avi Kivity |
|
Subject: |
[Qemu-devel] [PATCH] Rename target_phys_addr_t to Phys |
|
Date: |
Wed, 4 Jan 2012 21:32:38 +0200 |
The name 'Phys' conveys exactly the same information as 'target_phys_addr_t':
- it has to be a physical address (no such thing as physical data)
- it has to be a target address (qemu doesn't do host physical addresses)
- the fact that it's a type is implied by the naming convention
As it's 4 characters vs. 18, and C standard compliant to boot, Phys is a
clear winner. Rename all instances of target_phys_addr_t to the new name.
All hail Phys!
Signed-off-by: Avi Kivity <address@hidden>
---
HACKING | 2 +-
cpu-all.h | 2 +-
cpu-common.h | 64 +++++++++---------
cpu-defs.h | 2 +-
disas.h | 2 +-
dma-helpers.c | 2 +-
dma.h | 2 +-
exec-all.h | 6 +-
exec-obsolete.h | 4 +-
exec.c | 140 +++++++++++++++++++-------------------
hw/a9mpcore.c | 4 +-
hw/alpha_pci.c | 12 ++--
hw/alpha_typhoon.c | 12 ++--
hw/an5206.c | 2 +-
hw/apb_pci.c | 24 +++---
hw/apb_pci.h | 4 +-
hw/apic.c | 14 ++--
hw/arm-misc.h | 10 ++--
hw/arm11mpcore.c | 8 +-
hw/arm_boot.c | 10 ++--
hw/arm_gic.c | 20 +++---
hw/arm_l2x0.c | 4 +-
hw/arm_mptimer.c | 12 ++--
hw/arm_sysctl.c | 4 +-
hw/arm_timer.c | 12 ++--
hw/armv7m.c | 12 ++--
hw/axis_dev88.c | 8 +-
hw/bonito.c | 38 +++++-----
hw/cirrus_vga.c | 16 ++--
hw/cris-boot.h | 2 +-
hw/cs4231.c | 4 +-
hw/cs4231a.c | 4 +-
hw/cuda.c | 12 ++--
hw/dma.c | 4 +-
hw/dp8393x.c | 18 +++---
hw/ds1225y.c | 4 +-
hw/dummy_m68k.c | 2 +-
hw/e1000.c | 8 +-
hw/eccmemctl.c | 8 +-
hw/eepro100.c | 4 +-
hw/elf_ops.h | 2 +-
hw/empty_slot.c | 6 +-
hw/empty_slot.h | 2 +-
hw/escc.c | 8 +-
hw/escc.h | 4 +-
hw/esp.c | 8 +-
hw/esp.h | 2 +-
hw/etraxfs.h | 2 +-
hw/etraxfs_dma.c | 22 +++---
hw/etraxfs_dma.h | 2 +-
hw/etraxfs_eth.c | 4 +-
hw/etraxfs_pic.c | 4 +-
hw/etraxfs_ser.c | 4 +-
hw/etraxfs_timer.c | 4 +-
hw/fdc.c | 8 +-
hw/fdc.h | 4 +-
hw/flash.h | 8 +-
hw/framebuffer.c | 6 +-
hw/framebuffer.h | 2 +-
hw/fw_cfg.c | 16 ++--
hw/fw_cfg.h | 2 +-
hw/g364fb.c | 4 +-
hw/grlib.h | 6 +-
hw/grlib_apbuart.c | 4 +-
hw/grlib_gptimer.c | 8 +-
hw/grlib_irqmp.c | 4 +-
hw/gt64xxx.c | 20 +++---
hw/heathrow_pic.c | 4 +-
hw/hpet.c | 8 +-
hw/i8259.c | 8 +-
hw/ide.h | 2 +-
hw/ide/ahci.c | 18 +++---
hw/ide/cmd646.c | 12 ++--
hw/ide/macio.c | 12 ++--
hw/ide/mmio.c | 10 ++--
hw/ide/piix.c | 4 +-
hw/ide/via.c | 4 +-
hw/integratorcp.c | 14 ++--
hw/intel-hda.c | 26 ++++----
hw/ioapic.c | 4 +-
hw/isa-bus.c | 2 +-
hw/isa.h | 6 +-
hw/isa_mmio.c | 16 ++--
hw/ivshmem.c | 4 +-
hw/jazz_led.c | 14 ++--
hw/lan9118.c | 4 +-
hw/lance.c | 4 +-
hw/lm32_boards.c | 38 +++++-----
hw/lm32_hwsetup.h | 2 +-
hw/lm32_sys.c | 4 +-
hw/lm32_timer.c | 4 +-
hw/lm32_uart.c | 4 +-
hw/lm4549.c | 4 +-
hw/lm4549.h | 4 +-
hw/loader.c | 30 ++++----
hw/loader.h | 22 +++---
hw/lsi53c895a.c | 12 ++--
hw/m48t59.c | 14 ++--
hw/mac_dbdma.c | 4 +-
hw/mac_dbdma.h | 2 +-
hw/mac_nvram.c | 8 +-
hw/mainstone.c | 2 +-
hw/marvell_88w8618_audio.c | 4 +-
hw/mcf.h | 10 ++--
hw/mcf5206.c | 20 +++---
hw/mcf5208.c | 10 ++--
hw/mcf_fec.c | 6 +-
hw/mcf_intc.c | 6 +-
hw/mcf_uart.c | 6 +-
hw/milkymist-ac97.c | 4 +-
hw/milkymist-hpdmc.c | 4 +-
hw/milkymist-hw.h | 24 +++---
hw/milkymist-memcard.c | 4 +-
hw/milkymist-minimac2.c | 6 +-
hw/milkymist-pfpu.c | 8 +-
hw/milkymist-softusb.c | 4 +-
hw/milkymist-sysctl.c | 4 +-
hw/milkymist-tmu2.c | 8 +-
hw/milkymist-uart.c | 4 +-
hw/milkymist-vgafb.c | 4 +-
hw/milkymist.c | 16 ++--
hw/mips.h | 8 +-
hw/mips_jazz.c | 8 +-
hw/mips_malta.c | 6 +-
hw/mips_r4k.c | 4 +-
hw/mipsnet.c | 4 +-
hw/mpc8544_guts.c | 4 +-
hw/msix.c | 4 +-
hw/mst_fpga.c | 4 +-
hw/multiboot.c | 16 ++--
hw/musicpal.c | 32 +++++-----
hw/ne2000.c | 4 +-
hw/nvram.h | 2 +-
hw/omap.h | 70 ++++++++++----------
hw/omap1.c | 148 ++++++++++++++++++++--------------------
hw/omap2.c | 28 ++++----
hw/omap_dma.c | 24 +++---
hw/omap_dss.c | 36 +++++-----
hw/omap_gpio.c | 16 ++--
hw/omap_gpmc.c | 16 ++--
hw/omap_gptimer.c | 8 +-
hw/omap_i2c.c | 8 +-
hw/omap_intc.c | 8 +-
hw/omap_l4.c | 16 ++--
hw/omap_lcdc.c | 8 +-
hw/omap_mmc.c | 6 +-
hw/omap_sdrc.c | 6 +-
hw/omap_spi.c | 4 +-
hw/omap_sx1.c | 4 +-
hw/omap_synctimer.c | 6 +-
hw/omap_tap.c | 4 +-
hw/omap_uart.c | 10 ++--
hw/onenand.c | 8 +-
hw/opencores_eth.c | 8 +-
hw/openpic.c | 52 +++++++-------
hw/openpic.h | 2 +-
hw/palm.c | 8 +-
hw/parallel.c | 14 ++--
hw/pc.c | 4 +-
hw/pc.h | 18 +++---
hw/pc_piix.c | 2 +-
hw/pci.h | 2 +-
hw/pci_host.c | 8 +-
hw/pcie_host.c | 10 ++--
hw/pcie_host.h | 8 +-
hw/pckbd.c | 8 +-
hw/pcnet-pci.c | 20 +++---
hw/pcnet.c | 34 +++++-----
hw/pcnet.h | 4 +-
hw/petalogix_ml605_mmu.c | 10 ++--
hw/petalogix_s3adsp1800_mmu.c | 10 ++--
hw/pflash_cfi01.c | 48 +++++++-------
hw/pflash_cfi02.c | 40 ++++++------
hw/piix_pci.c | 16 ++--
hw/pl011.c | 4 +-
hw/pl022.c | 4 +-
hw/pl031.c | 4 +-
hw/pl041.c | 6 +-
hw/pl050.c | 4 +-
hw/pl061.c | 4 +-
hw/pl080.c | 4 +-
hw/pl110.c | 4 +-
hw/pl181.c | 4 +-
hw/pl190.c | 4 +-
hw/ppc405.h | 12 ++--
hw/ppc405_boards.c | 28 ++++----
hw/ppc405_uc.c | 64 +++++++++---------
hw/ppc440.c | 4 +-
hw/ppc440_bamboo.c | 10 ++--
hw/ppc4xx.h | 16 ++--
hw/ppc4xx_devs.c | 28 ++++----
hw/ppc4xx_pci.c | 16 ++--
hw/ppc_mac.h | 4 +-
hw/ppc_newworld.c | 8 +-
hw/ppc_oldworld.c | 2 +-
hw/ppc_prep.c | 34 +++++-----
hw/ppce500_mpc8544ds.c | 16 ++--
hw/ppce500_pci.c | 4 +-
hw/ppce500_spin.c | 16 ++--
hw/prep_pci.c | 14 ++--
hw/pxa.h | 24 +++---
hw/pxa2xx.c | 42 ++++++------
hw/pxa2xx_dma.c | 16 ++--
hw/pxa2xx_gpio.c | 6 +-
hw/pxa2xx_keypad.c | 6 +-
hw/pxa2xx_lcd.c | 26 ++++----
hw/pxa2xx_mmci.c | 18 +++---
hw/pxa2xx_pcmcia.c | 14 ++--
hw/pxa2xx_pic.c | 10 ++--
hw/pxa2xx_timer.c | 4 +-
hw/qdev-addr.c | 16 ++--
hw/qdev-addr.h | 4 +-
hw/qxl.c | 4 +-
hw/r2d.c | 6 +-
hw/rc4030.c | 34 +++++-----
hw/realview.c | 4 +-
hw/rtl8139.c | 16 ++--
hw/s390-virtio-bus.c | 2 +-
hw/s390-virtio.c | 4 +-
hw/sbi.c | 4 +-
hw/serial.c | 6 +-
hw/sh.h | 4 +-
hw/sh7750.c | 24 +++---
hw/sh_intc.c | 4 +-
hw/sh_pci.c | 4 +-
hw/sh_serial.c | 6 +-
hw/sh_timer.c | 10 ++--
hw/sharpsl.h | 2 +-
hw/slavio_intctl.c | 8 +-
hw/slavio_misc.c | 32 +++++-----
hw/slavio_timer.c | 4 +-
hw/sm501.c | 18 +++---
hw/smc91c111.c | 12 ++--
hw/soc_dma.c | 8 +-
hw/soc_dma.h | 10 ++--
hw/spapr.c | 14 ++--
hw/spapr.h | 8 +-
hw/spapr_pci.c | 4 +-
hw/spapr_pci.h | 2 +-
hw/spapr_rtas.c | 4 +-
hw/sparc32_dma.c | 8 +-
hw/sparc32_dma.h | 4 +-
hw/spitz.c | 4 +-
hw/stellaris.c | 16 ++--
hw/stellaris_enet.c | 4 +-
hw/strongarm.c | 28 ++++----
hw/sun4c_intctl.c | 4 +-
hw/sun4m.c | 84 ++++++++++++------------
hw/sun4m.h | 6 +-
hw/sun4m_iommu.c | 26 ++++----
hw/sun4u.c | 6 +-
hw/sysbus.c | 20 +++---
hw/sysbus.h | 18 +++---
hw/tc6393xb.c | 16 ++--
hw/tcx.c | 10 ++--
hw/tusb6010.c | 12 ++--
hw/unin_pci.c | 4 +-
hw/usb-ehci.c | 22 +++---
hw/usb-libhw.c | 2 +-
hw/usb-musb.c | 12 ++--
hw/usb-ohci.c | 8 +-
hw/versatile_pci.c | 6 +-
hw/versatilepb.c | 4 +-
hw/vga-isa-mm.c | 20 +++---
hw/vga.c | 10 ++--
hw/vga_int.h | 4 +-
hw/vhost.c | 18 +++---
hw/virtex_ml507.c | 12 ++--
hw/virtio-pci.c | 4 +-
hw/virtio.c | 76 +++++++++++-----------
hw/virtio.h | 28 ++++----
hw/vmware_vga.c | 4 +-
hw/wdt_i6300esb.c | 12 ++--
hw/xen_platform.c | 4 +-
hw/xilinx.h | 10 ++--
hw/xilinx_axidma.c | 10 ++--
hw/xilinx_axienet.c | 4 +-
hw/xilinx_ethlite.c | 4 +-
hw/xilinx_intc.c | 4 +-
hw/xilinx_timer.c | 6 +-
hw/xilinx_uartlite.c | 4 +-
hw/xtensa_lx60.c | 12 ++--
hw/zaurus.c | 6 +-
kvm-all.c | 26 ++++----
kvm-stub.c | 4 +-
kvm.h | 6 +-
memory.c | 64 +++++++++---------
memory.h | 44 ++++++------
monitor.c | 30 ++++----
softmmu_template.h | 12 ++--
target-alpha/cpu.h | 2 +-
target-alpha/helper.c | 2 +-
target-alpha/op_helper.c | 2 +-
target-arm/helper.c | 2 +-
target-cris/helper.c | 2 +-
target-i386/helper.c | 6 +-
target-i386/kvm.c | 6 +-
target-i386/op_helper.c | 6 +-
target-lm32/helper.c | 2 +-
target-m68k/helper.c | 2 +-
target-microblaze/cpu.h | 2 +-
target-microblaze/helper.c | 2 +-
target-microblaze/op_helper.c | 2 +-
target-mips/cpu.h | 12 ++--
target-mips/helper.c | 18 +++---
target-mips/op_helper.c | 6 +-
target-ppc/cpu.h | 24 +++---
target-ppc/helper.c | 46 ++++++------
target-ppc/op_helper.c | 2 +-
target-s390x/cpu.h | 2 +-
target-s390x/helper.c | 8 +-
target-s390x/op_helper.c | 10 ++--
target-sh4/cpu.h | 16 ++--
target-sh4/helper.c | 18 +++---
target-sparc/cpu.h | 4 +-
target-sparc/ldst_helper.c | 40 ++++++------
target-sparc/mmu_helper.c | 38 +++++-----
target-xtensa/helper.c | 2 +-
targphys.h | 8 +-
xen-all.c | 32 +++++-----
xen-mapcache.c | 32 +++++-----
xen-mapcache.h | 6 +-
xtensa-semi.c | 6 +-
323 files changed, 1959 insertions(+), 1959 deletions(-)
diff --git a/HACKING b/HACKING
index 471cf1d..38e3497 100644
--- a/HACKING
+++ b/HACKING
@@ -32,7 +32,7 @@ mandatory for VMState fields.
Don't use Linux kernel internal types like u32, __u32 or __le32.
-Use target_phys_addr_t for guest physical addresses except pcibus_t
+Use Phys for guest physical addresses except pcibus_t
for PCI addresses. In addition, ram_addr_t is a QEMU internal address
space that maps guest RAM physical addresses into an intermediate
address space that can map to host virtual address spaces. Generally
diff --git a/cpu-all.h b/cpu-all.h
index e2c3c49..1940d32 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -465,7 +465,7 @@ int cpu_str_to_log_mask(const char *str);
/* Return the physical page corresponding to a virtual one. Use it
only for debugging because no protection checks are done. Return -1
if no page found. */
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
+Phys cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
/* memory API */
diff --git a/cpu-common.h b/cpu-common.h
index a40c57d..9c248f0 100644
--- a/cpu-common.h
+++ b/cpu-common.h
@@ -35,8 +35,8 @@ typedef unsigned long ram_addr_t;
/* memory API */
-typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr,
uint32_t value);
-typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
+typedef void CPUWriteMemoryFunc(void *opaque, Phys addr, uint32_t value);
+typedef uint32_t CPUReadMemoryFunc(void *opaque, Phys addr);
void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
/* This should only be used for ram local to a device. */
@@ -51,23 +51,23 @@ int qemu_ram_addr_from_host(void *ptr, ram_addr_t
*ram_addr);
ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
-void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
+void cpu_physical_memory_rw(Phys addr, uint8_t *buf,
int len, int is_write);
-static inline void cpu_physical_memory_read(target_phys_addr_t addr,
+static inline void cpu_physical_memory_read(Phys addr,
void *buf, int len)
{
cpu_physical_memory_rw(addr, buf, len, 0);
}
-static inline void cpu_physical_memory_write(target_phys_addr_t addr,
+static inline void cpu_physical_memory_write(Phys addr,
const void *buf, int len)
{
cpu_physical_memory_rw(addr, (void *)buf, len, 1);
}
-void *cpu_physical_memory_map(target_phys_addr_t addr,
- target_phys_addr_t *plen,
+void *cpu_physical_memory_map(Phys addr,
+ Phys *plen,
int is_write);
-void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
- int is_write, target_phys_addr_t access_len);
+void cpu_physical_memory_unmap(void *buffer, Phys len,
+ int is_write, Phys access_len);
void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
void cpu_unregister_map_client(void *cookie);
@@ -78,33 +78,33 @@ void cpu_unregister_map_client(void *cookie);
*/
void qemu_flush_coalesced_mmio_buffer(void);
-uint32_t ldub_phys(target_phys_addr_t addr);
-uint32_t lduw_le_phys(target_phys_addr_t addr);
-uint32_t lduw_be_phys(target_phys_addr_t addr);
-uint32_t ldl_le_phys(target_phys_addr_t addr);
-uint32_t ldl_be_phys(target_phys_addr_t addr);
-uint64_t ldq_le_phys(target_phys_addr_t addr);
-uint64_t ldq_be_phys(target_phys_addr_t addr);
-void stb_phys(target_phys_addr_t addr, uint32_t val);
-void stw_le_phys(target_phys_addr_t addr, uint32_t val);
-void stw_be_phys(target_phys_addr_t addr, uint32_t val);
-void stl_le_phys(target_phys_addr_t addr, uint32_t val);
-void stl_be_phys(target_phys_addr_t addr, uint32_t val);
-void stq_le_phys(target_phys_addr_t addr, uint64_t val);
-void stq_be_phys(target_phys_addr_t addr, uint64_t val);
+uint32_t ldub_phys(Phys addr);
+uint32_t lduw_le_phys(Phys addr);
+uint32_t lduw_be_phys(Phys addr);
+uint32_t ldl_le_phys(Phys addr);
+uint32_t ldl_be_phys(Phys addr);
+uint64_t ldq_le_phys(Phys addr);
+uint64_t ldq_be_phys(Phys addr);
+void stb_phys(Phys addr, uint32_t val);
+void stw_le_phys(Phys addr, uint32_t val);
+void stw_be_phys(Phys addr, uint32_t val);
+void stl_le_phys(Phys addr, uint32_t val);
+void stl_be_phys(Phys addr, uint32_t val);
+void stq_le_phys(Phys addr, uint64_t val);
+void stq_be_phys(Phys addr, uint64_t val);
#ifdef NEED_CPU_H
-uint32_t lduw_phys(target_phys_addr_t addr);
-uint32_t ldl_phys(target_phys_addr_t addr);
-uint64_t ldq_phys(target_phys_addr_t addr);
-void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
-void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
-void stw_phys(target_phys_addr_t addr, uint32_t val);
-void stl_phys(target_phys_addr_t addr, uint32_t val);
-void stq_phys(target_phys_addr_t addr, uint64_t val);
+uint32_t lduw_phys(Phys addr);
+uint32_t ldl_phys(Phys addr);
+uint64_t ldq_phys(Phys addr);
+void stl_phys_notdirty(Phys addr, uint32_t val);
+void stq_phys_notdirty(Phys addr, uint64_t val);
+void stw_phys(Phys addr, uint32_t val);
+void stl_phys(Phys addr, uint32_t val);
+void stq_phys(Phys addr, uint64_t val);
#endif
-void cpu_physical_memory_write_rom(target_phys_addr_t addr,
+void cpu_physical_memory_write_rom(Phys addr,
const uint8_t *buf, int len);
extern struct MemoryRegion io_mem_ram;
diff --git a/cpu-defs.h b/cpu-defs.h
index 57a709b..824d645 100644
--- a/cpu-defs.h
+++ b/cpu-defs.h
@@ -113,7 +113,7 @@ extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1
<< CPU_TLB_ENTRY_BIT
#define CPU_COMMON_TLB \
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
- target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
+ Phys iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
target_ulong tlb_flush_addr; \
target_ulong tlb_flush_mask;
diff --git a/disas.h b/disas.h
index f9287f7..1c11a7d 100644
--- a/disas.h
+++ b/disas.h
@@ -22,7 +22,7 @@ struct elf64_sym;
#if defined(CONFIG_USER_ONLY)
typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_ulong
orig_addr);
#else
-typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_phys_addr_t
orig_addr);
+typedef const char *(*lookup_symbol_t)(struct syminfo *s, Phys orig_addr);
#endif
struct syminfo {
diff --git a/dma-helpers.c b/dma-helpers.c
index f08cdb5..a2fa915 100644
--- a/dma-helpers.c
+++ b/dma-helpers.c
@@ -106,7 +106,7 @@ static void dma_complete(DMAAIOCB *dbs, int ret)
static void dma_bdrv_cb(void *opaque, int ret)
{
DMAAIOCB *dbs = (DMAAIOCB *)opaque;
- target_phys_addr_t cur_addr, cur_len;
+ Phys cur_addr, cur_len;
void *mem;
trace_dma_bdrv_cb(dbs, ret);
diff --git a/dma.h b/dma.h
index a13209d..196b91d 100644
--- a/dma.h
+++ b/dma.h
@@ -18,7 +18,7 @@
typedef struct ScatterGatherEntry ScatterGatherEntry;
#if defined(TARGET_PHYS_ADDR_BITS)
-typedef target_phys_addr_t dma_addr_t;
+typedef Phys dma_addr_t;
#define DMA_ADDR_FMT TARGET_FMT_plx
diff --git a/exec-all.h b/exec-all.h
index 51d01f2..ff5471e 100644
--- a/exec-all.h
+++ b/exec-all.h
@@ -100,7 +100,7 @@ void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
#if !defined(CONFIG_USER_ONLY)
void tlb_set_page(CPUState *env, target_ulong vaddr,
- target_phys_addr_t paddr, int prot,
+ Phys paddr, int prot,
int mmu_idx, target_ulong size);
#endif
@@ -299,8 +299,8 @@ extern void *tci_tb_ptr;
#if !defined(CONFIG_USER_ONLY)
-uint64_t io_mem_read(int index, target_phys_addr_t addr, unsigned size);
-void io_mem_write(int index, target_phys_addr_t addr, uint64_t value,
+uint64_t io_mem_read(int index, Phys addr, unsigned size);
+void io_mem_write(int index, Phys addr, uint64_t value,
unsigned size);
extern struct MemoryRegion *io_mem_region[IO_MEM_NB_ENTRIES];
diff --git a/exec-obsolete.h b/exec-obsolete.h
index f8af27e..7fb475b 100644
--- a/exec-obsolete.h
+++ b/exec-obsolete.h
@@ -39,8 +39,8 @@ struct MemoryRegionSection;
void cpu_register_physical_memory_log(struct MemoryRegionSection *section,
bool readable, bool readonly);
-void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
-void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
+void qemu_register_coalesced_mmio(Phys addr, ram_addr_t size);
+void qemu_unregister_coalesced_mmio(Phys addr, ram_addr_t size);
int cpu_physical_memory_set_dirty_tracking(int enable);
diff --git a/exec.c b/exec.c
index b1d6602..fb1e56a 100644
--- a/exec.c
+++ b/exec.c
@@ -179,7 +179,7 @@
#define V_L1_BITS V_L1_BITS_REM
#endif
-#define P_L1_SIZE ((target_phys_addr_t)1 << P_L1_BITS)
+#define P_L1_SIZE ((Phys)1 << P_L1_BITS)
#define V_L1_SIZE ((target_ulong)1 << V_L1_BITS)
#define P_L1_SHIFT (TARGET_PHYS_ADDR_SPACE_BITS - TARGET_PAGE_BITS - P_L1_BITS)
@@ -398,7 +398,7 @@ static void page_init(void)
}
#if !defined(CONFIG_USER_ONLY)
-static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
+static PhysPageDesc *phys_page_find_alloc(Phys index, int alloc)
{
PhysPageDesc *pd;
void **lp;
@@ -439,7 +439,7 @@ static void page_init(void)
return pd + (index & (L2_SIZE - 1));
}
-static inline PhysPageDesc phys_page_find(target_phys_addr_t index)
+static inline PhysPageDesc phys_page_find(Phys index)
{
PhysPageDesc *p = phys_page_find_alloc(index, 0);
@@ -1409,7 +1409,7 @@ static void breakpoint_invalidate(CPUState *env,
target_ulong pc)
#else
static void breakpoint_invalidate(CPUState *env, target_ulong pc)
{
- target_phys_addr_t addr;
+ Phys addr;
target_ulong pd;
ram_addr_t ram_addr;
PhysPageDesc p;
@@ -2109,7 +2109,7 @@ static bool is_ram_rom_romd(ram_addr_t pd)
is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
supplied size is only used by tlb_flush_page. */
void tlb_set_page(CPUState *env, target_ulong vaddr,
- target_phys_addr_t paddr, int prot,
+ Phys paddr, int prot,
int mmu_idx, target_ulong size)
{
PhysPageDesc p;
@@ -2120,7 +2120,7 @@ void tlb_set_page(CPUState *env, target_ulong vaddr,
unsigned long addend;
CPUTLBEntry *te;
CPUWatchpoint *wp;
- target_phys_addr_t iotlb;
+ Phys iotlb;
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
@@ -2480,14 +2480,14 @@ static inline void tlb_set_dirty(CPUState *env,
#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
typedef struct subpage_t {
MemoryRegion iomem;
- target_phys_addr_t base;
+ Phys base;
ram_addr_t sub_io_index[TARGET_PAGE_SIZE];
ram_addr_t region_offset[TARGET_PAGE_SIZE];
} subpage_t;
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
ram_addr_t memory, ram_addr_t region_offset);
-static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
+static subpage_t *subpage_init (Phys base, ram_addr_t *phys,
ram_addr_t orig_memory,
ram_addr_t region_offset);
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
@@ -2521,11 +2521,11 @@ static int subpage_register (subpage_t *mmio, uint32_t
start, uint32_t end,
void cpu_register_physical_memory_log(MemoryRegionSection *section,
bool readable, bool readonly)
{
- target_phys_addr_t start_addr = section->offset_within_address_space;
+ Phys start_addr = section->offset_within_address_space;
ram_addr_t size = section->size;
ram_addr_t phys_offset = section->mr->ram_addr;
ram_addr_t region_offset = section->offset_within_region;
- target_phys_addr_t addr, end_addr;
+ Phys addr, end_addr;
PhysPageDesc *p;
CPUState *env;
ram_addr_t orig_size = size;
@@ -2547,14 +2547,14 @@ void
cpu_register_physical_memory_log(MemoryRegionSection *section,
}
region_offset &= TARGET_PAGE_MASK;
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
- end_addr = start_addr + (target_phys_addr_t)size;
+ end_addr = start_addr + (Phys)size;
addr = start_addr;
do {
p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 0);
if (p && p->phys_offset != io_mem_unassigned.ram_addr) {
ram_addr_t orig_memory = p->phys_offset;
- target_phys_addr_t start_addr2, end_addr2;
+ Phys start_addr2, end_addr2;
int need_subpage = 0;
MemoryRegion *mr = io_mem_region[orig_memory & ~TARGET_PAGE_MASK];
@@ -2584,7 +2584,7 @@ void cpu_register_physical_memory_log(MemoryRegionSection
*section,
if (is_ram_rom_romd(phys_offset)) {
phys_offset += TARGET_PAGE_SIZE;
} else {
- target_phys_addr_t start_addr2, end_addr2;
+ Phys start_addr2, end_addr2;
int need_subpage = 0;
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
@@ -2613,13 +2613,13 @@ void
cpu_register_physical_memory_log(MemoryRegionSection *section,
}
}
-void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
+void qemu_register_coalesced_mmio(Phys addr, ram_addr_t size)
{
if (kvm_enabled())
kvm_coalesce_mmio_region(addr, size);
}
-void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
+void qemu_unregister_coalesced_mmio(Phys addr, ram_addr_t size)
{
if (kvm_enabled())
kvm_uncoalesce_mmio_region(addr, size);
@@ -3123,7 +3123,7 @@ ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
return ram_addr;
}
-static uint64_t unassigned_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t unassigned_mem_read(void *opaque, Phys addr,
unsigned size)
{
#ifdef DEBUG_UNASSIGNED
@@ -3135,7 +3135,7 @@ static uint64_t unassigned_mem_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void unassigned_mem_write(void *opaque, target_phys_addr_t addr,
+static void unassigned_mem_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
#ifdef DEBUG_UNASSIGNED
@@ -3152,13 +3152,13 @@ static void unassigned_mem_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t error_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t error_mem_read(void *opaque, Phys addr,
unsigned size)
{
abort();
}
-static void error_mem_write(void *opaque, target_phys_addr_t addr,
+static void error_mem_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
abort();
@@ -3176,7 +3176,7 @@ static void error_mem_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void notdirty_mem_write(void *opaque, target_phys_addr_t ram_addr,
+static void notdirty_mem_write(void *opaque, Phys ram_addr,
uint64_t val, unsigned size)
{
int dirty_flags;
@@ -3262,7 +3262,7 @@ static void check_watchpoint(int offset, int len_mask,
int flags)
/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
so these check for a hit then pass through to the normal out-of-line
phys routines. */
-static uint64_t watch_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t watch_mem_read(void *opaque, Phys addr,
unsigned size)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_READ);
@@ -3274,7 +3274,7 @@ static uint64_t watch_mem_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void watch_mem_write(void *opaque, target_phys_addr_t addr,
+static void watch_mem_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~(size - 1), BP_MEM_WRITE);
@@ -3292,7 +3292,7 @@ static void watch_mem_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t subpage_read(void *opaque, target_phys_addr_t addr,
+static uint64_t subpage_read(void *opaque, Phys addr,
unsigned len)
{
subpage_t *mmio = opaque;
@@ -3307,7 +3307,7 @@ static uint64_t subpage_read(void *opaque,
target_phys_addr_t addr,
return io_mem_read(idx, addr, len);
}
-static void subpage_write(void *opaque, target_phys_addr_t addr,
+static void subpage_write(void *opaque, Phys addr,
uint64_t value, unsigned len)
{
subpage_t *mmio = opaque;
@@ -3329,7 +3329,7 @@ static void subpage_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t subpage_ram_read(void *opaque, target_phys_addr_t addr,
+static uint64_t subpage_ram_read(void *opaque, Phys addr,
unsigned size)
{
ram_addr_t raddr = addr;
@@ -3342,7 +3342,7 @@ static uint64_t subpage_ram_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void subpage_ram_write(void *opaque, target_phys_addr_t addr,
+static void subpage_ram_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
ram_addr_t raddr = addr;
@@ -3386,7 +3386,7 @@ static int subpage_register (subpage_t *mmio, uint32_t
start, uint32_t end,
return 0;
}
-static subpage_t *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
+static subpage_t *subpage_init (Phys base, ram_addr_t *phys,
ram_addr_t orig_memory,
ram_addr_t region_offset)
{
@@ -3543,13 +3543,13 @@ int cpu_memory_rw_debug(CPUState *env, target_ulong
addr,
}
#else
-void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
+void cpu_physical_memory_rw(Phys addr, uint8_t *buf,
int len, int is_write)
{
int l, io_index;
uint8_t *ptr;
uint32_t val;
- target_phys_addr_t page;
+ Phys page;
ram_addr_t pd;
PhysPageDesc p;
@@ -3563,7 +3563,7 @@ void cpu_physical_memory_rw(target_phys_addr_t addr,
uint8_t *buf,
if (is_write) {
if ((pd & ~TARGET_PAGE_MASK) != io_mem_ram.ram_addr) {
- target_phys_addr_t addr1;
+ Phys addr1;
io_index = pd & (IO_MEM_NB_ENTRIES - 1);
addr1 = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
/* XXX: could force cpu_single_env to NULL to avoid
@@ -3601,7 +3601,7 @@ void cpu_physical_memory_rw(target_phys_addr_t addr,
uint8_t *buf,
}
} else {
if (!is_ram_rom_romd(pd)) {
- target_phys_addr_t addr1;
+ Phys addr1;
/* I/O case */
io_index = pd & (IO_MEM_NB_ENTRIES - 1);
addr1 = (addr & ~TARGET_PAGE_MASK) + p.region_offset;
@@ -3635,12 +3635,12 @@ void cpu_physical_memory_rw(target_phys_addr_t addr,
uint8_t *buf,
}
/* used for ROM loading : can write in RAM and ROM */
-void cpu_physical_memory_write_rom(target_phys_addr_t addr,
+void cpu_physical_memory_write_rom(Phys addr,
const uint8_t *buf, int len)
{
int l;
uint8_t *ptr;
- target_phys_addr_t page;
+ Phys page;
unsigned long pd;
PhysPageDesc p;
@@ -3670,8 +3670,8 @@ void cpu_physical_memory_write_rom(target_phys_addr_t
addr,
typedef struct {
void *buffer;
- target_phys_addr_t addr;
- target_phys_addr_t len;
+ Phys addr;
+ Phys len;
} BounceBuffer;
static BounceBuffer bounce;
@@ -3721,14 +3721,14 @@ static void cpu_notify_map_clients(void)
* Use cpu_register_map_client() to know when retrying the map operation is
* likely to succeed.
*/
-void *cpu_physical_memory_map(target_phys_addr_t addr,
- target_phys_addr_t *plen,
+void *cpu_physical_memory_map(Phys addr,
+ Phys *plen,
int is_write)
{
- target_phys_addr_t len = *plen;
- target_phys_addr_t todo = 0;
+ Phys len = *plen;
+ Phys todo = 0;
int l;
- target_phys_addr_t page;
+ Phys page;
unsigned long pd;
PhysPageDesc p;
ram_addr_t raddr = RAM_ADDR_MAX;
@@ -3775,8 +3775,8 @@ static void cpu_notify_map_clients(void)
* Will also mark the memory as dirty if is_write == 1. access_len gives
* the amount of memory that was actually read or written by the caller.
*/
-void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
- int is_write, target_phys_addr_t access_len)
+void cpu_physical_memory_unmap(void *buffer, Phys len,
+ int is_write, Phys access_len)
{
if (buffer != bounce.buffer) {
if (is_write) {
@@ -3811,7 +3811,7 @@ void cpu_physical_memory_unmap(void *buffer,
target_phys_addr_t len,
}
/* warning: addr must be aligned */
-static inline uint32_t ldl_phys_internal(target_phys_addr_t addr,
+static inline uint32_t ldl_phys_internal(Phys addr,
enum device_endian endian)
{
int io_index;
@@ -3856,23 +3856,23 @@ static inline uint32_t
ldl_phys_internal(target_phys_addr_t addr,
return val;
}
-uint32_t ldl_phys(target_phys_addr_t addr)
+uint32_t ldl_phys(Phys addr)
{
return ldl_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t ldl_le_phys(target_phys_addr_t addr)
+uint32_t ldl_le_phys(Phys addr)
{
return ldl_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t ldl_be_phys(target_phys_addr_t addr)
+uint32_t ldl_be_phys(Phys addr)
{
return ldl_phys_internal(addr, DEVICE_BIG_ENDIAN);
}
/* warning: addr must be aligned */
-static inline uint64_t ldq_phys_internal(target_phys_addr_t addr,
+static inline uint64_t ldq_phys_internal(Phys addr,
enum device_endian endian)
{
int io_index;
@@ -3917,23 +3917,23 @@ static inline uint64_t
ldq_phys_internal(target_phys_addr_t addr,
return val;
}
-uint64_t ldq_phys(target_phys_addr_t addr)
+uint64_t ldq_phys(Phys addr)
{
return ldq_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
}
-uint64_t ldq_le_phys(target_phys_addr_t addr)
+uint64_t ldq_le_phys(Phys addr)
{
return ldq_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
}
-uint64_t ldq_be_phys(target_phys_addr_t addr)
+uint64_t ldq_be_phys(Phys addr)
{
return ldq_phys_internal(addr, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-uint32_t ldub_phys(target_phys_addr_t addr)
+uint32_t ldub_phys(Phys addr)
{
uint8_t val;
cpu_physical_memory_read(addr, &val, 1);
@@ -3941,7 +3941,7 @@ uint32_t ldub_phys(target_phys_addr_t addr)
}
/* warning: addr must be aligned */
-static inline uint32_t lduw_phys_internal(target_phys_addr_t addr,
+static inline uint32_t lduw_phys_internal(Phys addr,
enum device_endian endian)
{
int io_index;
@@ -3986,17 +3986,17 @@ static inline uint32_t
lduw_phys_internal(target_phys_addr_t addr,
return val;
}
-uint32_t lduw_phys(target_phys_addr_t addr)
+uint32_t lduw_phys(Phys addr)
{
return lduw_phys_internal(addr, DEVICE_NATIVE_ENDIAN);
}
-uint32_t lduw_le_phys(target_phys_addr_t addr)
+uint32_t lduw_le_phys(Phys addr)
{
return lduw_phys_internal(addr, DEVICE_LITTLE_ENDIAN);
}
-uint32_t lduw_be_phys(target_phys_addr_t addr)
+uint32_t lduw_be_phys(Phys addr)
{
return lduw_phys_internal(addr, DEVICE_BIG_ENDIAN);
}
@@ -4004,7 +4004,7 @@ uint32_t lduw_be_phys(target_phys_addr_t addr)
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
-void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
+void stl_phys_notdirty(Phys addr, uint32_t val)
{
int io_index;
uint8_t *ptr;
@@ -4035,7 +4035,7 @@ void stl_phys_notdirty(target_phys_addr_t addr, uint32_t
val)
}
}
-void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
+void stq_phys_notdirty(Phys addr, uint64_t val)
{
int io_index;
uint8_t *ptr;
@@ -4063,7 +4063,7 @@ void stq_phys_notdirty(target_phys_addr_t addr, uint64_t
val)
}
/* warning: addr must be aligned */
-static inline void stl_phys_internal(target_phys_addr_t addr, uint32_t val,
+static inline void stl_phys_internal(Phys addr, uint32_t val,
enum device_endian endian)
{
int io_index;
@@ -4113,30 +4113,30 @@ static inline void stl_phys_internal(target_phys_addr_t
addr, uint32_t val,
}
}
-void stl_phys(target_phys_addr_t addr, uint32_t val)
+void stl_phys(Phys addr, uint32_t val)
{
stl_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stl_le_phys(target_phys_addr_t addr, uint32_t val)
+void stl_le_phys(Phys addr, uint32_t val)
{
stl_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stl_be_phys(target_phys_addr_t addr, uint32_t val)
+void stl_be_phys(Phys addr, uint32_t val)
{
stl_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-void stb_phys(target_phys_addr_t addr, uint32_t val)
+void stb_phys(Phys addr, uint32_t val)
{
uint8_t v = val;
cpu_physical_memory_write(addr, &v, 1);
}
/* warning: addr must be aligned */
-static inline void stw_phys_internal(target_phys_addr_t addr, uint32_t val,
+static inline void stw_phys_internal(Phys addr, uint32_t val,
enum device_endian endian)
{
int io_index;
@@ -4186,35 +4186,35 @@ static inline void stw_phys_internal(target_phys_addr_t
addr, uint32_t val,
}
}
-void stw_phys(target_phys_addr_t addr, uint32_t val)
+void stw_phys(Phys addr, uint32_t val)
{
stw_phys_internal(addr, val, DEVICE_NATIVE_ENDIAN);
}
-void stw_le_phys(target_phys_addr_t addr, uint32_t val)
+void stw_le_phys(Phys addr, uint32_t val)
{
stw_phys_internal(addr, val, DEVICE_LITTLE_ENDIAN);
}
-void stw_be_phys(target_phys_addr_t addr, uint32_t val)
+void stw_be_phys(Phys addr, uint32_t val)
{
stw_phys_internal(addr, val, DEVICE_BIG_ENDIAN);
}
/* XXX: optimize */
-void stq_phys(target_phys_addr_t addr, uint64_t val)
+void stq_phys(Phys addr, uint64_t val)
{
val = tswap64(val);
cpu_physical_memory_write(addr, &val, 8);
}
-void stq_le_phys(target_phys_addr_t addr, uint64_t val)
+void stq_le_phys(Phys addr, uint64_t val)
{
val = cpu_to_le64(val);
cpu_physical_memory_write(addr, &val, 8);
}
-void stq_be_phys(target_phys_addr_t addr, uint64_t val)
+void stq_be_phys(Phys addr, uint64_t val)
{
val = cpu_to_be64(val);
cpu_physical_memory_write(addr, &val, 8);
@@ -4225,7 +4225,7 @@ int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
uint8_t *buf, int len, int is_write)
{
int l;
- target_phys_addr_t phys_addr;
+ Phys phys_addr;
target_ulong page;
while (len > 0) {
diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
index 3ef0e13..4693ee6 100644
--- a/hw/a9mpcore.c
+++ b/hw/a9mpcore.c
@@ -39,7 +39,7 @@
DeviceState *mptimer;
} a9mp_priv_state;
-static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset,
+static uint64_t a9_scu_read(void *opaque, Phys offset,
unsigned size)
{
a9mp_priv_state *s = (a9mp_priv_state *)opaque;
@@ -70,7 +70,7 @@ static uint64_t a9_scu_read(void *opaque, target_phys_addr_t
offset,
}
}
-static void a9_scu_write(void *opaque, target_phys_addr_t offset,
+static void a9_scu_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
a9mp_priv_state *s = (a9mp_priv_state *)opaque;
diff --git a/hw/alpha_pci.c b/hw/alpha_pci.c
index e975702..51a745a 100644
--- a/hw/alpha_pci.c
+++ b/hw/alpha_pci.c
@@ -16,7 +16,7 @@
/* PCI IO reads/writes, to byte-word addressable memory. */
/* ??? Doesn't handle multiple PCI busses. */
-static uint64_t bw_io_read(void *opaque, target_phys_addr_t addr, unsigned
size)
+static uint64_t bw_io_read(void *opaque, Phys addr, unsigned size)
{
switch (size) {
case 1:
@@ -29,7 +29,7 @@ static uint64_t bw_io_read(void *opaque, target_phys_addr_t
addr, unsigned size)
abort();
}
-static void bw_io_write(void *opaque, target_phys_addr_t addr,
+static void bw_io_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
switch (size) {
@@ -58,14 +58,14 @@ static void bw_io_write(void *opaque, target_phys_addr_t
addr,
};
/* PCI config space reads/writes, to byte-word addressable memory. */
-static uint64_t bw_conf1_read(void *opaque, target_phys_addr_t addr,
+static uint64_t bw_conf1_read(void *opaque, Phys addr,
unsigned size)
{
PCIBus *b = opaque;
return pci_data_read(b, addr, size);
}
-static void bw_conf1_write(void *opaque, target_phys_addr_t addr,
+static void bw_conf1_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
PCIBus *b = opaque;
@@ -84,12 +84,12 @@ static void bw_conf1_write(void *opaque, target_phys_addr_t
addr,
/* PCI/EISA Interrupt Acknowledge Cycle. */
-static uint64_t iack_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t iack_read(void *opaque, Phys addr, unsigned size)
{
return pic_read_irq(isa_pic);
}
-static void special_write(void *opaque, target_phys_addr_t addr,
+static void special_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
qemu_log("pci: special write cycle");
diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c
index 7d924a3..1b0beef 100644
--- a/hw/alpha_typhoon.c
+++ b/hw/alpha_typhoon.c
@@ -64,7 +64,7 @@ static void cpu_irq_change(CPUState *env, uint64_t req)
}
}
-static uint64_t cchip_read(void *opaque, target_phys_addr_t addr, unsigned
size)
+static uint64_t cchip_read(void *opaque, Phys addr, unsigned size)
{
CPUState *env = cpu_single_env;
TyphoonState *s = opaque;
@@ -197,13 +197,13 @@ static uint64_t cchip_read(void *opaque,
target_phys_addr_t addr, unsigned size)
return ret;
}
-static uint64_t dchip_read(void *opaque, target_phys_addr_t addr, unsigned
size)
+static uint64_t dchip_read(void *opaque, Phys addr, unsigned size)
{
/* Skip this. It's all related to DRAM timing and setup. */
return 0;
}
-static uint64_t pchip_read(void *opaque, target_phys_addr_t addr, unsigned
size)
+static uint64_t pchip_read(void *opaque, Phys addr, unsigned size)
{
TyphoonState *s = opaque;
uint64_t ret = 0;
@@ -300,7 +300,7 @@ static uint64_t pchip_read(void *opaque, target_phys_addr_t
addr, unsigned size)
return ret;
}
-static void cchip_write(void *opaque, target_phys_addr_t addr,
+static void cchip_write(void *opaque, Phys addr,
uint64_t v32, unsigned size)
{
TyphoonState *s = opaque;
@@ -457,13 +457,13 @@ static void cchip_write(void *opaque, target_phys_addr_t
addr,
}
}
-static void dchip_write(void *opaque, target_phys_addr_t addr,
+static void dchip_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
/* Skip this. It's all related to DRAM timing and setup. */
}
-static void pchip_write(void *opaque, target_phys_addr_t addr,
+static void pchip_write(void *opaque, Phys addr,
uint64_t v32, unsigned size)
{
TyphoonState *s = opaque;
diff --git a/hw/an5206.c b/hw/an5206.c
index d57306d..47ca81e 100644
--- a/hw/an5206.c
+++ b/hw/an5206.c
@@ -27,7 +27,7 @@ static void an5206_init(ram_addr_t ram_size,
CPUState *env;
int kernel_size;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ Phys entry;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 3a1b111..44c100a 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -82,7 +82,7 @@
unsigned int nr_resets;
} APBState;
-static void apb_config_writel (void *opaque, target_phys_addr_t addr,
+static void apb_config_writel (void *opaque, Phys addr,
uint64_t val, unsigned size)
{
APBState *s = opaque;
@@ -131,7 +131,7 @@ static void apb_config_writel (void *opaque,
target_phys_addr_t addr,
}
static uint64_t apb_config_readl (void *opaque,
- target_phys_addr_t addr, unsigned size)
+ Phys addr, unsigned size)
{
APBState *s = opaque;
uint32_t val;
@@ -184,7 +184,7 @@ static uint64_t apb_config_readl (void *opaque,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
+static void apb_pci_config_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
APBState *s = opaque;
@@ -194,7 +194,7 @@ static void apb_pci_config_write(void *opaque,
target_phys_addr_t addr,
pci_data_write(s->bus, addr, val, size);
}
-static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
+static uint64_t apb_pci_config_read(void *opaque, Phys addr,
unsigned size)
{
uint32_t ret;
@@ -206,25 +206,25 @@ static uint64_t apb_pci_config_read(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
+static void pci_apb_iowriteb (void *opaque, Phys addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
-static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
+static void pci_apb_iowritew (void *opaque, Phys addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, bswap16(val));
}
-static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
+static void pci_apb_iowritel (void *opaque, Phys addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, bswap32(val));
}
-static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
+static uint32_t pci_apb_ioreadb (void *opaque, Phys addr)
{
uint32_t val;
@@ -232,7 +232,7 @@ static uint32_t pci_apb_ioreadb (void *opaque,
target_phys_addr_t addr)
return val;
}
-static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
+static uint32_t pci_apb_ioreadw (void *opaque, Phys addr)
{
uint32_t val;
@@ -240,7 +240,7 @@ static uint32_t pci_apb_ioreadw (void *opaque,
target_phys_addr_t addr)
return val;
}
-static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
+static uint32_t pci_apb_ioreadl (void *opaque, Phys addr)
{
uint32_t val;
@@ -314,8 +314,8 @@ static int apb_pci_bridge_initfn(PCIDevice *dev)
return 0;
}
-PCIBus *pci_apb_init(target_phys_addr_t special_base,
- target_phys_addr_t mem_base,
+PCIBus *pci_apb_init(Phys special_base,
+ Phys mem_base,
qemu_irq *pic, PCIBus **bus2, PCIBus **bus3)
{
DeviceState *dev;
diff --git a/hw/apb_pci.h b/hw/apb_pci.h
index 8869f9d..102aea3 100644
--- a/hw/apb_pci.h
+++ b/hw/apb_pci.h
@@ -3,7 +3,7 @@
#include "qemu-common.h"
-PCIBus *pci_apb_init(target_phys_addr_t special_base,
- target_phys_addr_t mem_base,
+PCIBus *pci_apb_init(Phys special_base,
+ Phys mem_base,
qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
#endif
diff --git a/hw/apic.c b/hw/apic.c
index 9d0f460..74b0ca7 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -689,25 +689,25 @@ static void apic_timer(void *opaque)
apic_timer_update(s, s->next_time);
}
-static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t apic_mem_readb(void *opaque, Phys addr)
{
return 0;
}
-static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t apic_mem_readw(void *opaque, Phys addr)
{
return 0;
}
-static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void apic_mem_writeb(void *opaque, Phys addr, uint32_t val)
{
}
-static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void apic_mem_writew(void *opaque, Phys addr, uint32_t val)
{
}
-static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t apic_mem_readl(void *opaque, Phys addr)
{
DeviceState *d;
APICState *s;
@@ -787,7 +787,7 @@ static uint32_t apic_mem_readl(void *opaque,
target_phys_addr_t addr)
return val;
}
-static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
+static void apic_send_msi(Phys addr, uint32_t data)
{
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
@@ -798,7 +798,7 @@ static void apic_send_msi(target_phys_addr_t addr, uint32_t
data)
apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
}
-static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void apic_mem_writel(void *opaque, Phys addr, uint32_t val)
{
DeviceState *d;
APICState *s;
diff --git a/hw/arm-misc.h b/hw/arm-misc.h
index af403a1..94e0314 100644
--- a/hw/arm-misc.h
+++ b/hw/arm-misc.h
@@ -29,16 +29,16 @@ struct arm_boot_info {
const char *kernel_filename;
const char *kernel_cmdline;
const char *initrd_filename;
- target_phys_addr_t loader_start;
- target_phys_addr_t smp_loader_start;
- target_phys_addr_t smp_priv_base;
+ Phys loader_start;
+ Phys smp_loader_start;
+ Phys smp_priv_base;
int nb_cpus;
int board_id;
int (*atag_board)(const struct arm_boot_info *info, void *p);
/* Used internally by arm_boot.c */
int is_linux;
- target_phys_addr_t initrd_size;
- target_phys_addr_t entry;
+ Phys initrd_size;
+ Phys entry;
};
void arm_load_kernel(CPUState *env, struct arm_boot_info *info);
diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c
index bc0457e..c08181a 100644
--- a/hw/arm11mpcore.c
+++ b/hw/arm11mpcore.c
@@ -41,7 +41,7 @@
/* Per-CPU private memory mapped IO. */
-static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mpcore_scu_read(void *opaque, Phys offset,
unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
@@ -63,7 +63,7 @@ static uint64_t mpcore_scu_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
+static void mpcore_scu_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
@@ -107,7 +107,7 @@ static void mpcore_priv_map_setup(mpcore_priv_state *s)
* at 0x200, 0x300...
*/
for (i = 0; i < (s->num_cpu + 1); i++) {
- target_phys_addr_t offset = 0x100 + (i * 0x100);
+ Phys offset = 0x100 + (i * 0x100);
memory_region_add_subregion(&s->container, offset,
&s->gic.cpuiomem[i]);
}
/* Add the regions for timer and watchdog for "current CPU" and
@@ -117,7 +117,7 @@ static void mpcore_priv_map_setup(mpcore_priv_state *s)
s, (s->num_cpu + 1) * 2);
for (i = 0; i < (s->num_cpu + 1) * 2; i++) {
/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
- target_phys_addr_t offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
+ Phys offset = 0x600 + (i >> 1) * 0x100 + (i & 1) * 0x20;
memory_region_add_subregion(&s->container, offset,
sysbus_mmio_get_region(busdev, i));
}
diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index 215d5de..f2be28a 100644
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -50,9 +50,9 @@
} while (0)
static void set_kernel_args(const struct arm_boot_info *info,
- int initrd_size, target_phys_addr_t base)
+ int initrd_size, Phys base)
{
- target_phys_addr_t p;
+ Phys p;
p = base + KERNEL_ARGS_ADDR;
/* ATAG_CORE */
@@ -103,9 +103,9 @@ static void set_kernel_args(const struct arm_boot_info
*info,
}
static void set_kernel_args_old(const struct arm_boot_info *info,
- int initrd_size, target_phys_addr_t base)
+ int initrd_size, Phys base)
{
- target_phys_addr_t p;
+ Phys p;
const char *s;
@@ -210,7 +210,7 @@ void arm_load_kernel(CPUState *env, struct arm_boot_info
*info)
int n;
int is_linux = 0;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ Phys entry;
int big_endian;
/* Load the kernel. */
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 0339cf5..bd807e5 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -262,7 +262,7 @@ static void gic_complete_irq(gic_state * s, int cpu, int
irq)
}
}
-static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t gic_dist_readb(void *opaque, Phys offset)
{
gic_state *s = (gic_state *)opaque;
uint32_t res;
@@ -376,7 +376,7 @@ static uint32_t gic_dist_readb(void *opaque,
target_phys_addr_t offset)
return 0;
}
-static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t gic_dist_readw(void *opaque, Phys offset)
{
uint32_t val;
val = gic_dist_readb(opaque, offset);
@@ -384,7 +384,7 @@ static uint32_t gic_dist_readw(void *opaque,
target_phys_addr_t offset)
return val;
}
-static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t gic_dist_readl(void *opaque, Phys offset)
{
uint32_t val;
#ifdef NVIC
@@ -399,7 +399,7 @@ static uint32_t gic_dist_readl(void *opaque,
target_phys_addr_t offset)
return val;
}
-static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
+static void gic_dist_writeb(void *opaque, Phys offset,
uint32_t value)
{
gic_state *s = (gic_state *)opaque;
@@ -545,14 +545,14 @@ static void gic_dist_writeb(void *opaque,
target_phys_addr_t offset,
hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
}
-static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
+static void gic_dist_writew(void *opaque, Phys offset,
uint32_t value)
{
gic_dist_writeb(opaque, offset, value & 0xff);
gic_dist_writeb(opaque, offset + 1, value >> 8);
}
-static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
+static void gic_dist_writel(void *opaque, Phys offset,
uint32_t value)
{
gic_state *s = (gic_state *)opaque;
@@ -648,14 +648,14 @@ static void gic_cpu_write(gic_state *s, int cpu, int
offset, uint32_t value)
}
/* Wrappers to read/write the GIC CPU interface for the current CPU */
-static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
+static uint64_t gic_thiscpu_read(void *opaque, Phys addr,
unsigned size)
{
gic_state *s = (gic_state *)opaque;
return gic_cpu_read(s, gic_get_current_cpu(), addr & 0xff);
}
-static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
+static void gic_thiscpu_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
gic_state *s = (gic_state *)opaque;
@@ -665,7 +665,7 @@ static void gic_thiscpu_write(void *opaque,
target_phys_addr_t addr,
/* Wrappers to read/write the GIC CPU interface for a specific CPU.
* These just decode the opaque pointer into gic_state* + cpu id.
*/
-static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
+static uint64_t gic_do_cpu_read(void *opaque, Phys addr,
unsigned size)
{
gic_state **backref = (gic_state **)opaque;
@@ -674,7 +674,7 @@ static uint64_t gic_do_cpu_read(void *opaque,
target_phys_addr_t addr,
return gic_cpu_read(s, id, addr & 0xff);
}
-static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
+static void gic_do_cpu_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
gic_state **backref = (gic_state **)opaque;
diff --git a/hw/arm_l2x0.c b/hw/arm_l2x0.c
index 2faed39..f4a0b1d 100644
--- a/hw/arm_l2x0.c
+++ b/hw/arm_l2x0.c
@@ -51,7 +51,7 @@
};
-static uint64_t l2x0_priv_read(void *opaque, target_phys_addr_t offset,
+static uint64_t l2x0_priv_read(void *opaque, Phys offset,
unsigned size)
{
uint32_t cache_data;
@@ -93,7 +93,7 @@ static uint64_t l2x0_priv_read(void *opaque,
target_phys_addr_t offset,
return 0;
}
-static void l2x0_priv_write(void *opaque, target_phys_addr_t offset,
+static void l2x0_priv_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
l2x0_state *s = (l2x0_state *)opaque;
diff --git a/hw/arm_mptimer.c b/hw/arm_mptimer.c
index 455a0aa..ee23aa7 100644
--- a/hw/arm_mptimer.c
+++ b/hw/arm_mptimer.c
@@ -92,7 +92,7 @@ static void timerblock_tick(void *opaque)
timerblock_update_irq(tb);
}
-static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr,
+static uint64_t timerblock_read(void *opaque, Phys addr,
unsigned size)
{
timerblock *tb = (timerblock *)opaque;
@@ -121,7 +121,7 @@ static uint64_t timerblock_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void timerblock_write(void *opaque, target_phys_addr_t addr,
+static void timerblock_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
timerblock *tb = (timerblock *)opaque;
@@ -161,7 +161,7 @@ static void timerblock_write(void *opaque,
target_phys_addr_t addr,
/* Wrapper functions to implement the "read timer/watchdog for
* the current CPU" memory regions.
*/
-static uint64_t arm_thistimer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t arm_thistimer_read(void *opaque, Phys addr,
unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
@@ -169,7 +169,7 @@ static uint64_t arm_thistimer_read(void *opaque,
target_phys_addr_t addr,
return timerblock_read(&s->timerblock[id * 2], addr, size);
}
-static void arm_thistimer_write(void *opaque, target_phys_addr_t addr,
+static void arm_thistimer_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
@@ -177,7 +177,7 @@ static void arm_thistimer_write(void *opaque,
target_phys_addr_t addr,
timerblock_write(&s->timerblock[id * 2], addr, value, size);
}
-static uint64_t arm_thiswdog_read(void *opaque, target_phys_addr_t addr,
+static uint64_t arm_thiswdog_read(void *opaque, Phys addr,
unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
@@ -185,7 +185,7 @@ static uint64_t arm_thiswdog_read(void *opaque,
target_phys_addr_t addr,
return timerblock_read(&s->timerblock[id * 2 + 1], addr, size);
}
-static void arm_thiswdog_write(void *opaque, target_phys_addr_t addr,
+static void arm_thiswdog_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
arm_mptimer_state *s = (arm_mptimer_state *)opaque;
diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
index 4b88648..87e6d45 100644
--- a/hw/arm_sysctl.c
+++ b/hw/arm_sysctl.c
@@ -92,7 +92,7 @@ static void arm_sysctl_reset(DeviceState *d)
}
}
-static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset,
+static uint64_t arm_sysctl_read(void *opaque, Phys offset,
unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
@@ -189,7 +189,7 @@ static uint64_t arm_sysctl_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
+static void arm_sysctl_write(void *opaque, Phys offset,
uint64_t val, unsigned size)
{
arm_sysctl_state *s = (arm_sysctl_state *)opaque;
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index 60e1c63..52913b9 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -44,7 +44,7 @@ static void arm_timer_update(arm_timer_state *s)
}
}
-static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
+static uint32_t arm_timer_read(void *opaque, Phys offset)
{
arm_timer_state *s = (arm_timer_state *)opaque;
@@ -86,7 +86,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int
reload)
ptimer_set_limit(s->timer, limit, reload);
}
-static void arm_timer_write(void *opaque, target_phys_addr_t offset,
+static void arm_timer_write(void *opaque, Phys offset,
uint32_t value)
{
arm_timer_state *s = (arm_timer_state *)opaque;
@@ -201,7 +201,7 @@ static void sp804_set_irq(void *opaque, int irq, int level)
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}
-static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
+static uint64_t sp804_read(void *opaque, Phys offset,
unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
@@ -229,7 +229,7 @@ static uint64_t sp804_read(void *opaque, target_phys_addr_t
offset,
return 0;
}
-static void sp804_write(void *opaque, target_phys_addr_t offset,
+static void sp804_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
sp804_state *s = (sp804_state *)opaque;
@@ -304,7 +304,7 @@ static int sp804_init(SysBusDevice *dev)
arm_timer_state *timer[3];
} icp_pit_state;
-static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
+static uint64_t icp_pit_read(void *opaque, Phys offset,
unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
@@ -319,7 +319,7 @@ static uint64_t icp_pit_read(void *opaque,
target_phys_addr_t offset,
return arm_timer_read(s->timer[n], offset & 0xff);
}
-static void icp_pit_write(void *opaque, target_phys_addr_t offset,
+static void icp_pit_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
icp_pit_state *s = (icp_pit_state *)opaque;
diff --git a/hw/armv7m.c b/hw/armv7m.c
index 5c7a950..714ef11 100644
--- a/hw/armv7m.c
+++ b/hw/armv7m.c
@@ -25,14 +25,14 @@ static inline uint32_t bitband_addr(void * opaque, uint32_t
addr)
}
-static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t bitband_readb(void *opaque, Phys offset)
{
uint8_t v;
cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
return (v & (1 << ((offset >> 2) & 7))) != 0;
}
-static void bitband_writeb(void *opaque, target_phys_addr_t offset,
+static void bitband_writeb(void *opaque, Phys offset,
uint32_t value)
{
uint32_t addr;
@@ -48,7 +48,7 @@ static void bitband_writeb(void *opaque, target_phys_addr_t
offset,
cpu_physical_memory_write(addr, &v, 1);
}
-static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t bitband_readw(void *opaque, Phys offset)
{
uint32_t addr;
uint16_t mask;
@@ -60,7 +60,7 @@ static uint32_t bitband_readw(void *opaque,
target_phys_addr_t offset)
return (v & mask) != 0;
}
-static void bitband_writew(void *opaque, target_phys_addr_t offset,
+static void bitband_writew(void *opaque, Phys offset,
uint32_t value)
{
uint32_t addr;
@@ -77,7 +77,7 @@ static void bitband_writew(void *opaque, target_phys_addr_t
offset,
cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
}
-static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t bitband_readl(void *opaque, Phys offset)
{
uint32_t addr;
uint32_t mask;
@@ -89,7 +89,7 @@ static uint32_t bitband_readl(void *opaque,
target_phys_addr_t offset)
return (v & mask) != 0;
}
-static void bitband_writel(void *opaque, target_phys_addr_t offset,
+static void bitband_writel(void *opaque, Phys offset,
uint32_t value)
{
uint32_t addr;
diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c
index c9301fd..a3a491a 100644
--- a/hw/axis_dev88.c
+++ b/hw/axis_dev88.c
@@ -47,7 +47,7 @@ struct nand_state_t
};
static struct nand_state_t nand_state;
-static uint64_t nand_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t nand_read(void *opaque, Phys addr, unsigned size)
{
struct nand_state_t *s = opaque;
uint32_t r;
@@ -62,7 +62,7 @@ static uint64_t nand_read(void *opaque, target_phys_addr_t
addr, unsigned size)
}
static void
-nand_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+nand_write(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
struct nand_state_t *s = opaque;
@@ -166,7 +166,7 @@ static void tempsensor_clkedge(struct tempsensor_t *s,
uint32_t regs[0x5c / 4];
} gpio_state;
-static uint64_t gpio_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t gpio_read(void *opaque, Phys addr, unsigned size)
{
struct gpio_state_t *s = opaque;
uint32_t r = 0;
@@ -195,7 +195,7 @@ static uint64_t gpio_read(void *opaque, target_phys_addr_t
addr, unsigned size)
D(printf("%s %x=%x\n", __func__, addr, r));
}
-static void gpio_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void gpio_write(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
struct gpio_state_t *s = opaque;
diff --git a/hw/bonito.c b/hw/bonito.c
index 04d706a..0ef9d6e 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -205,19 +205,19 @@
MemoryRegion iomem_ldma;
MemoryRegion iomem_cop;
- target_phys_addr_t bonito_pciio_start;
- target_phys_addr_t bonito_pciio_length;
+ Phys bonito_pciio_start;
+ Phys bonito_pciio_length;
int bonito_pciio_handle;
- target_phys_addr_t bonito_localio_start;
- target_phys_addr_t bonito_localio_length;
+ Phys bonito_localio_start;
+ Phys bonito_localio_length;
int bonito_localio_handle;
} PCIBonitoState;
PCIBonitoState * bonito_state;
-static void bonito_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_writel(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@@ -280,7 +280,7 @@ static void bonito_writel(void *opaque, target_phys_addr_t
addr,
}
}
-static uint64_t bonito_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t bonito_readl(void *opaque, Phys addr,
unsigned size)
{
PCIBonitoState *s = opaque;
@@ -307,7 +307,7 @@ static uint64_t bonito_readl(void *opaque,
target_phys_addr_t addr,
},
};
-static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_pciconf_writel(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@@ -316,7 +316,7 @@ static void bonito_pciconf_writel(void *opaque,
target_phys_addr_t addr,
s->dev.config_write(&s->dev, addr, val, 4);
}
-static uint64_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t bonito_pciconf_readl(void *opaque, Phys addr,
unsigned size)
{
@@ -338,7 +338,7 @@ static uint64_t bonito_pciconf_readl(void *opaque,
target_phys_addr_t addr,
},
};
-static uint64_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t bonito_ldma_readl(void *opaque, Phys addr,
unsigned size)
{
uint32_t val;
@@ -349,7 +349,7 @@ static uint64_t bonito_ldma_readl(void *opaque,
target_phys_addr_t addr,
return val;
}
-static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_ldma_writel(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@@ -367,7 +367,7 @@ static void bonito_ldma_writel(void *opaque,
target_phys_addr_t addr,
},
};
-static uint64_t bonito_cop_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t bonito_cop_readl(void *opaque, Phys addr,
unsigned size)
{
uint32_t val;
@@ -378,7 +378,7 @@ static uint64_t bonito_cop_readl(void *opaque,
target_phys_addr_t addr,
return val;
}
-static void bonito_cop_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_cop_writel(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
PCIBonitoState *s = opaque;
@@ -396,7 +396,7 @@ static void bonito_cop_writel(void *opaque,
target_phys_addr_t addr,
},
};
-static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
+static uint32_t bonito_sbridge_pciaddr(void *opaque, Phys addr)
{
PCIBonitoState *s = opaque;
uint32_t cfgaddr;
@@ -431,7 +431,7 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque,
target_phys_addr_t addr)
return pciaddr;
}
-static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr,
+static void bonito_spciconf_writeb(void *opaque, Phys addr,
uint32_t val)
{
PCIBonitoState *s = opaque;
@@ -455,7 +455,7 @@ static void bonito_spciconf_writeb(void *opaque,
target_phys_addr_t addr,
pci_set_word(s->dev.config + PCI_STATUS, status);
}
-static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr,
+static void bonito_spciconf_writew(void *opaque, Phys addr,
uint32_t val)
{
PCIBonitoState *s = opaque;
@@ -481,7 +481,7 @@ static void bonito_spciconf_writew(void *opaque,
target_phys_addr_t addr,
pci_set_word(s->dev.config + PCI_STATUS, status);
}
-static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,
+static void bonito_spciconf_writel(void *opaque, Phys addr,
uint32_t val)
{
PCIBonitoState *s = opaque;
@@ -507,7 +507,7 @@ static void bonito_spciconf_writel(void *opaque,
target_phys_addr_t addr,
pci_set_word(s->dev.config + PCI_STATUS, status);
}
-static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t bonito_spciconf_readb(void *opaque, Phys addr)
{
PCIBonitoState *s = opaque;
uint32_t pciaddr;
@@ -531,7 +531,7 @@ static uint32_t bonito_spciconf_readb(void *opaque,
target_phys_addr_t addr)
return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 1);
}
-static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t bonito_spciconf_readw(void *opaque, Phys addr)
{
PCIBonitoState *s = opaque;
uint32_t pciaddr;
@@ -557,7 +557,7 @@ static uint32_t bonito_spciconf_readw(void *opaque,
target_phys_addr_t addr)
return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 2);
}
-static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t bonito_spciconf_readl(void *opaque, Phys addr)
{
PCIBonitoState *s = opaque;
uint32_t pciaddr;
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index f7b1d3d..debfe7d 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -1954,7 +1954,7 @@ static void
cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
***************************************/
static uint64_t cirrus_vga_mem_read(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
uint32_t size)
{
CirrusVGAState *s = opaque;
@@ -1998,7 +1998,7 @@ static uint64_t cirrus_vga_mem_read(void *opaque,
}
static void cirrus_vga_mem_write(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
uint64_t mem_value,
uint32_t size)
{
@@ -2247,7 +2247,7 @@ static void cirrus_cursor_draw_line(VGACommonState *s1,
uint8_t *d1, int scr_y)
*
***************************************/
-static uint64_t cirrus_linear_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cirrus_linear_read(void *opaque, Phys addr,
unsigned size)
{
CirrusVGAState *s = opaque;
@@ -2276,7 +2276,7 @@ static uint64_t cirrus_linear_read(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,
+static void cirrus_linear_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
CirrusVGAState *s = opaque;
@@ -2325,7 +2325,7 @@ static void cirrus_linear_write(void *opaque,
target_phys_addr_t addr,
static uint64_t cirrus_linear_bitblt_read(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
unsigned size)
{
CirrusVGAState *s = opaque;
@@ -2338,7 +2338,7 @@ static uint64_t cirrus_linear_bitblt_read(void *opaque,
}
static void cirrus_linear_bitblt_write(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
uint64_t val,
unsigned size)
{
@@ -2628,7 +2628,7 @@ static void cirrus_vga_ioport_write(void *opaque,
uint32_t addr, uint32_t val)
*
***************************************/
-static uint64_t cirrus_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cirrus_mmio_read(void *opaque, Phys addr,
unsigned size)
{
CirrusVGAState *s = opaque;
@@ -2640,7 +2640,7 @@ static uint64_t cirrus_mmio_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void cirrus_mmio_write(void *opaque, target_phys_addr_t addr,
+static void cirrus_mmio_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
CirrusVGAState *s = opaque;
diff --git a/hw/cris-boot.h b/hw/cris-boot.h
index e9caf8d..f10d60b 100644
--- a/hw/cris-boot.h
+++ b/hw/cris-boot.h
@@ -5,7 +5,7 @@ struct cris_load_info
const char *cmdline;
int image_size;
- target_phys_addr_t entry;
+ Phys entry;
};
void cris_load_image(CPUState *env, struct cris_load_info *li);
diff --git a/hw/cs4231.c b/hw/cs4231.c
index 2dfb708..065e3f0 100644
--- a/hw/cs4231.c
+++ b/hw/cs4231.c
@@ -55,7 +55,7 @@ static void cs_reset(DeviceState *d)
s->dregs[25] = CS_VER;
}
-static uint64_t cs_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cs_mem_read(void *opaque, Phys addr,
unsigned size)
{
CSState *s = opaque;
@@ -82,7 +82,7 @@ static uint64_t cs_mem_read(void *opaque, target_phys_addr_t
addr,
return ret;
}
-static void cs_mem_write(void *opaque, target_phys_addr_t addr,
+static void cs_mem_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
CSState *s = opaque;
diff --git a/hw/cs4231a.c b/hw/cs4231a.c
index dc77a3a..4eda856 100644
--- a/hw/cs4231a.c
+++ b/hw/cs4231a.c
@@ -346,7 +346,7 @@ static void cs_reset_voices (CSState *s, uint32_t val)
}
}
-static uint64_t cs_read (void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t cs_read (void *opaque, Phys addr, unsigned size)
{
CSState *s = opaque;
uint32_t saddr, iaddr, ret;
@@ -383,7 +383,7 @@ static uint64_t cs_read (void *opaque, target_phys_addr_t
addr, unsigned size)
return ret;
}
-static void cs_write (void *opaque, target_phys_addr_t addr,
+static void cs_write (void *opaque, Phys addr,
uint64_t val64, unsigned size)
{
CSState *s = opaque;
diff --git a/hw/cuda.c b/hw/cuda.c
index 4077436..3ce9c8f 100644
--- a/hw/cuda.c
+++ b/hw/cuda.c
@@ -252,7 +252,7 @@ static void cuda_timer1(void *opaque)
cuda_update_irq(s);
}
-static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t cuda_readb(void *opaque, Phys addr)
{
CUDAState *s = opaque;
uint32_t val;
@@ -325,7 +325,7 @@ static uint32_t cuda_readb(void *opaque, target_phys_addr_t
addr)
return val;
}
-static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void cuda_writeb(void *opaque, Phys addr, uint32_t val)
{
CUDAState *s = opaque;
@@ -616,20 +616,20 @@ static void cuda_receive_packet_from_host(CUDAState *s,
}
}
-static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void cuda_writew (void *opaque, Phys addr, uint32_t value)
{
}
-static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void cuda_writel (void *opaque, Phys addr, uint32_t value)
{
}
-static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t cuda_readw (void *opaque, Phys addr)
{
return 0;
}
-static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t cuda_readl (void *opaque, Phys addr)
{
return 0;
}
diff --git a/hw/dma.c b/hw/dma.c
index 0a9322d..b3a4c71 100644
--- a/hw/dma.c
+++ b/hw/dma.c
@@ -411,7 +411,7 @@ void DMA_register_channel (int nchan,
int DMA_read_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
- target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) |
r->now[ADDR];
+ Phys addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
@@ -433,7 +433,7 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len)
int DMA_write_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
- target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) |
r->now[ADDR];
+ Phys addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
diff --git a/hw/dp8393x.c b/hw/dp8393x.c
index 017d074..3813343 100644
--- a/hw/dp8393x.c
+++ b/hw/dp8393x.c
@@ -168,7 +168,7 @@
int loopback_packet;
/* Memory access */
- void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int
len, int is_write);
+ void (*memory_rw)(void *opaque, Phys addr, uint8_t *buf, int len, int
is_write);
void* mem_opaque;
} dp8393xState;
@@ -603,7 +603,7 @@ static void dp8393x_watchdog(void *opaque)
dp8393x_update_irq(s);
}
-static uint32_t dp8393x_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t dp8393x_readw(void *opaque, Phys addr)
{
dp8393xState *s = opaque;
int reg;
@@ -616,13 +616,13 @@ static uint32_t dp8393x_readw(void *opaque,
target_phys_addr_t addr)
return read_register(s, reg);
}
-static uint32_t dp8393x_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t dp8393x_readb(void *opaque, Phys addr)
{
uint16_t v = dp8393x_readw(opaque, addr & ~0x1);
return (v >> (8 * (addr & 0x1))) & 0xff;
}
-static uint32_t dp8393x_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t dp8393x_readl(void *opaque, Phys addr)
{
uint32_t v;
v = dp8393x_readw(opaque, addr);
@@ -630,7 +630,7 @@ static uint32_t dp8393x_readl(void *opaque,
target_phys_addr_t addr)
return v;
}
-static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void dp8393x_writew(void *opaque, Phys addr, uint32_t val)
{
dp8393xState *s = opaque;
int reg;
@@ -644,7 +644,7 @@ static void dp8393x_writew(void *opaque, target_phys_addr_t
addr, uint32_t val)
write_register(s, reg, (uint16_t)val);
}
-static void dp8393x_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void dp8393x_writeb(void *opaque, Phys addr, uint32_t val)
{
uint16_t old_val = dp8393x_readw(opaque, addr & ~0x1);
@@ -659,7 +659,7 @@ static void dp8393x_writeb(void *opaque, target_phys_addr_t
addr, uint32_t val)
dp8393x_writew(opaque, addr & ~0x1, val);
}
-static void dp8393x_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void dp8393x_writel(void *opaque, Phys addr, uint32_t val)
{
dp8393x_writew(opaque, addr, val & 0xffff);
dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff);
@@ -879,10 +879,10 @@ static void nic_cleanup(VLANClientState *nc)
.cleanup = nic_cleanup,
};
-void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
+void dp83932_init(NICInfo *nd, Phys base, int it_shift,
MemoryRegion *address_space,
qemu_irq irq, void* mem_opaque,
- void (*memory_rw)(void *opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int is_write))
+ void (*memory_rw)(void *opaque, Phys addr, uint8_t *buf, int
len, int is_write))
{
dp8393xState *s;
diff --git a/hw/ds1225y.c b/hw/ds1225y.c
index 7aa0832..b6c8dc7 100644
--- a/hw/ds1225y.c
+++ b/hw/ds1225y.c
@@ -34,7 +34,7 @@
uint8_t *contents;
} NvRamState;
-static uint64_t nvram_read(void *opaque, target_phys_addr_t addr, unsigned
size)
+static uint64_t nvram_read(void *opaque, Phys addr, unsigned size)
{
NvRamState *s = opaque;
uint32_t val;
@@ -44,7 +44,7 @@ static uint64_t nvram_read(void *opaque, target_phys_addr_t
addr, unsigned size)
return val;
}
-static void nvram_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+static void nvram_write(void *opaque, Phys addr, uint64_t val,
unsigned size)
{
NvRamState *s = opaque;
diff --git a/hw/dummy_m68k.c b/hw/dummy_m68k.c
index e3c5740..ca7ade5 100644
--- a/hw/dummy_m68k.c
+++ b/hw/dummy_m68k.c
@@ -26,7 +26,7 @@ static void dummy_m68k_init(ram_addr_t ram_size,
MemoryRegion *ram = g_new(MemoryRegion, 1);
int kernel_size;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ Phys entry;
if (!cpu_model)
cpu_model = "cfv4e";
diff --git a/hw/e1000.c b/hw/e1000.c
index a29c944..b80e023 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -901,7 +901,7 @@ static void (*macreg_writeops[])(E1000State *, int,
uint32_t) = {
enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
static void
-e1000_mmio_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+e1000_mmio_write(void *opaque, Phys addr, uint64_t val,
unsigned size)
{
E1000State *s = opaque;
@@ -918,7 +918,7 @@ static void (*macreg_writeops[])(E1000State *, int,
uint32_t) = {
}
static uint64_t
-e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
+e1000_mmio_read(void *opaque, Phys addr, unsigned size)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
@@ -941,7 +941,7 @@ static void (*macreg_writeops[])(E1000State *, int,
uint32_t) = {
},
};
-static uint64_t e1000_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t e1000_io_read(void *opaque, Phys addr,
unsigned size)
{
E1000State *s = opaque;
@@ -950,7 +950,7 @@ static uint64_t e1000_io_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void e1000_io_write(void *opaque, target_phys_addr_t addr,
+static void e1000_io_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
E1000State *s = opaque;
diff --git a/hw/eccmemctl.c b/hw/eccmemctl.c
index 7743465..3215290 100644
--- a/hw/eccmemctl.c
+++ b/hw/eccmemctl.c
@@ -129,7 +129,7 @@
uint32_t version;
} ECCState;
-static void ecc_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+static void ecc_mem_write(void *opaque, Phys addr, uint64_t val,
unsigned size)
{
ECCState *s = opaque;
@@ -172,7 +172,7 @@ static void ecc_mem_write(void *opaque, target_phys_addr_t
addr, uint64_t val,
}
}
-static uint64_t ecc_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ecc_mem_read(void *opaque, Phys addr,
unsigned size)
{
ECCState *s = opaque;
@@ -229,7 +229,7 @@ static uint64_t ecc_mem_read(void *opaque,
target_phys_addr_t addr,
},
};
-static void ecc_diag_mem_write(void *opaque, target_phys_addr_t addr,
+static void ecc_diag_mem_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
ECCState *s = opaque;
@@ -238,7 +238,7 @@ static void ecc_diag_mem_write(void *opaque,
target_phys_addr_t addr,
s->diag[addr & ECC_DIAG_MASK] = val;
}
-static uint64_t ecc_diag_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ecc_diag_mem_read(void *opaque, Phys addr,
unsigned size)
{
ECCState *s = opaque;
diff --git a/hw/eepro100.c b/hw/eepro100.c
index 6a162f6..10b5ddc 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -1569,7 +1569,7 @@ static void eepro100_write4(EEPRO100State * s, uint32_t
addr, uint32_t val)
}
}
-static uint64_t eepro100_read(void *opaque, target_phys_addr_t addr,
+static uint64_t eepro100_read(void *opaque, Phys addr,
unsigned size)
{
EEPRO100State *s = opaque;
@@ -1582,7 +1582,7 @@ static uint64_t eepro100_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void eepro100_write(void *opaque, target_phys_addr_t addr,
+static void eepro100_write(void *opaque, Phys addr,
uint64_t data, unsigned size)
{
EEPRO100State *s = opaque;
diff --git a/hw/elf_ops.h b/hw/elf_ops.h
index 6af357f..7d5852d 100644
--- a/hw/elf_ops.h
+++ b/hw/elf_ops.h
@@ -74,7 +74,7 @@ static int glue(symfind, SZ)(const void *s0, const void *s1)
}
static const char *glue(lookup_symbol, SZ)(struct syminfo *s,
- target_phys_addr_t orig_addr)
+ Phys orig_addr)
{
struct elf_sym *syms = glue(s->disas_symtab.elf, SZ);
struct elf_sym key;
diff --git a/hw/empty_slot.c b/hw/empty_slot.c
index 8b734f2..f22ae53 100644
--- a/hw/empty_slot.c
+++ b/hw/empty_slot.c
@@ -28,14 +28,14 @@
uint64_t size;
} EmptySlot;
-static uint64_t empty_slot_read(void *opaque, target_phys_addr_t addr,
+static uint64_t empty_slot_read(void *opaque, Phys addr,
unsigned size)
{
DPRINTF("read from " TARGET_FMT_plx "\n", addr);
return 0;
}
-static void empty_slot_write(void *opaque, target_phys_addr_t addr,
+static void empty_slot_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", (unsigned)val, addr);
@@ -47,7 +47,7 @@ static void empty_slot_write(void *opaque, target_phys_addr_t
addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size)
+void empty_slot_init(Phys addr, uint64_t slot_size)
{
if (slot_size > 0) {
/* Only empty slots larger than 0 byte need handling. */
diff --git a/hw/empty_slot.h b/hw/empty_slot.h
index 78dc91d..da041db 100644
--- a/hw/empty_slot.h
+++ b/hw/empty_slot.h
@@ -1,2 +1,2 @@
/* empty_slot.c */
-void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size);
+void empty_slot_init(Phys addr, uint64_t slot_size);
diff --git a/hw/escc.c b/hw/escc.c
index 81204a6..efc7a38 100644
--- a/hw/escc.c
+++ b/hw/escc.c
@@ -463,7 +463,7 @@ static void escc_update_parameters(ChannelState *s)
qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
-static void escc_mem_write(void *opaque, target_phys_addr_t addr,
+static void escc_mem_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
SerialState *serial = opaque;
@@ -565,7 +565,7 @@ static void escc_mem_write(void *opaque, target_phys_addr_t
addr,
}
}
-static uint64_t escc_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t escc_mem_read(void *opaque, Phys addr,
unsigned size)
{
SerialState *serial = opaque;
@@ -683,7 +683,7 @@ static void serial_event(void *opaque, int event)
}
};
-MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
+MemoryRegion *escc_init(Phys base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift)
{
@@ -846,7 +846,7 @@ static void sunmouse_event(void *opaque,
put_queue(s, 0);
}
-void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
+void slavio_serial_ms_kbd_init(Phys base, qemu_irq irq,
int disabled, int clock, int it_shift)
{
DeviceState *dev;
diff --git a/hw/escc.h b/hw/escc.h
index d1da46f..b74eb51 100644
--- a/hw/escc.h
+++ b/hw/escc.h
@@ -1,8 +1,8 @@
/* escc.c */
#define ESCC_SIZE 4
-MemoryRegion *escc_init(target_phys_addr_t base, qemu_irq irqA, qemu_irq irqB,
+MemoryRegion *escc_init(Phys base, qemu_irq irqA, qemu_irq irqB,
CharDriverState *chrA, CharDriverState *chrB,
int clock, int it_shift);
-void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
+void slavio_serial_ms_kbd_init(Phys base, qemu_irq irq,
int disabled, int clock, int it_shift);
diff --git a/hw/esp.c b/hw/esp.c
index 9551c78..175c6a6 100644
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -505,7 +505,7 @@ static void esp_gpio_demux(void *opaque, int irq, int level)
}
}
-static uint64_t esp_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t esp_mem_read(void *opaque, Phys addr,
unsigned size)
{
ESPState *s = opaque;
@@ -547,7 +547,7 @@ static uint64_t esp_mem_read(void *opaque,
target_phys_addr_t addr,
return s->rregs[saddr];
}
-static void esp_mem_write(void *opaque, target_phys_addr_t addr,
+static void esp_mem_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
ESPState *s = opaque;
@@ -665,7 +665,7 @@ static void esp_mem_write(void *opaque, target_phys_addr_t
addr,
s->wregs[saddr] = val;
}
-static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr,
+static bool esp_mem_accepts(void *opaque, Phys addr,
unsigned size, bool is_write)
{
return (size == 1) || (is_write && size == 4);
@@ -700,7 +700,7 @@ static bool esp_mem_accepts(void *opaque,
target_phys_addr_t addr,
}
};
-void esp_init(target_phys_addr_t espaddr, int it_shift,
+void esp_init(Phys espaddr, int it_shift,
ESPDMAMemoryReadWriteFunc dma_memory_read,
ESPDMAMemoryReadWriteFunc dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset,
diff --git a/hw/esp.h b/hw/esp.h
index 62bfd4d..285908d 100644
--- a/hw/esp.h
+++ b/hw/esp.h
@@ -4,7 +4,7 @@
/* esp.c */
#define ESP_MAX_DEVS 7
typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
-void esp_init(target_phys_addr_t espaddr, int it_shift,
+void esp_init(Phys espaddr, int it_shift,
ESPDMAMemoryReadWriteFunc dma_memory_read,
ESPDMAMemoryReadWriteFunc dma_memory_write,
void *dma_opaque, qemu_irq irq, qemu_irq *reset,
diff --git a/hw/etraxfs.h b/hw/etraxfs.h
index 24e8fd8..7aa5f1d 100644
--- a/hw/etraxfs.h
+++ b/hw/etraxfs.h
@@ -29,7 +29,7 @@ qemu_irq *cris_pic_init_cpu(CPUState *env);
/* Instantiate an ETRAXFS Ethernet MAC. */
static inline DeviceState *
-etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr,
+etraxfs_eth_init(NICInfo *nd, Phys base, int phyaddr,
void *dma_out, void *dma_in)
{
DeviceState *dev;
diff --git a/hw/etraxfs_dma.c b/hw/etraxfs_dma.c
index d2bd584..06b4329 100644
--- a/hw/etraxfs_dma.c
+++ b/hw/etraxfs_dma.c
@@ -212,7 +212,7 @@ static inline int channel_en(struct fs_dma_ctrl *ctrl, int
c)
&& ctrl->channels[c].client;
}
-static inline int fs_channel(target_phys_addr_t addr)
+static inline int fs_channel(Phys addr)
{
/* Every channel has a 0x2000 ctrl register map. */
return addr >> 13;
@@ -221,7 +221,7 @@ static inline int fs_channel(target_phys_addr_t addr)
#ifdef USE_THIS_DEAD_CODE
static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
+ Phys addr = channel_reg(ctrl, c, RW_GROUP);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
@@ -253,7 +253,7 @@ static void dump_d(int ch, struct dma_descr_data *d)
static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
+ Phys addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Load and decode. FIXME: handle endianness. */
cpu_physical_memory_read (addr,
@@ -270,7 +270,7 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ Phys addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Load and decode. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@@ -284,7 +284,7 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
+ Phys addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@@ -296,7 +296,7 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
{
- target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
+ Phys addr = channel_reg(ctrl, c, RW_SAVED_DATA);
/* Encode and store. FIXME: handle endianness. */
D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
@@ -557,14 +557,14 @@ static inline int channel_in_run(struct fs_dma_ctrl
*ctrl, int c)
return 0;
}
-static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
+static uint32_t dma_rinvalid (void *opaque, Phys addr)
{
hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
return 0;
}
static uint64_t
-dma_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+dma_read(void *opaque, Phys addr, unsigned int size)
{
struct fs_dma_ctrl *ctrl = opaque;
int c;
@@ -596,7 +596,7 @@ static uint32_t dma_rinvalid (void *opaque,
target_phys_addr_t addr)
}
static void
-dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
+dma_winvalid (void *opaque, Phys addr, uint32_t value)
{
hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
}
@@ -611,7 +611,7 @@ static uint32_t dma_rinvalid (void *opaque,
target_phys_addr_t addr)
}
static void
-dma_write(void *opaque, target_phys_addr_t addr,
+dma_write(void *opaque, Phys addr,
uint64_t val64, unsigned int size)
{
struct fs_dma_ctrl *ctrl = opaque;
@@ -746,7 +746,7 @@ static void DMA_run(void *opaque)
qemu_bh_schedule_idle(etraxfs_dmac->bh);
}
-void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels)
+void *etraxfs_dmac_init(Phys base, int nr_channels)
{
struct fs_dma_ctrl *ctrl = NULL;
diff --git a/hw/etraxfs_dma.h b/hw/etraxfs_dma.h
index 96408ab..0693241 100644
--- a/hw/etraxfs_dma.h
+++ b/hw/etraxfs_dma.h
@@ -13,7 +13,7 @@ struct etraxfs_dma_client
} client;
};
-void *etraxfs_dmac_init(target_phys_addr_t base, int nr_channels);
+void *etraxfs_dmac_init(Phys base, int nr_channels);
void etraxfs_dmac_connect(void *opaque, int channel, qemu_irq *line,
int input);
void etraxfs_dmac_connect_client(void *opaque, int c,
diff --git a/hw/etraxfs_eth.c b/hw/etraxfs_eth.c
index b525258..ef35cdd 100644
--- a/hw/etraxfs_eth.c
+++ b/hw/etraxfs_eth.c
@@ -374,7 +374,7 @@ static void eth_validate_duplex(struct fs_eth *eth)
}
static uint64_t
-eth_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+eth_read(void *opaque, Phys addr, unsigned int size)
{
struct fs_eth *eth = opaque;
uint32_t r = 0;
@@ -418,7 +418,7 @@ static void eth_update_ma(struct fs_eth *eth, int ma)
}
static void
-eth_write(void *opaque, target_phys_addr_t addr,
+eth_write(void *opaque, Phys addr,
uint64_t val64, unsigned int size)
{
struct fs_eth *eth = opaque;
diff --git a/hw/etraxfs_pic.c b/hw/etraxfs_pic.c
index 993d6a8..90ce6db 100644
--- a/hw/etraxfs_pic.c
+++ b/hw/etraxfs_pic.c
@@ -79,7 +79,7 @@ static void pic_update(struct etrax_pic *fs)
}
static uint64_t
-pic_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+pic_read(void *opaque, Phys addr, unsigned int size)
{
struct etrax_pic *fs = opaque;
uint32_t rval;
@@ -89,7 +89,7 @@ static void pic_update(struct etrax_pic *fs)
return rval;
}
-static void pic_write(void *opaque, target_phys_addr_t addr,
+static void pic_write(void *opaque, Phys addr,
uint64_t value, unsigned int size)
{
struct etrax_pic *fs = opaque;
diff --git a/hw/etraxfs_ser.c b/hw/etraxfs_ser.c
index 2623dab..fd87b99 100644
--- a/hw/etraxfs_ser.c
+++ b/hw/etraxfs_ser.c
@@ -75,7 +75,7 @@ static void ser_update_irq(struct etrax_serial *s)
}
static uint64_t
-ser_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+ser_read(void *opaque, Phys addr, unsigned int size)
{
struct etrax_serial *s = opaque;
D(CPUState *env = s->env);
@@ -110,7 +110,7 @@ static void ser_update_irq(struct etrax_serial *s)
}
static void
-ser_write(void *opaque, target_phys_addr_t addr,
+ser_write(void *opaque, Phys addr,
uint64_t val64, unsigned int size)
{
struct etrax_serial *s = opaque;
diff --git a/hw/etraxfs_timer.c b/hw/etraxfs_timer.c
index 319cee1..bb7833b 100644
--- a/hw/etraxfs_timer.c
+++ b/hw/etraxfs_timer.c
@@ -74,7 +74,7 @@ struct etrax_timer {
};
static uint64_t
-timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+timer_read(void *opaque, Phys addr, unsigned int size)
{
struct etrax_timer *t = opaque;
uint32_t r = 0;
@@ -241,7 +241,7 @@ static inline void timer_watchdog_update(struct etrax_timer
*t, uint32_t value)
}
static void
-timer_write(void *opaque, target_phys_addr_t addr,
+timer_write(void *opaque, Phys addr,
uint64_t val64, unsigned int size)
{
struct etrax_timer *t = opaque;
diff --git a/hw/fdc.c b/hw/fdc.c
index 70aa5c7..1adce37 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -492,13 +492,13 @@ static void fdctrl_write (void *opaque, uint32_t reg,
uint32_t value)
}
}
-static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
+static uint64_t fdctrl_read_mem (void *opaque, Phys reg,
unsigned ize)
{
return fdctrl_read(opaque, (uint32_t)reg);
}
-static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
+static void fdctrl_write_mem (void *opaque, Phys reg,
uint64_t value, unsigned size)
{
fdctrl_write(opaque, (uint32_t)reg, value);
@@ -1805,7 +1805,7 @@ static int fdctrl_connect_drives(FDCtrl *fdctrl)
}
void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
- target_phys_addr_t mmio_base, DriveInfo **fds)
+ Phys mmio_base, DriveInfo **fds)
{
FDCtrl *fdctrl;
DeviceState *dev;
@@ -1826,7 +1826,7 @@ void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
sysbus_mmio_map(&sys->busdev, 0, mmio_base);
}
-void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
+void sun4m_fdctrl_init(qemu_irq irq, Phys io_base,
DriveInfo **fds, qemu_irq *fdc_tc)
{
DeviceState *dev;
diff --git a/hw/fdc.h b/hw/fdc.h
index 55a8d73..fdbc823 100644
--- a/hw/fdc.h
+++ b/hw/fdc.h
@@ -28,8 +28,8 @@ static inline ISADevice *fdctrl_init_isa(ISABus *bus,
DriveInfo **fds)
}
void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
- target_phys_addr_t mmio_base, DriveInfo **fds);
-void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
+ Phys mmio_base, DriveInfo **fds);
+void sun4m_fdctrl_init(qemu_irq irq, Phys io_base,
DriveInfo **fds, qemu_irq *fdc_tc);
void fdc_get_bs(BlockDriverState *bs[], ISADevice *dev);
diff --git a/hw/flash.h b/hw/flash.h
index 9c9e526..8047333 100644
--- a/hw/flash.h
+++ b/hw/flash.h
@@ -5,18 +5,18 @@
typedef struct pflash_t pflash_t;
/* pflash_cfi01.c */
-pflash_t *pflash_cfi01_register(target_phys_addr_t base,
+pflash_t *pflash_cfi01_register(Phys base,
DeviceState *qdev, const char *name,
- target_phys_addr_t size,
+ Phys size,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, int be);
/* pflash_cfi02.c */
-pflash_t *pflash_cfi02_register(target_phys_addr_t base,
+pflash_t *pflash_cfi02_register(Phys base,
DeviceState *qdev, const char *name,
- target_phys_addr_t size,
+ Phys size,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
diff --git a/hw/framebuffer.c b/hw/framebuffer.c
index b43bcdf..b125ffa 100644
--- a/hw/framebuffer.c
+++ b/hw/framebuffer.c
@@ -23,7 +23,7 @@
void framebuffer_update_display(
DisplayState *ds,
MemoryRegion *address_space,
- target_phys_addr_t base,
+ Phys base,
int cols, /* Width in pixels. */
int rows, /* Leight in pixels. */
int src_width, /* Length of source line, in bytes. */
@@ -35,7 +35,7 @@ void framebuffer_update_display(
int *first_row, /* Input and output. */
int *last_row /* Output only */)
{
- target_phys_addr_t src_len;
+ Phys src_len;
uint8_t *dest;
uint8_t *src;
uint8_t *src_base;
@@ -84,7 +84,7 @@ void framebuffer_update_display(
dest += i * dest_row_pitch;
for (; i < rows; i++) {
- target_phys_addr_t dirty_offset;
+ Phys dirty_offset;
dirty = 0;
dirty_offset = 0;
while (addr + dirty_offset < TARGET_PAGE_ALIGN(addr + src_width)) {
diff --git a/hw/framebuffer.h b/hw/framebuffer.h
index 527a6b8..0cade6d 100644
--- a/hw/framebuffer.h
+++ b/hw/framebuffer.h
@@ -10,7 +10,7 @@ typedef void (*drawfn)(void *, uint8_t *, const uint8_t *,
int, int);
void framebuffer_update_display(
DisplayState *ds,
MemoryRegion *address_space,
- target_phys_addr_t base,
+ Phys base,
int cols,
int rows,
int src_width,
diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
index f953532..77873fb 100644
--- a/hw/fw_cfg.c
+++ b/hw/fw_cfg.c
@@ -234,37 +234,37 @@ static uint8_t fw_cfg_read(FWCfgState *s)
return ret;
}
-static uint64_t fw_cfg_data_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t fw_cfg_data_mem_read(void *opaque, Phys addr,
unsigned size)
{
return fw_cfg_read(opaque);
}
-static void fw_cfg_data_mem_write(void *opaque, target_phys_addr_t addr,
+static void fw_cfg_data_mem_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
fw_cfg_write(opaque, (uint8_t)value);
}
-static void fw_cfg_ctl_mem_write(void *opaque, target_phys_addr_t addr,
+static void fw_cfg_ctl_mem_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
fw_cfg_select(opaque, (uint16_t)value);
}
-static bool fw_cfg_ctl_mem_valid(void *opaque, target_phys_addr_t addr,
+static bool fw_cfg_ctl_mem_valid(void *opaque, Phys addr,
unsigned size, bool is_write)
{
return is_write && size == 2;
}
-static uint64_t fw_cfg_comb_read(void *opaque, target_phys_addr_t addr,
+static uint64_t fw_cfg_comb_read(void *opaque, Phys addr,
unsigned size)
{
return fw_cfg_read(opaque);
}
-static void fw_cfg_comb_write(void *opaque, target_phys_addr_t addr,
+static void fw_cfg_comb_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
switch (size) {
@@ -277,7 +277,7 @@ static void fw_cfg_comb_write(void *opaque,
target_phys_addr_t addr,
}
}
-static bool fw_cfg_comb_valid(void *opaque, target_phys_addr_t addr,
+static bool fw_cfg_comb_valid(void *opaque, Phys addr,
unsigned size, bool is_write)
{
return (size == 1) || (is_write && size == 2);
@@ -470,7 +470,7 @@ static void fw_cfg_machine_ready(struct Notifier *n, void
*data)
}
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
- target_phys_addr_t ctl_addr, target_phys_addr_t
data_addr)
+ Phys ctl_addr, Phys data_addr)
{
DeviceState *dev;
SysBusDevice *d;
diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h
index 856bf91..b2d7435 100644
--- a/hw/fw_cfg.h
+++ b/hw/fw_cfg.h
@@ -63,7 +63,7 @@ int fw_cfg_add_callback(FWCfgState *s, uint16_t key,
FWCfgCallback callback,
int fw_cfg_add_file(FWCfgState *s, const char *filename, uint8_t *data,
uint32_t len);
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
- target_phys_addr_t crl_addr, target_phys_addr_t
data_addr);
+ Phys crl_addr, Phys data_addr);
#endif /* NO_QEMU_PROTOS */
diff --git a/hw/g364fb.c b/hw/g364fb.c
index 33ec149..013dd7e 100644
--- a/hw/g364fb.c
+++ b/hw/g364fb.c
@@ -335,7 +335,7 @@ static void g364fb_screen_dump(void *opaque, const char
*filename)
/* called for accesses to io ports */
static uint64_t g364fb_ctrl_read(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
unsigned int size)
{
G364State *s = opaque;
@@ -399,7 +399,7 @@ static void g364_invalidate_cursor_position(G364State *s)
}
static void g364fb_ctrl_write(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
uint64_t val,
unsigned int size)
{
diff --git a/hw/grlib.h b/hw/grlib.h
index fdf4b11..4ff417c 100644
--- a/hw/grlib.h
+++ b/hw/grlib.h
@@ -41,7 +41,7 @@ void grlib_irqmp_set_irq(void *opaque, int irq, int level);
void grlib_irqmp_ack(DeviceState *dev, int intno);
static inline
-DeviceState *grlib_irqmp_create(target_phys_addr_t base,
+DeviceState *grlib_irqmp_create(Phys base,
CPUState *env,
qemu_irq **cpu_irqs,
uint32_t nr_irqs,
@@ -73,7 +73,7 @@ DeviceState *grlib_irqmp_create(target_phys_addr_t base,
/* GPTimer */
static inline
-DeviceState *grlib_gptimer_create(target_phys_addr_t base,
+DeviceState *grlib_gptimer_create(Phys base,
uint32_t nr_timers,
uint32_t freq,
qemu_irq *cpu_irqs,
@@ -103,7 +103,7 @@ DeviceState *grlib_gptimer_create(target_phys_addr_t base,
/* APB UART */
static inline
-DeviceState *grlib_apbuart_create(target_phys_addr_t base,
+DeviceState *grlib_apbuart_create(Phys base,
CharDriverState *serial,
qemu_irq irq)
{
diff --git a/hw/grlib_apbuart.c b/hw/grlib_apbuart.c
index 62bdb03..e8d6aa2 100644
--- a/hw/grlib_apbuart.c
+++ b/hw/grlib_apbuart.c
@@ -103,7 +103,7 @@ static void grlib_apbuart_event(void *opaque, int event)
}
static void
-grlib_apbuart_write(void *opaque, target_phys_addr_t addr,
+grlib_apbuart_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
UART *uart = opaque;
@@ -137,7 +137,7 @@ static void grlib_apbuart_event(void *opaque, int event)
trace_grlib_apbuart_writel_unknown(addr, value);
}
-static bool grlib_apbuart_accepts(void *opaque, target_phys_addr_t addr,
+static bool grlib_apbuart_accepts(void *opaque, Phys addr,
unsigned size, bool is_write)
{
return is_write && size == 4;
diff --git a/hw/grlib_gptimer.c b/hw/grlib_gptimer.c
index 5645054..2c308aa 100644
--- a/hw/grlib_gptimer.c
+++ b/hw/grlib_gptimer.c
@@ -154,11 +154,11 @@ static void grlib_gptimer_hit(void *opaque)
}
}
-static uint64_t grlib_gptimer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t grlib_gptimer_read(void *opaque, Phys addr,
unsigned size)
{
GPTimerUnit *unit = opaque;
- target_phys_addr_t timer_addr;
+ Phys timer_addr;
int id;
uint32_t value = 0;
@@ -213,11 +213,11 @@ static uint64_t grlib_gptimer_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void grlib_gptimer_write(void *opaque, target_phys_addr_t addr,
+static void grlib_gptimer_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
GPTimerUnit *unit = opaque;
- target_phys_addr_t timer_addr;
+ Phys timer_addr;
int id;
addr &= 0xff;
diff --git a/hw/grlib_irqmp.c b/hw/grlib_irqmp.c
index 2872556..db16b46 100644
--- a/hw/grlib_irqmp.c
+++ b/hw/grlib_irqmp.c
@@ -162,7 +162,7 @@ void grlib_irqmp_set_irq(void *opaque, int irq, int level)
}
}
-static uint64_t grlib_irqmp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t grlib_irqmp_read(void *opaque, Phys addr,
unsigned size)
{
IRQMP *irqmp = opaque;
@@ -226,7 +226,7 @@ static uint64_t grlib_irqmp_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void grlib_irqmp_write(void *opaque, target_phys_addr_t addr,
+static void grlib_irqmp_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
IRQMP *irqmp = opaque;
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 432683a..c96165b 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -225,8 +225,8 @@
#define GT_PCI1_SERR1MASK (0xca8 >> 2)
#define PCI_MAPPING_ENTRY(regname) \
- target_phys_addr_t regname ##_start; \
- target_phys_addr_t regname ##_length; \
+ Phys regname ##_start; \
+ Phys regname ##_length; \
MemoryRegion regname ##_mem
typedef struct GT64120State {
@@ -240,11 +240,11 @@
/* Adjust range to avoid touching space which isn't mappable via PCI */
/* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
0x1fc00000 - 0x1fd00000 */
-static void check_reserved_space (target_phys_addr_t *start,
- target_phys_addr_t *length)
+static void check_reserved_space (Phys *start,
+ Phys *length)
{
- target_phys_addr_t begin = *start;
- target_phys_addr_t end = *start + *length;
+ Phys begin = *start;
+ Phys end = *start + *length;
if (end >= 0x1e000000LL && end < 0x1f100000LL)
end = 0x1e000000LL;
@@ -266,8 +266,8 @@ static void check_reserved_space (target_phys_addr_t *start,
static void gt64120_isd_mapping(GT64120State *s)
{
- target_phys_addr_t start = s->regs[GT_ISD] << 21;
- target_phys_addr_t length = 0x1000;
+ Phys start = s->regs[GT_ISD] << 21;
+ Phys length = 0x1000;
if (s->ISD_length) {
memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
@@ -306,7 +306,7 @@ static void gt64120_pci_mapping(GT64120State *s)
}
}
-static void gt64120_writel (void *opaque, target_phys_addr_t addr,
+static void gt64120_writel (void *opaque, Phys addr,
uint64_t val, unsigned size)
{
GT64120State *s = opaque;
@@ -586,7 +586,7 @@ static void gt64120_writel (void *opaque,
target_phys_addr_t addr,
}
static uint64_t gt64120_readl (void *opaque,
- target_phys_addr_t addr, unsigned size)
+ Phys addr, unsigned size)
{
GT64120State *s = opaque;
uint32_t val;
diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c
index 16f48d1..ecdd0bf 100644
--- a/hw/heathrow_pic.c
+++ b/hw/heathrow_pic.c
@@ -63,7 +63,7 @@ static void heathrow_pic_update(HeathrowPICS *s)
}
}
-static void pic_write(void *opaque, target_phys_addr_t addr,
+static void pic_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
HeathrowPICS *s = opaque;
@@ -91,7 +91,7 @@ static void pic_write(void *opaque, target_phys_addr_t addr,
}
}
-static uint64_t pic_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pic_read(void *opaque, Phys addr,
unsigned size)
{
HeathrowPICS *s = opaque;
diff --git a/hw/hpet.c b/hw/hpet.c
index 5312df7..4a0976b 100644
--- a/hw/hpet.c
+++ b/hw/hpet.c
@@ -342,20 +342,20 @@ static void hpet_del_timer(HPETTimer *t)
}
#ifdef HPET_DEBUG
-static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t hpet_ram_readb(void *opaque, Phys addr)
{
printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
return 0;
}
-static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t hpet_ram_readw(void *opaque, Phys addr)
{
printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
return 0;
}
#endif
-static uint64_t hpet_ram_read(void *opaque, target_phys_addr_t addr,
+static uint64_t hpet_ram_read(void *opaque, Phys addr,
unsigned size)
{
HPETState *s = opaque;
@@ -427,7 +427,7 @@ static uint64_t hpet_ram_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void hpet_ram_write(void *opaque, target_phys_addr_t addr,
+static void hpet_ram_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
int i;
diff --git a/hw/i8259.c b/hw/i8259.c
index 7331e0e..b3890cd 100644
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -275,7 +275,7 @@ static void pic_reset(DeviceState *dev)
s->elcr = 0;
}
-static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
+static void pic_ioport_write(void *opaque, Phys addr64,
uint64_t val64, unsigned size)
{
PicState *s = opaque;
@@ -369,7 +369,7 @@ static void pic_ioport_write(void *opaque,
target_phys_addr_t addr64,
}
}
-static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pic_ioport_read(void *opaque, Phys addr,
unsigned size)
{
PicState *s = opaque;
@@ -404,14 +404,14 @@ int pic_get_output(PicState *s)
return (pic_get_irq(s) >= 0);
}
-static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
+static void elcr_ioport_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
PicState *s = opaque;
s->elcr = val & s->elcr_mask;
}
-static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t elcr_ioport_read(void *opaque, Phys addr,
unsigned size)
{
PicState *s = opaque;
diff --git a/hw/ide.h b/hw/ide.h
index 0b18c90..6e58ad2 100644
--- a/hw/ide.h
+++ b/hw/ide.h
@@ -24,7 +24,7 @@ MemoryRegion *pmac_ide_init (DriveInfo **hd_table, qemu_irq
irq,
void *dbdma, int channel, qemu_irq dma_irq);
/* ide-mmio.c */
-void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
+void mmio_ide_init (Phys membase, Phys membase2,
MemoryRegion *address_space,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1);
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 0af201d..64c07ca 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -172,7 +172,7 @@ static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,
static void map_page(uint8_t **ptr, uint64_t addr, uint32_t wanted)
{
- target_phys_addr_t len = wanted;
+ Phys len = wanted;
if (*ptr) {
cpu_physical_memory_unmap(*ptr, len, 1, len);
@@ -276,7 +276,7 @@ static void ahci_port_write(AHCIState *s, int port, int
offset, uint32_t val)
}
}
-static uint64_t ahci_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ahci_mem_read(void *opaque, Phys addr,
unsigned size)
{
AHCIState *s = opaque;
@@ -314,7 +314,7 @@ static uint64_t ahci_mem_read(void *opaque,
target_phys_addr_t addr,
-static void ahci_mem_write(void *opaque, target_phys_addr_t addr,
+static void ahci_mem_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
AHCIState *s = opaque;
@@ -370,7 +370,7 @@ static void ahci_mem_write(void *opaque, target_phys_addr_t
addr,
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static uint64_t ahci_idp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ahci_idp_read(void *opaque, Phys addr,
unsigned size)
{
AHCIState *s = opaque;
@@ -386,7 +386,7 @@ static uint64_t ahci_idp_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void ahci_idp_write(void *opaque, target_phys_addr_t addr,
+static void ahci_idp_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
AHCIState *s = opaque;
@@ -629,7 +629,7 @@ static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t
*cmd_fis)
AHCIPortRegs *pr = &ad->port_regs;
uint8_t *d2h_fis;
int i;
- target_phys_addr_t cmd_len = 0x80;
+ Phys cmd_len = 0x80;
int cmd_mapped = 0;
if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {
@@ -681,8 +681,8 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList
*sglist)
uint32_t opts = le32_to_cpu(cmd->opts);
uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80;
int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN;
- target_phys_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG));
- target_phys_addr_t real_prdt_len = prdt_len;
+ Phys prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG));
+ Phys real_prdt_len = prdt_len;
uint8_t *prdt;
int i;
int r = 0;
@@ -829,7 +829,7 @@ static int handle_cmd(AHCIState *s, int port, int slot)
uint64_t tbl_addr;
AHCICmdHdr *cmd;
uint8_t *cmd_fis;
- target_phys_addr_t cmd_len;
+ Phys cmd_len;
if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) {
/* Engine currently busy, try again later */
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index 5fe98b1..996e1e9 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -43,7 +43,7 @@
static void cmd646_update_irq(PCIIDEState *d);
-static uint64_t cmd646_cmd_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cmd646_cmd_read(void *opaque, Phys addr,
unsigned size)
{
CMD646BAR *cmd646bar = opaque;
@@ -54,7 +54,7 @@ static uint64_t cmd646_cmd_read(void *opaque,
target_phys_addr_t addr,
return ide_status_read(cmd646bar->bus, addr + 2);
}
-static void cmd646_cmd_write(void *opaque, target_phys_addr_t addr,
+static void cmd646_cmd_write(void *opaque, Phys addr,
uint64_t data, unsigned size)
{
CMD646BAR *cmd646bar = opaque;
@@ -71,7 +71,7 @@ static void cmd646_cmd_write(void *opaque, target_phys_addr_t
addr,
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static uint64_t cmd646_data_read(void *opaque, target_phys_addr_t addr,
+static uint64_t cmd646_data_read(void *opaque, Phys addr,
unsigned size)
{
CMD646BAR *cmd646bar = opaque;
@@ -88,7 +88,7 @@ static uint64_t cmd646_data_read(void *opaque,
target_phys_addr_t addr,
return ((uint64_t)1 << (size * 8)) - 1;
}
-static void cmd646_data_write(void *opaque, target_phys_addr_t addr,
+static void cmd646_data_write(void *opaque, Phys addr,
uint64_t data, unsigned size)
{
CMD646BAR *cmd646bar = opaque;
@@ -121,7 +121,7 @@ static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
memory_region_init_io(&bar->data, &cmd646_data_ops, bar, "cmd646-data", 8);
}
-static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t bmdma_read(void *opaque, Phys addr,
unsigned size)
{
BMDMAState *bm = opaque;
@@ -159,7 +159,7 @@ static uint64_t bmdma_read(void *opaque, target_phys_addr_t
addr,
return val;
}
-static void bmdma_write(void *opaque, target_phys_addr_t addr,
+static void bmdma_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
BMDMAState *bm = opaque;
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index abbc41b..d8c9bdf 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -198,7 +198,7 @@ static void pmac_ide_flush(DBDMA_io *io)
/* PowerMac IDE memory IO */
static void pmac_ide_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ Phys addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@@ -216,7 +216,7 @@ static void pmac_ide_writeb (void *opaque,
}
}
-static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
+static uint32_t pmac_ide_readb (void *opaque,Phys addr)
{
uint8_t retval;
MACIOIDEState *d = opaque;
@@ -238,7 +238,7 @@ static uint32_t pmac_ide_readb (void
*opaque,target_phys_addr_t addr)
}
static void pmac_ide_writew (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ Phys addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@@ -249,7 +249,7 @@ static void pmac_ide_writew (void *opaque,
}
}
-static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
+static uint32_t pmac_ide_readw (void *opaque,Phys addr)
{
uint16_t retval;
MACIOIDEState *d = opaque;
@@ -265,7 +265,7 @@ static uint32_t pmac_ide_readw (void
*opaque,target_phys_addr_t addr)
}
static void pmac_ide_writel (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ Phys addr, uint32_t val)
{
MACIOIDEState *d = opaque;
@@ -276,7 +276,7 @@ static void pmac_ide_writel (void *opaque,
}
}
-static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
+static uint32_t pmac_ide_readl (void *opaque,Phys addr)
{
uint32_t retval;
MACIOIDEState *d = opaque;
diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c
index fcfb09e..969ce88 100644
--- a/hw/ide/mmio.c
+++ b/hw/ide/mmio.c
@@ -47,7 +47,7 @@ static void mmio_ide_reset(void *opaque)
ide_bus_reset(&s->bus);
}
-static uint64_t mmio_ide_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mmio_ide_read(void *opaque, Phys addr,
unsigned size)
{
MMIOState *s = opaque;
@@ -58,7 +58,7 @@ static uint64_t mmio_ide_read(void *opaque,
target_phys_addr_t addr,
return ide_data_readw(&s->bus, 0);
}
-static void mmio_ide_write(void *opaque, target_phys_addr_t addr,
+static void mmio_ide_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
@@ -75,14 +75,14 @@ static void mmio_ide_write(void *opaque, target_phys_addr_t
addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t mmio_ide_status_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mmio_ide_status_read(void *opaque, Phys addr,
unsigned size)
{
MMIOState *s= opaque;
return ide_status_read(&s->bus, 0);
}
-static void mmio_ide_cmd_write(void *opaque, target_phys_addr_t addr,
+static void mmio_ide_cmd_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
MMIOState *s = opaque;
@@ -107,7 +107,7 @@ static void mmio_ide_cmd_write(void *opaque,
target_phys_addr_t addr,
}
};
-void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2,
+void mmio_ide_init (Phys membase, Phys membase2,
MemoryRegion *address_space,
qemu_irq irq, int shift,
DriveInfo *hd0, DriveInfo *hd1)
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index 3473345..ad129b9 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -32,7 +32,7 @@
#include <hw/ide/pci.h>
-static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned
size)
+static uint64_t bmdma_read(void *opaque, Phys addr, unsigned size)
{
BMDMAState *bm = opaque;
uint32_t val;
@@ -58,7 +58,7 @@ static uint64_t bmdma_read(void *opaque, target_phys_addr_t
addr, unsigned size)
return val;
}
-static void bmdma_write(void *opaque, target_phys_addr_t addr,
+static void bmdma_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
BMDMAState *bm = opaque;
diff --git a/hw/ide/via.c b/hw/ide/via.c
index 4ea2064..5965931 100644
--- a/hw/ide/via.c
+++ b/hw/ide/via.c
@@ -33,7 +33,7 @@
#include <hw/ide/pci.h>
-static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t bmdma_read(void *opaque, Phys addr,
unsigned size)
{
BMDMAState *bm = opaque;
@@ -60,7 +60,7 @@ static uint64_t bmdma_read(void *opaque, target_phys_addr_t
addr,
return val;
}
-static void bmdma_write(void *opaque, target_phys_addr_t addr,
+static void bmdma_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
BMDMAState *bm = opaque;
diff --git a/hw/integratorcp.c b/hw/integratorcp.c
index c8f3955..c0ee7c6 100644
--- a/hw/integratorcp.c
+++ b/hw/integratorcp.c
@@ -40,7 +40,7 @@
0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
};
-static uint64_t integratorcm_read(void *opaque, target_phys_addr_t offset,
+static uint64_t integratorcm_read(void *opaque, Phys offset,
unsigned size)
{
integratorcm_state *s = (integratorcm_state *)opaque;
@@ -153,7 +153,7 @@ static void integratorcm_update(integratorcm_state *s)
hw_error("Core module interrupt\n");
}
-static void integratorcm_write(void *opaque, target_phys_addr_t offset,
+static void integratorcm_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
integratorcm_state *s = (integratorcm_state *)opaque;
@@ -308,7 +308,7 @@ static void icp_pic_set_irq(void *opaque, int irq, int
level)
icp_pic_update(s);
}
-static uint64_t icp_pic_read(void *opaque, target_phys_addr_t offset,
+static uint64_t icp_pic_read(void *opaque, Phys offset,
unsigned size)
{
icp_pic_state *s = (icp_pic_state *)opaque;
@@ -337,7 +337,7 @@ static uint64_t icp_pic_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void icp_pic_write(void *opaque, target_phys_addr_t offset,
+static void icp_pic_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
icp_pic_state *s = (icp_pic_state *)opaque;
@@ -394,7 +394,7 @@ static int icp_pic_init(SysBusDevice *dev)
/* CP control registers. */
-static uint64_t icp_control_read(void *opaque, target_phys_addr_t offset,
+static uint64_t icp_control_read(void *opaque, Phys offset,
unsigned size)
{
switch (offset >> 2) {
@@ -412,7 +412,7 @@ static uint64_t icp_control_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void icp_control_write(void *opaque, target_phys_addr_t offset,
+static void icp_control_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
switch (offset >> 2) {
@@ -432,7 +432,7 @@ static void icp_control_write(void *opaque,
target_phys_addr_t offset,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void icp_control_init(target_phys_addr_t base)
+static void icp_control_init(Phys base)
{
MemoryRegion *io;
diff --git a/hw/intel-hda.c b/hw/intel-hda.c
index 10769e0..c37b22d 100644
--- a/hw/intel-hda.c
+++ b/hw/intel-hda.c
@@ -211,9 +211,9 @@ struct IntelHDAReg {
/* --------------------------------------------------------------------- */
-static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
+static Phys intel_hda_addr(uint32_t lbase, uint32_t ubase)
{
- target_phys_addr_t addr;
+ Phys addr;
#if TARGET_PHYS_ADDR_BITS == 32
addr = lbase;
@@ -304,7 +304,7 @@ static int intel_hda_send_command(IntelHDAState *d,
uint32_t verb)
static void intel_hda_corb_run(IntelHDAState *d)
{
- target_phys_addr_t addr;
+ Phys addr;
uint32_t rp, verb;
if (d->ics & ICH6_IRS_BUSY) {
@@ -341,7 +341,7 @@ static void intel_hda_response(HDACodecDevice *dev, bool
solicited, uint32_t res
{
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
- target_phys_addr_t addr;
+ Phys addr;
uint32_t wp, ex;
if (d->ics & ICH6_IRS_BUSY) {
@@ -390,7 +390,7 @@ static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t
stnr, bool output,
{
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
- target_phys_addr_t addr;
+ Phys addr;
uint32_t s, copy, left;
IntelHDAStream *st;
bool irq = false;
@@ -462,7 +462,7 @@ static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t
stnr, bool output,
static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
{
- target_phys_addr_t addr;
+ Phys addr;
uint8_t buf[16];
uint32_t i;
@@ -895,7 +895,7 @@ static void intel_hda_set_st_ctl(IntelHDAState *d, const
IntelHDAReg *reg, uint3
};
-static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d,
target_phys_addr_t addr)
+static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, Phys addr)
{
const IntelHDAReg *reg;
@@ -1038,7 +1038,7 @@ static void intel_hda_regs_reset(IntelHDAState *d)
/* --------------------------------------------------------------------- */
-static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
+static void intel_hda_mmio_writeb(void *opaque, Phys addr, uint32_t val)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
@@ -1046,7 +1046,7 @@ static void intel_hda_mmio_writeb(void *opaque,
target_phys_addr_t addr, uint32_
intel_hda_reg_write(d, reg, val, 0xff);
}
-static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
+static void intel_hda_mmio_writew(void *opaque, Phys addr, uint32_t val)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
@@ -1054,7 +1054,7 @@ static void intel_hda_mmio_writew(void *opaque,
target_phys_addr_t addr, uint32_
intel_hda_reg_write(d, reg, val, 0xffff);
}
-static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
+static void intel_hda_mmio_writel(void *opaque, Phys addr, uint32_t val)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
@@ -1062,7 +1062,7 @@ static void intel_hda_mmio_writel(void *opaque,
target_phys_addr_t addr, uint32_
intel_hda_reg_write(d, reg, val, 0xffffffff);
}
-static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t intel_hda_mmio_readb(void *opaque, Phys addr)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
@@ -1070,7 +1070,7 @@ static uint32_t intel_hda_mmio_readb(void *opaque,
target_phys_addr_t addr)
return intel_hda_reg_read(d, reg, 0xff);
}
-static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t intel_hda_mmio_readw(void *opaque, Phys addr)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
@@ -1078,7 +1078,7 @@ static uint32_t intel_hda_mmio_readw(void *opaque,
target_phys_addr_t addr)
return intel_hda_reg_read(d, reg, 0xffff);
}
-static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t intel_hda_mmio_readl(void *opaque, Phys addr)
{
IntelHDAState *d = opaque;
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
diff --git a/hw/ioapic.c b/hw/ioapic.c
index 27b07c6..3cbfc3a 100644
--- a/hw/ioapic.c
+++ b/hw/ioapic.c
@@ -197,7 +197,7 @@ void ioapic_eoi_broadcast(int vector)
}
static uint64_t
-ioapic_mem_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+ioapic_mem_read(void *opaque, Phys addr, unsigned int size)
{
IOAPICState *s = opaque;
int index;
@@ -239,7 +239,7 @@ void ioapic_eoi_broadcast(int vector)
}
static void
-ioapic_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
+ioapic_mem_write(void *opaque, Phys addr, uint64_t val,
unsigned int size)
{
IOAPICState *s = opaque;
diff --git a/hw/isa-bus.c b/hw/isa-bus.c
index 5af790b..429a4ec 100644
--- a/hw/isa-bus.c
+++ b/hw/isa-bus.c
@@ -23,7 +23,7 @@
#include "exec-memory.h"
static ISABus *isabus;
-target_phys_addr_t isa_mem_base = 0;
+Phys isa_mem_base = 0;
static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent);
static char *isabus_get_fw_dev_path(DeviceState *dev);
diff --git a/hw/isa.h b/hw/isa.h
index b11a0be..61e53f6 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -71,10 +71,10 @@ void isa_register_portio_list(ISADevice *dev, uint16_t
start,
const MemoryRegionPortio *portio,
void *opaque, const char *name);
-extern target_phys_addr_t isa_mem_base;
+extern Phys isa_mem_base;
-void isa_mmio_setup(MemoryRegion *mr, target_phys_addr_t size);
-void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
+void isa_mmio_setup(MemoryRegion *mr, Phys size);
+void isa_mmio_init(Phys base, Phys size);
/* dma.c */
int DMA_get_channel_mode (int nchan);
diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c
index fd755ab..9bfc14a 100644
--- a/hw/isa_mmio.c
+++ b/hw/isa_mmio.c
@@ -26,35 +26,35 @@
#include "isa.h"
#include "exec-memory.h"
-static void isa_mmio_writeb (void *opaque, target_phys_addr_t addr,
+static void isa_mmio_writeb (void *opaque, Phys addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
-static void isa_mmio_writew(void *opaque, target_phys_addr_t addr,
+static void isa_mmio_writew(void *opaque, Phys addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, val);
}
-static void isa_mmio_writel(void *opaque, target_phys_addr_t addr,
+static void isa_mmio_writel(void *opaque, Phys addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, val);
}
-static uint32_t isa_mmio_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readb (void *opaque, Phys addr)
{
return cpu_inb(addr & IOPORTS_MASK);
}
-static uint32_t isa_mmio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readw(void *opaque, Phys addr)
{
return cpu_inw(addr & IOPORTS_MASK);
}
-static uint32_t isa_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t isa_mmio_readl(void *opaque, Phys addr)
{
return cpu_inl(addr & IOPORTS_MASK);
}
@@ -67,12 +67,12 @@ static uint32_t isa_mmio_readl(void *opaque,
target_phys_addr_t addr)
.endianness = DEVICE_LITTLE_ENDIAN,
};
-void isa_mmio_setup(MemoryRegion *mr, target_phys_addr_t size)
+void isa_mmio_setup(MemoryRegion *mr, Phys size)
{
memory_region_init_io(mr, &isa_mmio_ops, NULL, "isa-mmio", size);
}
-void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size)
+void isa_mmio_init(Phys base, Phys size)
{
MemoryRegion *mr = g_malloc(sizeof(*mr));
diff --git a/hw/ivshmem.c b/hw/ivshmem.c
index 1aa9e3b..ddf7e4e 100644
--- a/hw/ivshmem.c
+++ b/hw/ivshmem.c
@@ -160,7 +160,7 @@ static uint32_t ivshmem_IntrStatus_read(IVShmemState *s)
return ret;
}
-static void ivshmem_io_write(void *opaque, target_phys_addr_t addr,
+static void ivshmem_io_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
IVShmemState *s = opaque;
@@ -204,7 +204,7 @@ static void ivshmem_io_write(void *opaque,
target_phys_addr_t addr,
}
}
-static uint64_t ivshmem_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ivshmem_io_read(void *opaque, Phys addr,
unsigned size)
{
diff --git a/hw/jazz_led.c b/hw/jazz_led.c
index f8a2182..590464f 100644
--- a/hw/jazz_led.c
+++ b/hw/jazz_led.c
@@ -49,7 +49,7 @@
screen_state_t state;
} LedState;
-static uint32_t led_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t led_readb(void *opaque, Phys addr)
{
LedState *s = opaque;
uint32_t val;
@@ -68,7 +68,7 @@ static uint32_t led_readb(void *opaque, target_phys_addr_t
addr)
return val;
}
-static uint32_t led_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t led_readw(void *opaque, Phys addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -81,7 +81,7 @@ static uint32_t led_readw(void *opaque, target_phys_addr_t
addr)
return v;
}
-static uint32_t led_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t led_readl(void *opaque, Phys addr)
{
uint32_t v;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -98,7 +98,7 @@ static uint32_t led_readl(void *opaque, target_phys_addr_t
addr)
return v;
}
-static void led_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void led_writeb(void *opaque, Phys addr, uint32_t val)
{
LedState *s = opaque;
@@ -115,7 +115,7 @@ static void led_writeb(void *opaque, target_phys_addr_t
addr, uint32_t val)
}
}
-static void led_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void led_writew(void *opaque, Phys addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
led_writeb(opaque, addr, (val >> 8) & 0xff);
@@ -126,7 +126,7 @@ static void led_writew(void *opaque, target_phys_addr_t
addr, uint32_t val)
#endif
}
-static void led_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void led_writel(void *opaque, Phys addr, uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
led_writeb(opaque, addr, (val >> 24) & 0xff);
@@ -304,7 +304,7 @@ static void jazz_led_text_update(void *opaque, console_ch_t
*chardata)
dpy_update(s->ds, 0, 0, 2, 1);
}
-void jazz_led_init(MemoryRegion *address_space, target_phys_addr_t base)
+void jazz_led_init(MemoryRegion *address_space, Phys base)
{
LedState *s;
diff --git a/hw/lan9118.c b/hw/lan9118.c
index 7e64c5d..19a1dbc 100644
--- a/hw/lan9118.c
+++ b/hw/lan9118.c
@@ -895,7 +895,7 @@ static void lan9118_tick(void *opaque)
lan9118_update(s);
}
-static void lan9118_writel(void *opaque, target_phys_addr_t offset,
+static void lan9118_writel(void *opaque, Phys offset,
uint64_t val, unsigned size)
{
lan9118_state *s = (lan9118_state *)opaque;
@@ -1029,7 +1029,7 @@ static void lan9118_writel(void *opaque,
target_phys_addr_t offset,
lan9118_update(s);
}
-static uint64_t lan9118_readl(void *opaque, target_phys_addr_t offset,
+static uint64_t lan9118_readl(void *opaque, Phys offset,
unsigned size)
{
lan9118_state *s = (lan9118_state *)opaque;
diff --git a/hw/lance.c b/hw/lance.c
index 7164700..a4608ec 100644
--- a/hw/lance.c
+++ b/hw/lance.c
@@ -55,7 +55,7 @@ static void parent_lance_reset(void *opaque, int irq, int
level)
pcnet_h_reset(&d->state);
}
-static void lance_mem_write(void *opaque, target_phys_addr_t addr,
+static void lance_mem_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
SysBusPCNetState *d = opaque;
@@ -64,7 +64,7 @@ static void lance_mem_write(void *opaque, target_phys_addr_t
addr,
pcnet_ioport_writew(&d->state, addr, val & 0xffff);
}
-static uint64_t lance_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lance_mem_read(void *opaque, Phys addr,
unsigned size)
{
SysBusPCNetState *d = opaque;
diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c
index 3cdf120..4ff93f6 100644
--- a/hw/lm32_boards.c
+++ b/hw/lm32_boards.c
@@ -32,12 +32,12 @@
typedef struct {
CPUState *env;
- target_phys_addr_t bootstrap_pc;
- target_phys_addr_t flash_base;
- target_phys_addr_t hwsetup_base;
- target_phys_addr_t initrd_base;
+ Phys bootstrap_pc;
+ Phys flash_base;
+ Phys hwsetup_base;
+ Phys initrd_base;
size_t initrd_size;
- target_phys_addr_t cmdline_base;
+ Phys cmdline_base;
} ResetInfo;
static void cpu_irq_handler(void *opaque, int irq, int level)
@@ -84,14 +84,14 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
int i;
/* memory map */
- target_phys_addr_t flash_base = 0x04000000;
+ Phys flash_base = 0x04000000;
size_t flash_sector_size = 256 * 1024;
size_t flash_size = 32 * 1024 * 1024;
- target_phys_addr_t ram_base = 0x08000000;
+ Phys ram_base = 0x08000000;
size_t ram_size = 64 * 1024 * 1024;
- target_phys_addr_t timer0_base = 0x80002000;
- target_phys_addr_t uart0_base = 0x80006000;
- target_phys_addr_t timer1_base = 0x8000a000;
+ Phys timer0_base = 0x80002000;
+ Phys uart0_base = 0x80006000;
+ Phys timer1_base = 0x8000a000;
int uart0_irq = 0;
int timer0_irq = 1;
int timer1_irq = 3;
@@ -173,22 +173,22 @@ static void lm32_uclinux_init(ram_addr_t
ram_size_not_used,
int i;
/* memory map */
- target_phys_addr_t flash_base = 0x04000000;
+ Phys flash_base = 0x04000000;
size_t flash_sector_size = 256 * 1024;
size_t flash_size = 32 * 1024 * 1024;
- target_phys_addr_t ram_base = 0x08000000;
+ Phys ram_base = 0x08000000;
size_t ram_size = 64 * 1024 * 1024;
- target_phys_addr_t uart0_base = 0x80000000;
- target_phys_addr_t timer0_base = 0x80002000;
- target_phys_addr_t timer1_base = 0x80010000;
- target_phys_addr_t timer2_base = 0x80012000;
+ Phys uart0_base = 0x80000000;
+ Phys timer0_base = 0x80002000;
+ Phys timer1_base = 0x80010000;
+ Phys timer2_base = 0x80012000;
int uart0_irq = 0;
int timer0_irq = 1;
int timer1_irq = 20;
int timer2_irq = 21;
- target_phys_addr_t hwsetup_base = 0x0bffe000;
- target_phys_addr_t cmdline_base = 0x0bfff000;
- target_phys_addr_t initrd_base = 0x08400000;
+ Phys hwsetup_base = 0x0bffe000;
+ Phys cmdline_base = 0x0bfff000;
+ Phys initrd_base = 0x08400000;
size_t initrd_max = 0x01000000;
reset_info = g_malloc0(sizeof(ResetInfo));
diff --git a/hw/lm32_hwsetup.h b/hw/lm32_hwsetup.h
index 8fc285e..f82b43c 100644
--- a/hw/lm32_hwsetup.h
+++ b/hw/lm32_hwsetup.h
@@ -71,7 +71,7 @@ static inline void hwsetup_free(HWSetup *hw)
}
static inline void hwsetup_create_rom(HWSetup *hw,
- target_phys_addr_t base)
+ Phys base)
{
rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, base);
}
diff --git a/hw/lm32_sys.c b/hw/lm32_sys.c
index 83974ee..d7336ea 100644
--- a/hw/lm32_sys.c
+++ b/hw/lm32_sys.c
@@ -61,7 +61,7 @@ static void copy_testname(LM32SysState *s)
s->testname[MAX_TESTNAME_LEN - 1] = '\0';
}
-static void sys_write(void *opaque, target_phys_addr_t addr,
+static void sys_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
LM32SysState *s = opaque;
@@ -91,7 +91,7 @@ static void sys_write(void *opaque, target_phys_addr_t addr,
}
}
-static bool sys_ops_accepts(void *opaque, target_phys_addr_t addr,
+static bool sys_ops_accepts(void *opaque, Phys addr,
unsigned size, bool is_write)
{
return is_write && size == 4;
diff --git a/hw/lm32_timer.c b/hw/lm32_timer.c
index 445847f..3ee6429 100644
--- a/hw/lm32_timer.c
+++ b/hw/lm32_timer.c
@@ -71,7 +71,7 @@ static void timer_update_irq(LM32TimerState *s)
qemu_set_irq(s->irq, state);
}
-static uint64_t timer_read(void *opaque, target_phys_addr_t addr, unsigned
size)
+static uint64_t timer_read(void *opaque, Phys addr, unsigned size)
{
LM32TimerState *s = opaque;
uint32_t r = 0;
@@ -96,7 +96,7 @@ static uint64_t timer_read(void *opaque, target_phys_addr_t
addr, unsigned size)
return r;
}
-static void timer_write(void *opaque, target_phys_addr_t addr,
+static void timer_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
LM32TimerState *s = opaque;
diff --git a/hw/lm32_uart.c b/hw/lm32_uart.c
index d013abd..25f547b 100644
--- a/hw/lm32_uart.c
+++ b/hw/lm32_uart.c
@@ -125,7 +125,7 @@ static void uart_update_irq(LM32UartState *s)
qemu_set_irq(s->irq, irq);
}
-static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t uart_read(void *opaque, Phys addr,
unsigned size)
{
LM32UartState *s = opaque;
@@ -160,7 +160,7 @@ static uint64_t uart_read(void *opaque, target_phys_addr_t
addr,
return r;
}
-static void uart_write(void *opaque, target_phys_addr_t addr,
+static void uart_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
LM32UartState *s = opaque;
diff --git a/hw/lm4549.c b/hw/lm4549.c
index 80b3ec4..7b613d0 100644
--- a/hw/lm4549.c
+++ b/hw/lm4549.c
@@ -150,7 +150,7 @@ static void lm4549_audio_out_callback(void *opaque, int
free)
}
}
-uint32_t lm4549_read(lm4549_state *s, target_phys_addr_t offset)
+uint32_t lm4549_read(lm4549_state *s, Phys offset)
{
uint16_t *regfile = s->regfile;
uint32_t value = 0;
@@ -165,7 +165,7 @@ uint32_t lm4549_read(lm4549_state *s, target_phys_addr_t
offset)
}
void lm4549_write(lm4549_state *s,
- target_phys_addr_t offset, uint32_t value)
+ Phys offset, uint32_t value)
{
uint16_t *regfile = s->regfile;
diff --git a/hw/lm4549.h b/hw/lm4549.h
index 5948780..0916024 100644
--- a/hw/lm4549.h
+++ b/hw/lm4549.h
@@ -36,8 +36,8 @@ extern const VMStateDescription vmstate_lm4549_state;
void lm4549_init(lm4549_state *s, lm4549_callback data_req, void *opaque);
-uint32_t lm4549_read(lm4549_state *s, target_phys_addr_t offset);
-void lm4549_write(lm4549_state *s, target_phys_addr_t offset, uint32_t value);
+uint32_t lm4549_read(lm4549_state *s, Phys offset);
+void lm4549_write(lm4549_state *s, Phys offset, uint32_t value);
uint32_t lm4549_write_samples(lm4549_state *s, uint32_t left, uint32_t right);
#endif /* #ifndef HW_LM4549_H */
diff --git a/hw/loader.c b/hw/loader.c
index 446b628..5dab890 100644
--- a/hw/loader.c
+++ b/hw/loader.c
@@ -88,7 +88,7 @@ int load_image(const char *filename, uint8_t *addr)
/* read()-like version */
ssize_t read_targphys(const char *name,
- int fd, target_phys_addr_t dst_addr, size_t nbytes)
+ int fd, Phys dst_addr, size_t nbytes)
{
uint8_t *buf;
ssize_t did;
@@ -103,7 +103,7 @@ ssize_t read_targphys(const char *name,
/* return the size or -1 if error */
int load_image_targphys(const char *filename,
- target_phys_addr_t addr, int max_sz)
+ Phys addr, int max_sz)
{
int size;
@@ -113,7 +113,7 @@ int load_image_targphys(const char *filename,
return size;
}
-void pstrcpy_targphys(const char *name, target_phys_addr_t dest, int buf_size,
+void pstrcpy_targphys(const char *name, Phys dest, int buf_size,
const char *source)
{
const char *nulp;
@@ -175,8 +175,8 @@ static void bswap_ahdr(struct exec *e)
: (_N_SEGMENT_ROUND (_N_TXTENDADDR(x, target_page_size),
target_page_size)))
-int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
- int bswap_needed, target_phys_addr_t target_page_size)
+int load_aout(const char *filename, Phys addr, int max_sz,
+ int bswap_needed, Phys target_page_size)
{
int fd;
ssize_t size, ret;
@@ -430,8 +430,8 @@ static ssize_t gunzip(void *dst, size_t dstlen, uint8_t
*src,
}
/* Load a U-Boot image. */
-int load_uimage(const char *filename, target_phys_addr_t *ep,
- target_phys_addr_t *loadaddr, int *is_linux)
+int load_uimage(const char *filename, Phys *ep,
+ Phys *loadaddr, int *is_linux)
{
int fd;
int size;
@@ -535,7 +535,7 @@ struct Rom {
char *fw_dir;
char *fw_file;
- target_phys_addr_t addr;
+ Phys addr;
QTAILQ_ENTRY(Rom) next;
};
@@ -561,7 +561,7 @@ static void rom_insert(Rom *rom)
}
int rom_add_file(const char *file, const char *fw_dir,
- target_phys_addr_t addr, int32_t bootindex)
+ Phys addr, int32_t bootindex)
{
Rom *rom;
int rc, fd = -1;
@@ -629,7 +629,7 @@ int rom_add_file(const char *file, const char *fw_dir,
}
int rom_add_blob(const char *name, const void *blob, size_t len,
- target_phys_addr_t addr)
+ Phys addr)
{
Rom *rom;
@@ -675,7 +675,7 @@ static void rom_reset(void *unused)
int rom_load_all(void)
{
- target_phys_addr_t addr = 0;
+ Phys addr = 0;
MemoryRegionSection section;
Rom *rom;
@@ -705,7 +705,7 @@ void rom_set_fw(void *f)
fw_cfg = f;
}
-static Rom *find_rom(target_phys_addr_t addr)
+static Rom *find_rom(Phys addr)
{
Rom *rom;
@@ -729,9 +729,9 @@ void rom_set_fw(void *f)
* a ROM between addr and addr + size is copied. Note that this can involve
* multiple ROMs, which need not start at addr and need not end at addr + size.
*/
-int rom_copy(uint8_t *dest, target_phys_addr_t addr, size_t size)
+int rom_copy(uint8_t *dest, Phys addr, size_t size)
{
- target_phys_addr_t end = addr + size;
+ Phys end = addr + size;
uint8_t *s, *d = dest;
size_t l = 0;
Rom *rom;
@@ -764,7 +764,7 @@ int rom_copy(uint8_t *dest, target_phys_addr_t addr, size_t
size)
return (d + l) - dest;
}
-void *rom_ptr(target_phys_addr_t addr)
+void *rom_ptr(Phys addr)
{
Rom *rom;
diff --git a/hw/loader.h b/hw/loader.h
index fbcaba9..ded61c4 100644
--- a/hw/loader.h
+++ b/hw/loader.h
@@ -4,31 +4,31 @@
/* loader.c */
int get_image_size(const char *filename);
int load_image(const char *filename, uint8_t *addr); /* deprecated */
-int load_image_targphys(const char *filename, target_phys_addr_t, int max_sz);
+int load_image_targphys(const char *filename, Phys, int max_sz);
int load_elf(const char *filename, uint64_t (*translate_fn)(void *, uint64_t),
void *translate_opaque, uint64_t *pentry, uint64_t *lowaddr,
uint64_t *highaddr, int big_endian, int elf_machine,
int clear_lsb);
-int load_aout(const char *filename, target_phys_addr_t addr, int max_sz,
- int bswap_needed, target_phys_addr_t target_page_size);
-int load_uimage(const char *filename, target_phys_addr_t *ep,
- target_phys_addr_t *loadaddr, int *is_linux);
+int load_aout(const char *filename, Phys addr, int max_sz,
+ int bswap_needed, Phys target_page_size);
+int load_uimage(const char *filename, Phys *ep,
+ Phys *loadaddr, int *is_linux);
ssize_t read_targphys(const char *name,
- int fd, target_phys_addr_t dst_addr, size_t nbytes);
+ int fd, Phys dst_addr, size_t nbytes);
void pstrcpy_targphys(const char *name,
- target_phys_addr_t dest, int buf_size,
+ Phys dest, int buf_size,
const char *source);
int rom_add_file(const char *file, const char *fw_dir,
- target_phys_addr_t addr, int32_t bootindex);
+ Phys addr, int32_t bootindex);
int rom_add_blob(const char *name, const void *blob, size_t len,
- target_phys_addr_t addr);
+ Phys addr);
int rom_load_all(void);
void rom_set_fw(void *f);
-int rom_copy(uint8_t *dest, target_phys_addr_t addr, size_t size);
-void *rom_ptr(target_phys_addr_t addr);
+int rom_copy(uint8_t *dest, Phys addr, size_t size);
+void *rom_ptr(Phys addr);
void do_info_roms(Monitor *mon);
#define rom_add_file_fixed(_f, _a, _i) \
diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c
index 0d3a101..6fda29d 100644
--- a/hw/lsi53c895a.c
+++ b/hw/lsi53c895a.c
@@ -1885,7 +1885,7 @@ static void lsi_reg_writeb(LSIState *s, int offset,
uint8_t val)
#undef CASE_SET_REG32
}
-static void lsi_mmio_write(void *opaque, target_phys_addr_t addr,
+static void lsi_mmio_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
LSIState *s = opaque;
@@ -1893,7 +1893,7 @@ static void lsi_mmio_write(void *opaque,
target_phys_addr_t addr,
lsi_reg_writeb(s, addr & 0xff, val);
}
-static uint64_t lsi_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lsi_mmio_read(void *opaque, Phys addr,
unsigned size)
{
LSIState *s = opaque;
@@ -1911,7 +1911,7 @@ static uint64_t lsi_mmio_read(void *opaque,
target_phys_addr_t addr,
},
};
-static void lsi_ram_write(void *opaque, target_phys_addr_t addr,
+static void lsi_ram_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
LSIState *s = opaque;
@@ -1927,7 +1927,7 @@ static void lsi_ram_write(void *opaque,
target_phys_addr_t addr,
s->script_ram[addr >> 2] = newval;
}
-static uint64_t lsi_ram_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lsi_ram_read(void *opaque, Phys addr,
unsigned size)
{
LSIState *s = opaque;
@@ -1946,14 +1946,14 @@ static uint64_t lsi_ram_read(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t lsi_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lsi_io_read(void *opaque, Phys addr,
unsigned size)
{
LSIState *s = opaque;
return lsi_reg_readb(s, addr & 0xff);
}
-static void lsi_io_write(void *opaque, target_phys_addr_t addr,
+static void lsi_io_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
LSIState *s = opaque;
diff --git a/hw/m48t59.c b/hw/m48t59.c
index c043996..b29db26 100644
--- a/hw/m48t59.c
+++ b/hw/m48t59.c
@@ -518,14 +518,14 @@ static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
return retval;
}
-static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t
value)
+static void nvram_writeb (void *opaque, Phys addr, uint32_t value)
{
M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr, value & 0xff);
}
-static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t
value)
+static void nvram_writew (void *opaque, Phys addr, uint32_t value)
{
M48t59State *NVRAM = opaque;
@@ -533,7 +533,7 @@ static void nvram_writew (void *opaque, target_phys_addr_t
addr, uint32_t value)
m48t59_write(NVRAM, addr + 1, value & 0xff);
}
-static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t
value)
+static void nvram_writel (void *opaque, Phys addr, uint32_t value)
{
M48t59State *NVRAM = opaque;
@@ -543,7 +543,7 @@ static void nvram_writel (void *opaque, target_phys_addr_t
addr, uint32_t value)
m48t59_write(NVRAM, addr + 3, value & 0xff);
}
-static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t nvram_readb (void *opaque, Phys addr)
{
M48t59State *NVRAM = opaque;
uint32_t retval;
@@ -552,7 +552,7 @@ static uint32_t nvram_readb (void *opaque,
target_phys_addr_t addr)
return retval;
}
-static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t nvram_readw (void *opaque, Phys addr)
{
M48t59State *NVRAM = opaque;
uint32_t retval;
@@ -562,7 +562,7 @@ static uint32_t nvram_readw (void *opaque,
target_phys_addr_t addr)
return retval;
}
-static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t nvram_readl (void *opaque, Phys addr)
{
M48t59State *NVRAM = opaque;
uint32_t retval;
@@ -632,7 +632,7 @@ static void m48t59_reset_sysbus(DeviceState *d)
};
/* Initialisation routine */
-M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
+M48t59State *m48t59_init(qemu_irq IRQ, Phys mem_base,
uint32_t io_base, uint16_t size, int type)
{
DeviceState *dev;
diff --git a/hw/mac_dbdma.c b/hw/mac_dbdma.c
index 1791ec1..271f312 100644
--- a/hw/mac_dbdma.c
+++ b/hw/mac_dbdma.c
@@ -699,7 +699,7 @@ void DBDMA_register_channel(void *dbdma, int nchan,
qemu_irq irq,
ch->flush(&ch->io);
}
-static void dbdma_write(void *opaque, target_phys_addr_t addr,
+static void dbdma_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
int channel = addr >> DBDMA_CHANNEL_SHIFT;
@@ -749,7 +749,7 @@ static void dbdma_write(void *opaque, target_phys_addr_t
addr,
}
}
-static uint64_t dbdma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t dbdma_read(void *opaque, Phys addr,
unsigned size)
{
uint32_t value;
diff --git a/hw/mac_dbdma.h b/hw/mac_dbdma.h
index 6d1abe6..d050014 100644
--- a/hw/mac_dbdma.h
+++ b/hw/mac_dbdma.h
@@ -30,7 +30,7 @@ typedef void (*DBDMA_end)(DBDMA_io *io);
struct DBDMA_io {
void *opaque;
void *channel;
- target_phys_addr_t addr;
+ Phys addr;
int len;
int is_last;
int is_dma_out;
diff --git a/hw/mac_nvram.c b/hw/mac_nvram.c
index ed0a2b7..6e06399 100644
--- a/hw/mac_nvram.c
+++ b/hw/mac_nvram.c
@@ -71,7 +71,7 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t
val)
}
/* macio style NVRAM device */
-static void macio_nvram_writeb(void *opaque, target_phys_addr_t addr,
+static void macio_nvram_writeb(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
MacIONVRAMState *s = opaque;
@@ -81,7 +81,7 @@ static void macio_nvram_writeb(void *opaque,
target_phys_addr_t addr,
NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
}
-static uint64_t macio_nvram_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t macio_nvram_readb(void *opaque, Phys addr,
unsigned size)
{
MacIONVRAMState *s = opaque;
@@ -116,7 +116,7 @@ static void macio_nvram_reset(void *opaque)
{
}
-MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,
+MacIONVRAMState *macio_nvram_init (Phys size,
unsigned int it_shift)
{
MacIONVRAMState *s;
@@ -135,7 +135,7 @@ static void macio_nvram_reset(void *opaque)
}
void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar,
- target_phys_addr_t mem_base)
+ Phys mem_base)
{
memory_region_add_subregion(bar, mem_base, &s->mem);
}
diff --git a/hw/mainstone.c b/hw/mainstone.c
index c914a4e..ecfae96 100644
--- a/hw/mainstone.c
+++ b/hw/mainstone.c
@@ -98,7 +98,7 @@ static void mainstone_common_init(MemoryRegion
*address_space_mem,
const char *cpu_model, enum mainstone_model_e model, int
arm_id)
{
uint32_t sector_len = 256 * 1024;
- target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
+ Phys mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
PXA2xxState *cpu;
DeviceState *mst_irq;
DriveInfo *dinfo;
diff --git a/hw/marvell_88w8618_audio.c b/hw/marvell_88w8618_audio.c
index 855b792..768b7eb 100644
--- a/hw/marvell_88w8618_audio.c
+++ b/hw/marvell_88w8618_audio.c
@@ -135,7 +135,7 @@ static void
mv88w8618_audio_clock_update(mv88w8618_audio_state *s)
wm8750_set_bclk_in(s->wm, rate);
}
-static uint64_t mv88w8618_audio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_audio_read(void *opaque, Phys offset,
unsigned size)
{
mv88w8618_audio_state *s = opaque;
@@ -161,7 +161,7 @@ static uint64_t mv88w8618_audio_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void mv88w8618_audio_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_audio_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
mv88w8618_audio_state *s = opaque;
diff --git a/hw/mcf.h b/hw/mcf.h
index baa790b..62949eb 100644
--- a/hw/mcf.h
+++ b/hw/mcf.h
@@ -5,23 +5,23 @@
struct MemoryRegion;
/* mcf_uart.c */
-uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
+uint64_t mcf_uart_read(void *opaque, Phys addr,
unsigned size);
-void mcf_uart_write(void *opaque, target_phys_addr_t addr,
+void mcf_uart_write(void *opaque, Phys addr,
uint64_t val, unsigned size);
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
void mcf_uart_mm_init(struct MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq, CharDriverState *chr);
/* mcf_intc.c */
qemu_irq *mcf_intc_init(struct MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
CPUState *env);
/* mcf_fec.c */
void mcf_fec_init(struct MemoryRegion *sysmem, NICInfo *nd,
- target_phys_addr_t base, qemu_irq *irq);
+ Phys base, qemu_irq *irq);
/* mcf5206.c */
qemu_irq *mcf5206_init(struct MemoryRegion *sysmem,
diff --git a/hw/mcf5206.c b/hw/mcf5206.c
index 7b6d501..9e87701 100644
--- a/hw/mcf5206.c
+++ b/hw/mcf5206.c
@@ -370,10 +370,10 @@ static void m5206_mbar_write(m5206_mbar_state *s,
uint32_t offset,
/* 1c0-200 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
};
-static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset);
-static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset);
+static uint32_t m5206_mbar_readw(void *opaque, Phys offset);
+static uint32_t m5206_mbar_readl(void *opaque, Phys offset);
-static uint32_t m5206_mbar_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t m5206_mbar_readb(void *opaque, Phys offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
offset &= 0x3ff;
@@ -391,7 +391,7 @@ static uint32_t m5206_mbar_readb(void *opaque,
target_phys_addr_t offset)
return m5206_mbar_read(s, offset, 1);
}
-static uint32_t m5206_mbar_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t m5206_mbar_readw(void *opaque, Phys offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
int width;
@@ -415,7 +415,7 @@ static uint32_t m5206_mbar_readw(void *opaque,
target_phys_addr_t offset)
return m5206_mbar_read(s, offset, 2);
}
-static uint32_t m5206_mbar_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t m5206_mbar_readl(void *opaque, Phys offset)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
int width;
@@ -433,12 +433,12 @@ static uint32_t m5206_mbar_readl(void *opaque,
target_phys_addr_t offset)
return m5206_mbar_read(s, offset, 4);
}
-static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writew(void *opaque, Phys offset,
uint32_t value);
-static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writel(void *opaque, Phys offset,
uint32_t value);
-static void m5206_mbar_writeb(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writeb(void *opaque, Phys offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
@@ -462,7 +462,7 @@ static void m5206_mbar_writeb(void *opaque,
target_phys_addr_t offset,
m5206_mbar_write(s, offset, value, 1);
}
-static void m5206_mbar_writew(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writew(void *opaque, Phys offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
@@ -490,7 +490,7 @@ static void m5206_mbar_writew(void *opaque,
target_phys_addr_t offset,
m5206_mbar_write(s, offset, value, 2);
}
-static void m5206_mbar_writel(void *opaque, target_phys_addr_t offset,
+static void m5206_mbar_writel(void *opaque, Phys offset,
uint32_t value)
{
m5206_mbar_state *s = (m5206_mbar_state *)opaque;
diff --git a/hw/mcf5208.c b/hw/mcf5208.c
index 3b0636d..463d8c2 100644
--- a/hw/mcf5208.c
+++ b/hw/mcf5208.c
@@ -44,7 +44,7 @@ static void m5208_timer_update(m5208_timer_state *s)
qemu_irq_lower(s->irq);
}
-static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
+static void m5208_timer_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
@@ -106,7 +106,7 @@ static void m5208_timer_trigger(void *opaque)
m5208_timer_update(s);
}
-static uint64_t m5208_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t m5208_timer_read(void *opaque, Phys addr,
unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
@@ -129,7 +129,7 @@ static uint64_t m5208_timer_read(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t m5208_sys_read(void *opaque, target_phys_addr_t addr,
+static uint64_t m5208_sys_read(void *opaque, Phys addr,
unsigned size)
{
switch (addr) {
@@ -151,7 +151,7 @@ static uint64_t m5208_sys_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
+static void m5208_sys_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
@@ -194,7 +194,7 @@ static void mcf5208evb_init(ram_addr_t ram_size,
CPUState *env;
int kernel_size;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ Phys entry;
qemu_irq *pic;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
diff --git a/hw/mcf_fec.c b/hw/mcf_fec.c
index ae37bef..2118d44 100644
--- a/hw/mcf_fec.c
+++ b/hw/mcf_fec.c
@@ -216,7 +216,7 @@ static void mcf_fec_reset(mcf_fec_state *s)
s->rfsr = 0x500;
}
-static uint64_t mcf_fec_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mcf_fec_read(void *opaque, Phys addr,
unsigned size)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
@@ -254,7 +254,7 @@ static uint64_t mcf_fec_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void mcf_fec_write(void *opaque, target_phys_addr_t addr,
+static void mcf_fec_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
mcf_fec_state *s = (mcf_fec_state *)opaque;
@@ -458,7 +458,7 @@ static void mcf_fec_cleanup(VLANClientState *nc)
};
void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd,
- target_phys_addr_t base, qemu_irq *irq)
+ Phys base, qemu_irq *irq)
{
mcf_fec_state *s;
diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c
index 0b498dd..1544067 100644
--- a/hw/mcf_intc.c
+++ b/hw/mcf_intc.c
@@ -43,7 +43,7 @@ static void mcf_intc_update(mcf_intc_state *s)
m68k_set_irq_level(s->env, best_level, s->active_vector);
}
-static uint64_t mcf_intc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mcf_intc_read(void *opaque, Phys addr,
unsigned size)
{
int offset;
@@ -76,7 +76,7 @@ static uint64_t mcf_intc_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void mcf_intc_write(void *opaque, target_phys_addr_t addr,
+static void mcf_intc_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
int offset;
@@ -138,7 +138,7 @@ static void mcf_intc_reset(mcf_intc_state *s)
};
qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
CPUState *env)
{
mcf_intc_state *s;
diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c
index ec6a87f..a9d04e5 100644
--- a/hw/mcf_uart.c
+++ b/hw/mcf_uart.c
@@ -66,7 +66,7 @@ static void mcf_uart_update(mcf_uart_state *s)
qemu_set_irq(s->irq, (s->isr & s->imr) != 0);
}
-uint64_t mcf_uart_read(void *opaque, target_phys_addr_t addr,
+uint64_t mcf_uart_read(void *opaque, Phys addr,
unsigned size)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
@@ -185,7 +185,7 @@ static void mcf_do_command(mcf_uart_state *s, uint8_t cmd)
}
}
-void mcf_uart_write(void *opaque, target_phys_addr_t addr,
+void mcf_uart_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
mcf_uart_state *s = (mcf_uart_state *)opaque;
@@ -294,7 +294,7 @@ static void mcf_uart_receive(void *opaque, const uint8_t
*buf, int size)
};
void mcf_uart_mm_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq,
CharDriverState *chr)
{
diff --git a/hw/milkymist-ac97.c b/hw/milkymist-ac97.c
index e824a49..d0c2b5a 100644
--- a/hw/milkymist-ac97.c
+++ b/hw/milkymist-ac97.c
@@ -83,7 +83,7 @@ static void update_voices(MilkymistAC97State *s)
}
}
-static uint64_t ac97_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ac97_read(void *opaque, Phys addr,
unsigned size)
{
MilkymistAC97State *s = opaque;
@@ -115,7 +115,7 @@ static uint64_t ac97_read(void *opaque, target_phys_addr_t
addr,
return r;
}
-static void ac97_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void ac97_write(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
MilkymistAC97State *s = opaque;
diff --git a/hw/milkymist-hpdmc.c b/hw/milkymist-hpdmc.c
index be575c9..63ad57a 100644
--- a/hw/milkymist-hpdmc.c
+++ b/hw/milkymist-hpdmc.c
@@ -48,7 +48,7 @@ struct MilkymistHpdmcState {
};
typedef struct MilkymistHpdmcState MilkymistHpdmcState;
-static uint64_t hpdmc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t hpdmc_read(void *opaque, Phys addr,
unsigned size)
{
MilkymistHpdmcState *s = opaque;
@@ -74,7 +74,7 @@ static uint64_t hpdmc_read(void *opaque, target_phys_addr_t
addr,
return r;
}
-static void hpdmc_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void hpdmc_write(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
MilkymistHpdmcState *s = opaque;
diff --git a/hw/milkymist-hw.h b/hw/milkymist-hw.h
index 9f358a7..d2914cd 100644
--- a/hw/milkymist-hw.h
+++ b/hw/milkymist-hw.h
@@ -4,7 +4,7 @@
#include "qdev.h"
#include "qdev-addr.h"
-static inline DeviceState *milkymist_uart_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_uart_create(Phys base,
qemu_irq irq)
{
DeviceState *dev;
@@ -17,7 +17,7 @@ static inline DeviceState
*milkymist_uart_create(target_phys_addr_t base,
return dev;
}
-static inline DeviceState *milkymist_hpdmc_create(target_phys_addr_t base)
+static inline DeviceState *milkymist_hpdmc_create(Phys base)
{
DeviceState *dev;
@@ -28,7 +28,7 @@ static inline DeviceState
*milkymist_hpdmc_create(target_phys_addr_t base)
return dev;
}
-static inline DeviceState *milkymist_memcard_create(target_phys_addr_t base)
+static inline DeviceState *milkymist_memcard_create(Phys base)
{
DeviceState *dev;
@@ -39,7 +39,7 @@ static inline DeviceState
*milkymist_memcard_create(target_phys_addr_t base)
return dev;
}
-static inline DeviceState *milkymist_vgafb_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_vgafb_create(Phys base,
uint32_t fb_offset, uint32_t fb_mask)
{
DeviceState *dev;
@@ -53,7 +53,7 @@ static inline DeviceState
*milkymist_vgafb_create(target_phys_addr_t base,
return dev;
}
-static inline DeviceState *milkymist_sysctl_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_sysctl_create(Phys base,
qemu_irq gpio_irq, qemu_irq timer0_irq, qemu_irq timer1_irq,
uint32_t freq_hz, uint32_t system_id, uint32_t capabilities,
uint32_t gpio_strappings)
@@ -74,7 +74,7 @@ static inline DeviceState
*milkymist_sysctl_create(target_phys_addr_t base,
return dev;
}
-static inline DeviceState *milkymist_pfpu_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_pfpu_create(Phys base,
qemu_irq irq)
{
DeviceState *dev;
@@ -97,7 +97,7 @@ static const int glx_fbconfig_attr[] = {
};
#endif
-static inline DeviceState *milkymist_tmu2_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_tmu2_create(Phys base,
qemu_irq irq)
{
#ifdef CONFIG_OPENGL
@@ -152,7 +152,7 @@ static inline DeviceState
*milkymist_tmu2_create(target_phys_addr_t base,
#endif
}
-static inline DeviceState *milkymist_ac97_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_ac97_create(Phys base,
qemu_irq crrequest_irq, qemu_irq crreply_irq, qemu_irq dmar_irq,
qemu_irq dmaw_irq)
{
@@ -169,7 +169,7 @@ static inline DeviceState
*milkymist_ac97_create(target_phys_addr_t base,
return dev;
}
-static inline DeviceState *milkymist_minimac_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_minimac_create(Phys base,
qemu_irq rx_irq, qemu_irq tx_irq)
{
DeviceState *dev;
@@ -185,8 +185,8 @@ static inline DeviceState
*milkymist_minimac_create(target_phys_addr_t base,
return dev;
}
-static inline DeviceState *milkymist_minimac2_create(target_phys_addr_t base,
- target_phys_addr_t buffers_base, qemu_irq rx_irq, qemu_irq tx_irq)
+static inline DeviceState *milkymist_minimac2_create(Phys base,
+ Phys buffers_base, qemu_irq rx_irq, qemu_irq tx_irq)
{
DeviceState *dev;
@@ -202,7 +202,7 @@ static inline DeviceState
*milkymist_minimac2_create(target_phys_addr_t base,
return dev;
}
-static inline DeviceState *milkymist_softusb_create(target_phys_addr_t base,
+static inline DeviceState *milkymist_softusb_create(Phys base,
qemu_irq irq, uint32_t pmem_base, uint32_t pmem_size,
uint32_t dmem_base, uint32_t dmem_size)
{
diff --git a/hw/milkymist-memcard.c b/hw/milkymist-memcard.c
index 865a46c..bbb34e2 100644
--- a/hw/milkymist-memcard.c
+++ b/hw/milkymist-memcard.c
@@ -117,7 +117,7 @@ static void memcard_sd_command(MilkymistMemcardState *s)
}
}
-static uint64_t memcard_read(void *opaque, target_phys_addr_t addr,
+static uint64_t memcard_read(void *opaque, Phys addr,
unsigned size)
{
MilkymistMemcardState *s = opaque;
@@ -166,7 +166,7 @@ static uint64_t memcard_read(void *opaque,
target_phys_addr_t addr,
return r;
}
-static void memcard_write(void *opaque, target_phys_addr_t addr, uint64_t
value,
+static void memcard_write(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
MilkymistMemcardState *s = opaque;
diff --git a/hw/milkymist-minimac2.c b/hw/milkymist-minimac2.c
index 7006d29..5bdafa6 100644
--- a/hw/milkymist-minimac2.c
+++ b/hw/milkymist-minimac2.c
@@ -96,7 +96,7 @@ struct MilkymistMinimac2State {
NICState *nic;
NICConf conf;
char *phy_model;
- target_phys_addr_t buffers_base;
+ Phys buffers_base;
MemoryRegion buffers;
MemoryRegion regs_region;
@@ -323,7 +323,7 @@ static ssize_t minimac2_rx(VLANClientState *nc, const
uint8_t *buf, size_t size)
}
static uint64_t
-minimac2_read(void *opaque, target_phys_addr_t addr, unsigned size)
+minimac2_read(void *opaque, Phys addr, unsigned size)
{
MilkymistMinimac2State *s = opaque;
uint32_t r = 0;
@@ -352,7 +352,7 @@ static ssize_t minimac2_rx(VLANClientState *nc, const
uint8_t *buf, size_t size)
}
static void
-minimac2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+minimac2_write(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
MilkymistMinimac2State *s = opaque;
diff --git a/hw/milkymist-pfpu.c b/hw/milkymist-pfpu.c
index dc92eb6..e279953 100644
--- a/hw/milkymist-pfpu.c
+++ b/hw/milkymist-pfpu.c
@@ -131,7 +131,7 @@ struct MilkymistPFPUState {
};
typedef struct MilkymistPFPUState MilkymistPFPUState;
-static inline target_phys_addr_t
+static inline Phys
get_dma_address(uint32_t base, uint32_t x, uint32_t y)
{
return base + 8 * (128 * y + x);
@@ -225,7 +225,7 @@ static int pfpu_decode_insn(MilkymistPFPUState *s)
{
uint32_t a = cpu_to_be32(s->gp_regs[reg_a]);
uint32_t b = cpu_to_be32(s->gp_regs[reg_b]);
- target_phys_addr_t dma_ptr =
+ Phys dma_ptr =
get_dma_address(s->regs[R_MESHBASE],
s->gp_regs[GPR_X], s->gp_regs[GPR_Y]);
cpu_physical_memory_write(dma_ptr, (uint8_t *)&a, 4);
@@ -380,7 +380,7 @@ static inline int get_microcode_address(MilkymistPFPUState
*s, uint32_t addr)
return (512 * s->regs[R_CODEPAGE]) + addr - MICROCODE_BEGIN;
}
-static uint64_t pfpu_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pfpu_read(void *opaque, Phys addr,
unsigned size)
{
MilkymistPFPUState *s = opaque;
@@ -420,7 +420,7 @@ static uint64_t pfpu_read(void *opaque, target_phys_addr_t
addr,
return r;
}
-static void pfpu_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void pfpu_write(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
MilkymistPFPUState *s = opaque;
diff --git a/hw/milkymist-softusb.c b/hw/milkymist-softusb.c
index 83bd1c4..9d9028d 100644
--- a/hw/milkymist-softusb.c
+++ b/hw/milkymist-softusb.c
@@ -71,7 +71,7 @@ struct MilkymistSoftUsbState {
};
typedef struct MilkymistSoftUsbState MilkymistSoftUsbState;
-static uint64_t softusb_read(void *opaque, target_phys_addr_t addr,
+static uint64_t softusb_read(void *opaque, Phys addr,
unsigned size)
{
MilkymistSoftUsbState *s = opaque;
@@ -95,7 +95,7 @@ static uint64_t softusb_read(void *opaque, target_phys_addr_t
addr,
}
static void
-softusb_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+softusb_write(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
MilkymistSoftUsbState *s = opaque;
diff --git a/hw/milkymist-sysctl.c b/hw/milkymist-sysctl.c
index 6326b70..13db66e 100644
--- a/hw/milkymist-sysctl.c
+++ b/hw/milkymist-sysctl.c
@@ -89,7 +89,7 @@ static void sysctl_icap_write(MilkymistSysctlState *s,
uint32_t value)
}
}
-static uint64_t sysctl_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sysctl_read(void *opaque, Phys addr,
unsigned size)
{
MilkymistSysctlState *s = opaque;
@@ -131,7 +131,7 @@ static uint64_t sysctl_read(void *opaque,
target_phys_addr_t addr,
return r;
}
-static void sysctl_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void sysctl_write(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
MilkymistSysctlState *s = opaque;
diff --git a/hw/milkymist-tmu2.c b/hw/milkymist-tmu2.c
index 20110e5..ecddb84 100644
--- a/hw/milkymist-tmu2.c
+++ b/hw/milkymist-tmu2.c
@@ -182,9 +182,9 @@ static void tmu2_start(MilkymistTMU2State *s)
GLXPbuffer pbuffer;
GLuint texture;
void *fb;
- target_phys_addr_t fb_len;
+ Phys fb_len;
void *mesh;
- target_phys_addr_t mesh_len;
+ Phys mesh_len;
float m;
trace_milkymist_tmu2_start();
@@ -310,7 +310,7 @@ static void tmu2_start(MilkymistTMU2State *s)
qemu_irq_pulse(s->irq);
}
-static uint64_t tmu2_read(void *opaque, target_phys_addr_t addr,
+static uint64_t tmu2_read(void *opaque, Phys addr,
unsigned size)
{
MilkymistTMU2State *s = opaque;
@@ -372,7 +372,7 @@ static void tmu2_check_registers(MilkymistTMU2State *s)
}
}
-static void tmu2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void tmu2_write(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
MilkymistTMU2State *s = opaque;
diff --git a/hw/milkymist-uart.c b/hw/milkymist-uart.c
index eaf1c0d..84bbcbb 100644
--- a/hw/milkymist-uart.c
+++ b/hw/milkymist-uart.c
@@ -78,7 +78,7 @@ static void uart_update_irq(MilkymistUartState *s)
}
}
-static uint64_t uart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t uart_read(void *opaque, Phys addr,
unsigned size)
{
MilkymistUartState *s = opaque;
@@ -107,7 +107,7 @@ static uint64_t uart_read(void *opaque, target_phys_addr_t
addr,
return r;
}
-static void uart_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void uart_write(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
MilkymistUartState *s = opaque;
diff --git a/hw/milkymist-vgafb.c b/hw/milkymist-vgafb.c
index 108115e..ed7403f 100644
--- a/hw/milkymist-vgafb.c
+++ b/hw/milkymist-vgafb.c
@@ -154,7 +154,7 @@ static void vgafb_resize(MilkymistVgafbState *s)
s->invalidate = 1;
}
-static uint64_t vgafb_read(void *opaque, target_phys_addr_t addr,
+static uint64_t vgafb_read(void *opaque, Phys addr,
unsigned size)
{
MilkymistVgafbState *s = opaque;
@@ -191,7 +191,7 @@ static uint64_t vgafb_read(void *opaque, target_phys_addr_t
addr,
return r;
}
-static void vgafb_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void vgafb_write(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
MilkymistVgafbState *s = opaque;
diff --git a/hw/milkymist.c b/hw/milkymist.c
index eaef0c2..8927876 100644
--- a/hw/milkymist.c
+++ b/hw/milkymist.c
@@ -38,11 +38,11 @@
typedef struct {
CPUState *env;
- target_phys_addr_t bootstrap_pc;
- target_phys_addr_t flash_base;
- target_phys_addr_t initrd_base;
+ Phys bootstrap_pc;
+ Phys flash_base;
+ Phys initrd_base;
size_t initrd_size;
- target_phys_addr_t cmdline_base;
+ Phys cmdline_base;
} ResetInfo;
static void cpu_irq_handler(void *opaque, int irq, int level)
@@ -90,14 +90,14 @@ static void main_cpu_reset(void *opaque)
ResetInfo *reset_info;
/* memory map */
- target_phys_addr_t flash_base = 0x00000000;
+ Phys flash_base = 0x00000000;
size_t flash_sector_size = 128 * 1024;
size_t flash_size = 32 * 1024 * 1024;
- target_phys_addr_t sdram_base = 0x40000000;
+ Phys sdram_base = 0x40000000;
size_t sdram_size = 128 * 1024 * 1024;
- target_phys_addr_t initrd_base = sdram_base + 0x1002000;
- target_phys_addr_t cmdline_base = sdram_base + 0x1000000;
+ Phys initrd_base = sdram_base + 0x1002000;
+ Phys cmdline_base = sdram_base + 0x1000000;
size_t initrd_max = sdram_size - 0x1002000;
reset_info = g_malloc0(sizeof(ResetInfo));
diff --git a/hw/mips.h b/hw/mips.h
index 22156fc..d5adf45 100644
--- a/hw/mips.h
+++ b/hw/mips.h
@@ -11,11 +11,11 @@ PCIBus *gt64120_register(qemu_irq *pic);
PCIBus *bonito_init(qemu_irq *pic);
/* jazz_led.c */
-void jazz_led_init(MemoryRegion *address_space, target_phys_addr_t base);
+void jazz_led_init(MemoryRegion *address_space, Phys base);
/* rc4030.c */
typedef struct rc4030DMAState *rc4030_dma;
-void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf,
int len, int is_write);
+void rc4030_dma_memory_rw(void *opaque, Phys addr, uint8_t *buf, int len, int
is_write);
void rc4030_dma_read(void *dma, uint8_t *buf, int len);
void rc4030_dma_write(void *dma, uint8_t *buf, int len);
@@ -24,9 +24,9 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
MemoryRegion *sysmem);
/* dp8393x.c */
-void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
+void dp83932_init(NICInfo *nd, Phys base, int it_shift,
MemoryRegion *address_space,
qemu_irq irq, void* mem_opaque,
- void (*memory_rw)(void *opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int is_write));
+ void (*memory_rw)(void *opaque, Phys addr, uint8_t *buf, int
len, int is_write));
#endif
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 63165b9..0930dd9 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -52,12 +52,12 @@ static void main_cpu_reset(void *opaque)
cpu_reset(env);
}
-static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t rtc_read(void *opaque, Phys addr, unsigned size)
{
return cpu_inw(0x71);
}
-static void rtc_write(void *opaque, target_phys_addr_t addr,
+static void rtc_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
cpu_outw(0x71, val & 0xff);
@@ -69,7 +69,7 @@ static void rtc_write(void *opaque, target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
+static uint64_t dma_dummy_read(void *opaque, Phys addr,
unsigned size)
{
/* Nothing to do. That is only to ensure that
@@ -77,7 +77,7 @@ static uint64_t dma_dummy_read(void *opaque,
target_phys_addr_t addr,
return 0xff;
}
-static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
+static void dma_dummy_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
/* Nothing to do. That is only to ensure that
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 6b72cf2..dff1052 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -218,7 +218,7 @@ static void eeprom24c0x_write(int scl, int sda)
eeprom.sda = sda;
}
-static uint64_t malta_fpga_read(void *opaque, target_phys_addr_t addr,
+static uint64_t malta_fpga_read(void *opaque, Phys addr,
unsigned size)
{
MaltaFPGAState *s = opaque;
@@ -306,7 +306,7 @@ static uint64_t malta_fpga_read(void *opaque,
target_phys_addr_t addr,
return val;
}
-static void malta_fpga_write(void *opaque, target_phys_addr_t addr,
+static void malta_fpga_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
MaltaFPGAState *s = opaque;
@@ -428,7 +428,7 @@ static void malta_fpga_led_init(CharDriverState *chr)
}
static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
- target_phys_addr_t base, qemu_irq uart_irq, CharDriverState *uart_chr)
+ Phys base, qemu_irq uart_irq, CharDriverState *uart_chr)
{
MaltaFPGAState *s;
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 1c0615c..28087ee 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -42,7 +42,7 @@
const char *initrd_filename;
} loaderparams;
-static void mips_qemu_write (void *opaque, target_phys_addr_t addr,
+static void mips_qemu_write (void *opaque, Phys addr,
uint64_t val, unsigned size)
{
if ((addr & 0xffff) == 0 && val == 42)
@@ -51,7 +51,7 @@ static void mips_qemu_write (void *opaque, target_phys_addr_t
addr,
qemu_system_shutdown_request ();
}
-static uint64_t mips_qemu_read (void *opaque, target_phys_addr_t addr,
+static uint64_t mips_qemu_read (void *opaque, Phys addr,
unsigned size)
{
return 0;
diff --git a/hw/mipsnet.c b/hw/mipsnet.c
index b1234b8..c1acccc 100644
--- a/hw/mipsnet.c
+++ b/hw/mipsnet.c
@@ -96,7 +96,7 @@ static ssize_t mipsnet_receive(VLANClientState *nc, const
uint8_t *buf, size_t s
return size;
}
-static uint64_t mipsnet_ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mipsnet_ioport_read(void *opaque, Phys addr,
unsigned int size)
{
MIPSnetState *s = opaque;
@@ -142,7 +142,7 @@ static uint64_t mipsnet_ioport_read(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void mipsnet_ioport_write(void *opaque, target_phys_addr_t addr,
+static void mipsnet_ioport_write(void *opaque, Phys addr,
uint64_t val, unsigned int size)
{
MIPSnetState *s = opaque;
diff --git a/hw/mpc8544_guts.c b/hw/mpc8544_guts.c
index f01b38c..c853e0c 100644
--- a/hw/mpc8544_guts.c
+++ b/hw/mpc8544_guts.c
@@ -58,7 +58,7 @@ struct GutsState {
typedef struct GutsState GutsState;
-static uint64_t mpc8544_guts_read(void *opaque, target_phys_addr_t addr,
+static uint64_t mpc8544_guts_read(void *opaque, Phys addr,
unsigned size)
{
uint32_t value = 0;
@@ -80,7 +80,7 @@ static uint64_t mpc8544_guts_read(void *opaque,
target_phys_addr_t addr,
return value;
}
-static void mpc8544_guts_write(void *opaque, target_phys_addr_t addr,
+static void mpc8544_guts_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
addr &= MPC8544_GUTS_MMIO_SIZE - 1;
diff --git a/hw/msix.c b/hw/msix.c
index 149eed2..3f7e120 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -83,7 +83,7 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned
short nentries,
return 0;
}
-static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t msix_mmio_read(void *opaque, Phys addr,
unsigned size)
{
PCIDevice *dev = opaque;
@@ -179,7 +179,7 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
}
}
-static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
+static void msix_mmio_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
PCIDevice *dev = opaque;
diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c
index 9324702..e7c5d23 100644
--- a/hw/mst_fpga.c
+++ b/hw/mst_fpga.c
@@ -88,7 +88,7 @@
static uint64_t
-mst_fpga_readb(void *opaque, target_phys_addr_t addr, unsigned size)
+mst_fpga_readb(void *opaque, Phys addr, unsigned size)
{
mst_irq_state *s = (mst_irq_state *) opaque;
@@ -125,7 +125,7 @@
}
static void
-mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint64_t value,
+mst_fpga_writeb(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
mst_irq_state *s = (mst_irq_state *) opaque;
diff --git a/hw/multiboot.c b/hw/multiboot.c
index b4484a3..02675c3 100644
--- a/hw/multiboot.c
+++ b/hw/multiboot.c
@@ -80,15 +80,15 @@ enum {
/* buffer holding kernel, cmdlines and mb_infos */
void *mb_buf;
/* address in target */
- target_phys_addr_t mb_buf_phys;
+ Phys mb_buf_phys;
/* size of mb_buf in bytes */
unsigned mb_buf_size;
/* offset of mb-info's in bytes */
- target_phys_addr_t offset_mbinfo;
+ Phys offset_mbinfo;
/* offset in buffer for cmdlines in bytes */
- target_phys_addr_t offset_cmdlines;
+ Phys offset_cmdlines;
/* offset of modules in bytes */
- target_phys_addr_t offset_mods;
+ Phys offset_mods;
/* available slots for mb modules infos */
int mb_mods_avail;
/* currently used slots of mb modules */
@@ -97,7 +97,7 @@ enum {
static uint32_t mb_add_cmdline(MultibootState *s, const char *cmdline)
{
- target_phys_addr_t p = s->offset_cmdlines;
+ Phys p = s->offset_cmdlines;
char *b = (char *)s->mb_buf + p;
get_opt_value(b, strlen(cmdline) + 1, cmdline);
@@ -106,8 +106,8 @@ static uint32_t mb_add_cmdline(MultibootState *s, const
char *cmdline)
}
static void mb_add_mod(MultibootState *s,
- target_phys_addr_t start, target_phys_addr_t end,
- target_phys_addr_t cmdline_phys)
+ Phys start, Phys end,
+ Phys cmdline_phys)
{
char *p;
assert(s->mb_mods_count < s->mb_mods_avail);
@@ -270,7 +270,7 @@ int load_multiboot(void *fw_cfg,
*next_initrd = '\0';
/* if a space comes after the module filename, treat everything
after that as parameters */
- target_phys_addr_t c = mb_add_cmdline(&mbs, initrd_filename);
+ Phys c = mb_add_cmdline(&mbs, initrd_filename);
if ((next_space = strchr(initrd_filename, ' ')))
*next_space = '\0';
mb_debug("multiboot loading module: %s\n", initrd_filename);
diff --git a/hw/musicpal.c b/hw/musicpal.c
index a01e3d2..a5b100a 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -262,7 +262,7 @@ static void eth_send(mv88w8618_eth_state *s, int
queue_index)
} while (desc_addr != s->tx_queue[queue_index]);
}
-static uint64_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_eth_read(void *opaque, Phys offset,
unsigned size)
{
mv88w8618_eth_state *s = opaque;
@@ -304,7 +304,7 @@ static uint64_t mv88w8618_eth_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_eth_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
mv88w8618_eth_state *s = opaque;
@@ -525,7 +525,7 @@ static void musicpal_lcd_gpio_brigthness_in(void *opaque,
int irq, int level)
s->brightness |= level << irq;
}
-static uint64_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset,
+static uint64_t musicpal_lcd_read(void *opaque, Phys offset,
unsigned size)
{
musicpal_lcd_state *s = opaque;
@@ -539,7 +539,7 @@ static uint64_t musicpal_lcd_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
+static void musicpal_lcd_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
musicpal_lcd_state *s = opaque;
@@ -658,7 +658,7 @@ static void mv88w8618_pic_set_irq(void *opaque, int irq,
int level)
mv88w8618_pic_update(s);
}
-static uint64_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_pic_read(void *opaque, Phys offset,
unsigned size)
{
mv88w8618_pic_state *s = opaque;
@@ -672,7 +672,7 @@ static uint64_t mv88w8618_pic_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_pic_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
mv88w8618_pic_state *s = opaque;
@@ -782,7 +782,7 @@ static void mv88w8618_timer_init(SysBusDevice *dev,
mv88w8618_timer_state *s,
s->ptimer = ptimer_init(bh);
}
-static uint64_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_pit_read(void *opaque, Phys offset,
unsigned size)
{
mv88w8618_pit_state *s = opaque;
@@ -798,7 +798,7 @@ static uint64_t mv88w8618_pit_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_pit_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
mv88w8618_pit_state *s = opaque;
@@ -915,7 +915,7 @@ static int mv88w8618_pit_init(SysBusDevice *dev)
} mv88w8618_flashcfg_state;
static uint64_t mv88w8618_flashcfg_read(void *opaque,
- target_phys_addr_t offset,
+ Phys offset,
unsigned size)
{
mv88w8618_flashcfg_state *s = opaque;
@@ -929,7 +929,7 @@ static uint64_t mv88w8618_flashcfg_read(void *opaque,
}
}
-static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_flashcfg_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
mv88w8618_flashcfg_state *s = opaque;
@@ -981,7 +981,7 @@ static int mv88w8618_flashcfg_init(SysBusDevice *dev)
#define MP_BOARD_REVISION 0x31
-static uint64_t musicpal_misc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t musicpal_misc_read(void *opaque, Phys offset,
unsigned size)
{
switch (offset) {
@@ -993,7 +993,7 @@ static uint64_t musicpal_misc_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
+static void musicpal_misc_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
}
@@ -1017,7 +1017,7 @@ static void musicpal_misc_init(SysBusDevice *dev)
#define MP_WLAN_MAGIC1 0x11c
#define MP_WLAN_MAGIC2 0x124
-static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset,
+static uint64_t mv88w8618_wlan_read(void *opaque, Phys offset,
unsigned size)
{
switch (offset) {
@@ -1033,7 +1033,7 @@ static uint64_t mv88w8618_wlan_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
+static void mv88w8618_wlan_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
}
@@ -1151,7 +1151,7 @@ static void musicpal_gpio_pin_event(void *opaque, int
pin, int level)
}
}
-static uint64_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t musicpal_gpio_read(void *opaque, Phys offset,
unsigned size)
{
musicpal_gpio_state *s = opaque;
@@ -1190,7 +1190,7 @@ static uint64_t musicpal_gpio_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
+static void musicpal_gpio_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
musicpal_gpio_state *s = opaque;
diff --git a/hw/ne2000.c b/hw/ne2000.c
index 62e082f..15bcadc 100644
--- a/hw/ne2000.c
+++ b/hw/ne2000.c
@@ -676,7 +676,7 @@ static int ne2000_post_load(void* opaque, int version_id)
}
};
-static uint64_t ne2000_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ne2000_read(void *opaque, Phys addr,
unsigned size)
{
NE2000State *s = opaque;
@@ -695,7 +695,7 @@ static uint64_t ne2000_read(void *opaque,
target_phys_addr_t addr,
return ((uint64_t)1 << (size * 8)) - 1;
}
-static void ne2000_write(void *opaque, target_phys_addr_t addr,
+static void ne2000_write(void *opaque, Phys addr,
uint64_t data, unsigned size)
{
NE2000State *s = opaque;
diff --git a/hw/nvram.h b/hw/nvram.h
index 8924da4..dbd53e9 100644
--- a/hw/nvram.h
+++ b/hw/nvram.h
@@ -36,7 +36,7 @@ uint32_t m48t59_read (void *private, uint32_t addr);
void m48t59_toggle_lock (void *private, int lock);
M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
int type);
-M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
+M48t59State *m48t59_init(qemu_irq IRQ, Phys mem_base,
uint32_t io_base, uint16_t size, int type);
void m48t59_set_addr (void *opaque, uint32_t addr);
diff --git a/hw/omap.h b/hw/omap.h
index 60fa34c..6cca7a3 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -65,7 +65,7 @@ void omap_clk_reparent(omap_clk clk, omap_clk parent);
/* OMAP2 l4 Interconnect */
struct omap_l4_s;
struct omap_l4_region_s {
- target_phys_addr_t offset;
+ Phys offset;
size_t size;
int access;
};
@@ -80,13 +80,13 @@ struct omap_target_agent_s {
struct omap_l4_s *bus;
int regions;
const struct omap_l4_region_s *start;
- target_phys_addr_t base;
+ Phys base;
uint32_t component;
uint32_t control;
uint32_t status;
};
struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
- target_phys_addr_t base, int ta_num);
+ Phys base, int ta_num);
struct omap_target_agent_s;
struct omap_target_agent_s *omap_l4ta_get(
@@ -94,23 +94,23 @@ struct omap_target_agent_s *omap_l4ta_get(
const struct omap_l4_region_s *regions,
const struct omap_l4_agent_info_s *agents,
int cs);
-target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta,
+Phys omap_l4_attach(struct omap_target_agent_s *ta,
int region, MemoryRegion *mr);
-target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
+Phys omap_l4_region_base(struct omap_target_agent_s *ta,
int region);
-target_phys_addr_t omap_l4_region_size(struct omap_target_agent_s *ta,
+Phys omap_l4_region_size(struct omap_target_agent_s *ta,
int region);
/* OMAP2 SDRAM controller */
struct omap_sdrc_s;
struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
- target_phys_addr_t base);
+ Phys base);
void omap_sdrc_reset(struct omap_sdrc_s *s);
/* OMAP2 general purpose memory controller */
struct omap_gpmc_s;
struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq, qemu_irq drq);
void omap_gpmc_reset(struct omap_gpmc_s *s);
void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
@@ -433,11 +433,11 @@ enum omap_dma_model {
};
struct soc_dma_s;
-struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma_init(Phys base, qemu_irq *irqs,
MemoryRegion *sysmem,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model);
-struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma4_init(Phys base, qemu_irq *irqs,
MemoryRegion *sysmem,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk);
@@ -469,10 +469,10 @@ typedef enum {
/* Only used in OMAP DMA 3.x gigacells */
struct omap_dma_lcd_channel_s {
enum omap_dma_port src;
- target_phys_addr_t src_f1_top;
- target_phys_addr_t src_f1_bottom;
- target_phys_addr_t src_f2_top;
- target_phys_addr_t src_f2_bottom;
+ Phys src_f1_top;
+ Phys src_f1_bottom;
+ Phys src_f2_top;
+ Phys src_f2_bottom;
/* Used in OMAP DMA 3.2 gigacell */
unsigned char brust_f1;
@@ -508,7 +508,7 @@ struct omap_dma_lcd_channel_s {
int dual;
int current_frame;
- target_phys_addr_t phys_framebuffer[2];
+ Phys phys_framebuffer[2];
qemu_irq irq;
struct omap_mpu_state_s *mpu;
} *omap_dma_get_lcdch(struct soc_dma_s *s);
@@ -659,7 +659,7 @@ struct omap_synctimer_s *omap_synctimer_init(struct
omap_target_agent_s *ta,
void omap_synctimer_reset(struct omap_synctimer_s *s);
struct omap_uart_s;
-struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
+struct omap_uart_s *omap_uart_init(Phys base,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr);
@@ -728,7 +728,7 @@ void omap_tap_init(struct omap_target_agent_s *ta,
struct omap_lcd_panel_s;
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
omap_clk clk);
@@ -744,7 +744,7 @@ struct omap_dss_s;
void omap_dss_reset(struct omap_dss_s *s);
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
MemoryRegion *sysmem,
- target_phys_addr_t l3_base,
+ Phys l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2);
@@ -752,7 +752,7 @@ void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct
rfbi_chip_s *chip);
/* omap_mmc.c */
struct omap_mmc_s;
-struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
+struct omap_mmc_s *omap_mmc_init(Phys base,
MemoryRegion *sysmem,
BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk);
@@ -766,7 +766,7 @@ void omap_mmc_enable(struct omap_mmc_s *s, int enable);
/* omap_i2c.c */
struct omap_i2c_s;
struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq,
qemu_irq *dma,
omap_clk clk);
@@ -838,11 +838,11 @@ struct omap_mpu_state_s {
struct omap_dma_port_if_s {
uint32_t (*read[3])(struct omap_mpu_state_s *s,
- target_phys_addr_t offset);
+ Phys offset);
void (*write[3])(struct omap_mpu_state_s *s,
- target_phys_addr_t offset, uint32_t value);
+ Phys offset, uint32_t value);
int (*addr_valid)(struct omap_mpu_state_s *s,
- target_phys_addr_t addr);
+ Phys addr);
} port[__omap_dma_port_last];
unsigned long sdram_size;
@@ -959,14 +959,14 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion
*sysmem,
# error TARGET_PHYS_ADDR_BITS undefined
# endif
-uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
-void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
+uint32_t omap_badwidth_read8(void *opaque, Phys addr);
+void omap_badwidth_write8(void *opaque, Phys addr,
uint32_t value);
-uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
-void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
+uint32_t omap_badwidth_read16(void *opaque, Phys addr);
+void omap_badwidth_write16(void *opaque, Phys addr,
uint32_t value);
-uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
-void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
+uint32_t omap_badwidth_read32(void *opaque, Phys addr);
+void omap_badwidth_write32(void *opaque, Phys addr,
uint32_t value);
void omap_mpu_wakeup(void *opaque, int irq, int req);
@@ -1035,7 +1035,7 @@ struct io_fn {
int in;
};
-static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t io_readb(void *opaque, Phys addr)
{
struct io_fn *s = opaque;
uint32_t ret;
@@ -1047,7 +1047,7 @@ static uint32_t io_readb(void *opaque, target_phys_addr_t
addr)
fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
return ret;
}
-static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
+static uint32_t io_readh(void *opaque, Phys addr)
{
struct io_fn *s = opaque;
uint32_t ret;
@@ -1059,7 +1059,7 @@ static uint32_t io_readh(void *opaque, target_phys_addr_t
addr)
fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
return ret;
}
-static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t io_readw(void *opaque, Phys addr)
{
struct io_fn *s = opaque;
uint32_t ret;
@@ -1071,7 +1071,7 @@ static uint32_t io_readw(void *opaque, target_phys_addr_t
addr)
fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
return ret;
}
-static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void io_writeb(void *opaque, Phys addr, uint32_t value)
{
struct io_fn *s = opaque;
@@ -1081,7 +1081,7 @@ static void io_writeb(void *opaque, target_phys_addr_t
addr, uint32_t value)
s->mem_write[0](s->opaque, addr, value);
s->in --;
}
-static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void io_writeh(void *opaque, Phys addr, uint32_t value)
{
struct io_fn *s = opaque;
@@ -1091,7 +1091,7 @@ static void io_writeh(void *opaque, target_phys_addr_t
addr, uint32_t value)
s->mem_write[1](s->opaque, addr, value);
s->in --;
}
-static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void io_writew(void *opaque, Phys addr, uint32_t value)
{
struct io_fn *s = opaque;
diff --git a/hw/omap1.c b/hw/omap1.c
index 1aa5f23..5e71ab3 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -26,7 +26,7 @@
#include "sysbus.h"
/* Should signal the TCMI/GPMC */
-uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read8(void *opaque, Phys addr)
{
uint8_t ret;
@@ -35,7 +35,7 @@ uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t
addr)
return ret;
}
-void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write8(void *opaque, Phys addr,
uint32_t value)
{
uint8_t val8 = value;
@@ -44,7 +44,7 @@ void omap_badwidth_write8(void *opaque, target_phys_addr_t
addr,
cpu_physical_memory_write(addr, (void *) &val8, 1);
}
-uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read16(void *opaque, Phys addr)
{
uint16_t ret;
@@ -53,7 +53,7 @@ uint32_t omap_badwidth_read16(void *opaque,
target_phys_addr_t addr)
return ret;
}
-void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write16(void *opaque, Phys addr,
uint32_t value)
{
uint16_t val16 = value;
@@ -62,7 +62,7 @@ void omap_badwidth_write16(void *opaque, target_phys_addr_t
addr,
cpu_physical_memory_write(addr, (void *) &val16, 2);
}
-uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read32(void *opaque, Phys addr)
{
uint32_t ret;
@@ -71,7 +71,7 @@ uint32_t omap_badwidth_read32(void *opaque,
target_phys_addr_t addr)
return ret;
}
-void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write32(void *opaque, Phys addr,
uint32_t value)
{
OMAP_32B_REG(addr);
@@ -176,7 +176,7 @@ static void omap_timer_clk_setup(struct omap_mpu_timer_s
*timer)
timer->rate = omap_clk_getrate(timer->clk);
}
-static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpu_timer_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
@@ -200,7 +200,7 @@ static uint64_t omap_mpu_timer_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpu_timer_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
@@ -251,7 +251,7 @@ static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
}
static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion
*system_memory,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq, omap_clk clk)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
@@ -282,7 +282,7 @@ struct omap_watchdog_timer_s {
int reset;
};
-static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_wd_timer_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
@@ -307,7 +307,7 @@ static uint64_t omap_wd_timer_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_wd_timer_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
@@ -380,7 +380,7 @@ static void omap_wd_timer_reset(struct
omap_watchdog_timer_s *s)
}
static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq, omap_clk clk)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
@@ -405,7 +405,7 @@ struct omap_32khz_timer_s {
MemoryRegion iomem;
};
-static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_os_timer_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
@@ -432,7 +432,7 @@ static uint64_t omap_os_timer_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_os_timer_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
@@ -486,7 +486,7 @@ static void omap_os_timer_reset(struct omap_32khz_timer_s
*s)
}
static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq, omap_clk clk)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
@@ -506,7 +506,7 @@ static void omap_os_timer_reset(struct omap_32khz_timer_s
*s)
}
/* Ultra Low-Power Device Module */
-static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_ulpd_pm_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -573,7 +573,7 @@ static inline void omap_ulpd_req_update(struct
omap_mpu_state_s *s,
omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
}
-static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
+static void omap_ulpd_pm_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -726,7 +726,7 @@ static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
}
static void omap_ulpd_pm_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ Phys base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
@@ -736,7 +736,7 @@ static void omap_ulpd_pm_init(MemoryRegion *system_memory,
}
/* OMAP Pin Configuration */
-static uint64_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_pin_cfg_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -843,7 +843,7 @@ static inline void omap_pin_modconf1_update(struct
omap_mpu_state_s *s,
omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
}
-static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
+static void omap_pin_cfg_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -944,7 +944,7 @@ static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
}
static void omap_pin_cfg_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ Phys base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
@@ -954,7 +954,7 @@ static void omap_pin_cfg_init(MemoryRegion *system_memory,
}
/* Device Identification, Die Identification */
-static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_id_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1001,7 +1001,7 @@ static uint64_t omap_id_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_id_write(void *opaque, target_phys_addr_t addr,
+static void omap_id_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
if (size != 4) {
@@ -1035,7 +1035,7 @@ static void omap_id_init(MemoryRegion *memory, struct
omap_mpu_state_s *mpu)
}
/* MPUI Control (Dummy) */
-static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpui_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1068,7 +1068,7 @@ static uint64_t omap_mpui_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpui_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1109,7 +1109,7 @@ static void omap_mpui_reset(struct omap_mpu_state_s *s)
s->mpui_ctrl = 0x0003ff1b;
}
-static void omap_mpui_init(MemoryRegion *memory, target_phys_addr_t base,
+static void omap_mpui_init(MemoryRegion *memory, Phys base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
@@ -1131,7 +1131,7 @@ struct omap_tipb_bridge_s {
uint16_t enh_control;
};
-static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_tipb_bridge_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
@@ -1161,7 +1161,7 @@ static uint64_t omap_tipb_bridge_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
+static void omap_tipb_bridge_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
@@ -1215,7 +1215,7 @@ static void omap_tipb_bridge_reset(struct
omap_tipb_bridge_s *s)
}
static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
- MemoryRegion *memory, target_phys_addr_t base,
+ MemoryRegion *memory, Phys base,
qemu_irq abort_irq, omap_clk clk)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
@@ -1232,7 +1232,7 @@ static void omap_tipb_bridge_reset(struct
omap_tipb_bridge_s *s)
}
/* Dummy Traffic Controller's Memory Interface */
-static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_tcmi_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1270,7 +1270,7 @@ static uint64_t omap_tcmi_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
+static void omap_tcmi_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1330,7 +1330,7 @@ static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
}
-static void omap_tcmi_init(MemoryRegion *memory, target_phys_addr_t base,
+static void omap_tcmi_init(MemoryRegion *memory, Phys base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu,
@@ -1346,7 +1346,7 @@ struct dpll_ctl_s {
omap_clk dpll;
};
-static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_dpll_read(void *opaque, Phys addr,
unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
@@ -1362,7 +1362,7 @@ static uint64_t omap_dpll_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
+static void omap_dpll_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
@@ -1412,7 +1412,7 @@ static void omap_dpll_reset(struct dpll_ctl_s *s)
}
static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
- target_phys_addr_t base, omap_clk clk)
+ Phys base, omap_clk clk)
{
struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
@@ -1425,7 +1425,7 @@ static void omap_dpll_reset(struct dpll_ctl_s *s)
}
/* MPU Clock/Reset/Power Mode Control */
-static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_clkm_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1626,7 +1626,7 @@ static inline void omap_clkm_ckout1_update(struct
omap_mpu_state_s *s,
}
}
-static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
+static void omap_clkm_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1713,7 +1713,7 @@ static void omap_clkm_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_clkdsp_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1757,7 +1757,7 @@ static inline void omap_clkdsp_idlect2_update(struct
omap_mpu_state_s *s,
SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
}
-static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
+static void omap_clkdsp_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -1822,8 +1822,8 @@ static void omap_clkm_reset(struct omap_mpu_state_s *s)
s->clkm.dsp_rstct2 = 0x0000;
}
-static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base,
- target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
+static void omap_clkm_init(MemoryRegion *memory, Phys mpu_base,
+ Phys dsp_base, struct omap_mpu_state_s *s)
{
memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s,
"omap-clkm", 0x100);
@@ -1902,7 +1902,7 @@ static void omap_mpuio_kbd_update(struct omap_mpuio_s *s)
s->row_latch = ~rows;
}
-static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpuio_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
@@ -1962,7 +1962,7 @@ static uint64_t omap_mpuio_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpuio_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
@@ -2071,7 +2071,7 @@ static void omap_mpuio_onoff(void *opaque, int line, int
on)
}
static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
- target_phys_addr_t base,
+ Phys base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk)
{
@@ -2158,7 +2158,7 @@ static void omap_uwire_transfer_start(struct omap_uwire_s
*s)
}
}
-static uint64_t omap_uwire_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_uwire_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
@@ -2192,7 +2192,7 @@ static uint64_t omap_uwire_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
+static void omap_uwire_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
@@ -2262,7 +2262,7 @@ static void omap_uwire_reset(struct omap_uwire_s *s)
}
static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ Phys base,
qemu_irq txirq, qemu_irq rxirq,
qemu_irq dma,
omap_clk clk)
@@ -2311,7 +2311,7 @@ static void omap_pwl_update(struct omap_pwl_s *s)
}
}
-static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_pwl_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
@@ -2331,7 +2331,7 @@ static uint64_t omap_pwl_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
+static void omap_pwl_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
@@ -2380,7 +2380,7 @@ static void omap_pwl_clk_update(void *opaque, int line,
int on)
}
static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ Phys base,
omap_clk clk)
{
struct omap_pwl_s *s = g_malloc0(sizeof(*s));
@@ -2404,7 +2404,7 @@ struct omap_pwt_s {
omap_clk clk;
};
-static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_pwt_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
@@ -2426,7 +2426,7 @@ static uint64_t omap_pwt_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
+static void omap_pwt_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
@@ -2487,7 +2487,7 @@ static void omap_pwt_reset(struct omap_pwt_s *s)
}
static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ Phys base,
omap_clk clk)
{
struct omap_pwt_s *s = g_malloc0(sizeof(*s));
@@ -2535,7 +2535,7 @@ static void omap_rtc_alarm_update(struct omap_rtc_s *s)
printf("%s: conversion failed\n", __FUNCTION__);
}
-static uint64_t omap_rtc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_rtc_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
@@ -2617,7 +2617,7 @@ static uint64_t omap_rtc_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
+static void omap_rtc_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
@@ -2900,7 +2900,7 @@ static void omap_rtc_reset(struct omap_rtc_s *s)
}
static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ Phys base,
qemu_irq timerirq, qemu_irq alarmirq,
omap_clk clk)
{
@@ -3128,7 +3128,7 @@ static void omap_mcbsp_req_update(struct omap_mcbsp_s *s)
omap_mcbsp_rx_stop(s);
}
-static uint64_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mcbsp_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
@@ -3226,7 +3226,7 @@ static uint64_t omap_mcbsp_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
+static void omap_mcbsp_writeh(void *opaque, Phys addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
@@ -3364,7 +3364,7 @@ static void omap_mcbsp_writeh(void *opaque,
target_phys_addr_t addr,
OMAP_BAD_REG(addr);
}
-static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
+static void omap_mcbsp_writew(void *opaque, Phys addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
@@ -3395,7 +3395,7 @@ static void omap_mcbsp_writew(void *opaque,
target_phys_addr_t addr,
omap_badwidth_write16(opaque, addr, value);
}
-static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr,
+static void omap_mcbsp_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
switch (size) {
@@ -3431,7 +3431,7 @@ static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
}
static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ Phys base,
qemu_irq txirq, qemu_irq rxirq,
qemu_irq *dma, omap_clk clk)
{
@@ -3546,7 +3546,7 @@ static void omap_lpg_reset(struct omap_lpg_s *s)
omap_lpg_update(s);
}
-static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_lpg_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
@@ -3568,7 +3568,7 @@ static uint64_t omap_lpg_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
+static void omap_lpg_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
@@ -3612,7 +3612,7 @@ static void omap_lpg_clk_update(void *opaque, int line,
int on)
}
static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
- target_phys_addr_t base, omap_clk clk)
+ Phys base, omap_clk clk)
{
struct omap_lpg_s *s = (struct omap_lpg_s *)
g_malloc0(sizeof(struct omap_lpg_s));
@@ -3630,7 +3630,7 @@ static void omap_lpg_clk_update(void *opaque, int line,
int on)
}
/* MPUI Peripheral Bridge configuration */
-static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpui_io_read(void *opaque, Phys addr,
unsigned size)
{
if (size != 2) {
@@ -3644,7 +3644,7 @@ static uint64_t omap_mpui_io_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_mpui_io_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpui_io_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
/* FIXME: infinite loop */
@@ -3706,8 +3706,8 @@ static void omap1_mpu_reset(void *opaque)
}
static const struct omap_map_s {
- target_phys_addr_t phys_dsp;
- target_phys_addr_t phys_mpu;
+ Phys phys_dsp;
+ Phys phys_mpu;
uint32_t size;
const char *name;
} omap15xx_dsp_mm[] = {
@@ -3777,38 +3777,38 @@ void omap_mpu_wakeup(void *opaque, int irq, int req)
/* DMA ports for OMAP1 */
static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ Phys addr)
{
return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
}
static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ Phys addr)
{
return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE -
OMAP_EMIFS_BASE,
addr);
}
static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ Phys addr)
{
return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
}
static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ Phys addr)
{
return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr);
}
static int omap_validate_local_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ Phys addr)
{
return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr);
}
static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ Phys addr)
{
return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
}
diff --git a/hw/omap2.c b/hw/omap2.c
index a6851b0..9c416c5 100644
--- a/hw/omap2.c
+++ b/hw/omap2.c
@@ -324,7 +324,7 @@ static void omap_eac_reset(struct omap_eac_s *s)
omap_eac_interrupt_update(s);
}
-static uint64_t omap_eac_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_eac_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
@@ -440,7 +440,7 @@ static uint64_t omap_eac_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_eac_write(void *opaque, target_phys_addr_t addr,
+static void omap_eac_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
@@ -644,7 +644,7 @@ static void omap_sti_reset(struct omap_sti_s *s)
omap_sti_interrupt_update(s);
}
-static uint64_t omap_sti_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_sti_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
@@ -685,7 +685,7 @@ static uint64_t omap_sti_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_sti_write(void *opaque, target_phys_addr_t addr,
+static void omap_sti_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
@@ -741,14 +741,14 @@ static void omap_sti_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_sti_fifo_read(void *opaque, Phys addr,
unsigned size)
{
OMAP_BAD_REG(addr);
return 0;
}
-static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
+static void omap_sti_fifo_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
@@ -780,7 +780,7 @@ static void omap_sti_fifo_write(void *opaque,
target_phys_addr_t addr,
static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
MemoryRegion *sysmem,
- target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
+ Phys channel_base, qemu_irq irq, omap_clk clk,
CharDriverState *chr)
{
struct omap_sti_s *s = (struct omap_sti_s *)
@@ -1040,7 +1040,7 @@ static void omap_prcm_int_update(struct omap_prcm_s *s,
int dom)
/* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
}
-static uint64_t omap_prcm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_prcm_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
@@ -1352,7 +1352,7 @@ static void omap_prcm_dpll_update(struct omap_prcm_s *s)
}
}
-static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
+static void omap_prcm_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
@@ -1832,7 +1832,7 @@ struct omap_sysctl_s {
uint32_t msuspendmux[5];
};
-static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_sysctl_read8(void *opaque, Phys addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@@ -1857,7 +1857,7 @@ static uint32_t omap_sysctl_read8(void *opaque,
target_phys_addr_t addr)
return 0;
}
-static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_sysctl_read(void *opaque, Phys addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@@ -1957,7 +1957,7 @@ static uint32_t omap_sysctl_read(void *opaque,
target_phys_addr_t addr)
return 0;
}
-static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
+static void omap_sysctl_write8(void *opaque, Phys addr,
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@@ -1981,7 +1981,7 @@ static void omap_sysctl_write8(void *opaque,
target_phys_addr_t addr,
}
}
-static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
+static void omap_sysctl_write(void *opaque, Phys addr,
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
@@ -2228,7 +2228,7 @@ static void omap2_mpu_reset(void *opaque)
}
static int omap2_validate_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ Phys addr)
{
return 1;
}
diff --git a/hw/omap_dma.c b/hw/omap_dma.c
index 389cb78..677efa5 100644
--- a/hw/omap_dma.c
+++ b/hw/omap_dma.c
@@ -31,7 +31,7 @@ struct omap_dma_channel_s {
int endian_lock[2];
int translate[2];
enum omap_dma_port port[2];
- target_phys_addr_t addr[2];
+ Phys addr[2];
omap_dma_addressing_t mode[2];
uint32_t elements;
uint16_t frames;
@@ -78,7 +78,7 @@ struct omap_dma_channel_s {
struct omap_dma_channel_s *sibling;
struct omap_dma_reg_set_s {
- target_phys_addr_t src, dest;
+ Phys src, dest;
int frame;
int element;
int pck_element;
@@ -914,7 +914,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
break;
case 0x06: /* SYS_DMA_CSR_CH0 */
- OMAP_RO_REG((target_phys_addr_t) reg);
+ OMAP_RO_REG((Phys) reg);
break;
case 0x08: /* SYS_DMA_CSSA_L_CH0 */
@@ -954,7 +954,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
break;
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
- OMAP_RO_REG((target_phys_addr_t) reg);
+ OMAP_RO_REG((Phys) reg);
break;
case 0x1c: /* DMA_CDEI */
@@ -1446,7 +1446,7 @@ static int omap_dma_sys_read(struct omap_dma_s *s, int
offset,
return 0;
}
-static uint64_t omap_dma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_dma_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@@ -1494,7 +1494,7 @@ static uint64_t omap_dma_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_dma_write(void *opaque, target_phys_addr_t addr,
+static void omap_dma_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@@ -1618,7 +1618,7 @@ static void omap_dma_setcaps(struct omap_dma_s *s)
}
}
-struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma_init(Phys base, qemu_irq *irqs,
MemoryRegion *sysmem,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model)
@@ -1692,7 +1692,7 @@ static void omap_dma_interrupts_4_update(struct
omap_dma_s *s)
qemu_irq_raise(s->irq[3]);
}
-static uint64_t omap_dma4_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_dma4_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@@ -1842,7 +1842,7 @@ static uint64_t omap_dma4_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
+static void omap_dma4_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@@ -1988,12 +1988,12 @@ static void omap_dma4_write(void *opaque,
target_phys_addr_t addr,
break;
case 0x1c: /* DMA4_CSSA */
- ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
+ ch->addr[0] = (Phys) (uint32_t) value;
ch->set_update = 1;
break;
case 0x20: /* DMA4_CDSA */
- ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
+ ch->addr[1] = (Phys) (uint32_t) value;
ch->set_update = 1;
break;
@@ -2040,7 +2040,7 @@ static void omap_dma4_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma4_init(Phys base, qemu_irq *irqs,
MemoryRegion *sysmem,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk)
diff --git a/hw/omap_dss.c b/hw/omap_dss.c
index ede640b..d7b3d11 100644
--- a/hw/omap_dss.c
+++ b/hw/omap_dss.c
@@ -60,7 +60,7 @@ struct omap_dss_s {
int nx;
int ny;
- target_phys_addr_t addr[3];
+ Phys addr[3];
uint32_t attr;
uint32_t tresh;
@@ -168,7 +168,7 @@ void omap_dss_reset(struct omap_dss_s *s)
omap_dispc_interrupt_update(s);
}
-static uint64_t omap_diss_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_diss_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -206,7 +206,7 @@ static uint64_t omap_diss_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_diss_write(void *opaque, target_phys_addr_t addr,
+static void omap_diss_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -246,7 +246,7 @@ static void omap_diss_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_disc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_disc_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -371,7 +371,7 @@ static uint64_t omap_disc_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_disc_write(void *opaque, target_phys_addr_t addr,
+static void omap_disc_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -502,11 +502,11 @@ static void omap_disc_write(void *opaque,
target_phys_addr_t addr,
s->dispc.invalidate = 1;
break;
case 0x080: /* DISPC_GFX_BA0 */
- s->dispc.l[0].addr[0] = (target_phys_addr_t) value;
+ s->dispc.l[0].addr[0] = (Phys) value;
s->dispc.invalidate = 1;
break;
case 0x084: /* DISPC_GFX_BA1 */
- s->dispc.l[0].addr[1] = (target_phys_addr_t) value;
+ s->dispc.l[0].addr[1] = (Phys) value;
s->dispc.invalidate = 1;
break;
case 0x088: /* DISPC_GFX_POSITION */
@@ -543,7 +543,7 @@ static void omap_disc_write(void *opaque,
target_phys_addr_t addr,
s->dispc.l[0].wininc = value;
break;
case 0x0b8: /* DISPC_GFX_TABLE_BA */
- s->dispc.l[0].addr[2] = (target_phys_addr_t) value;
+ s->dispc.l[0].addr[2] = (Phys) value;
s->dispc.invalidate = 1;
break;
@@ -602,11 +602,11 @@ static void omap_rfbi_transfer_stop(struct omap_dss_s *s)
static void omap_rfbi_transfer_start(struct omap_dss_s *s)
{
void *data;
- target_phys_addr_t len;
- target_phys_addr_t data_addr;
+ Phys len;
+ Phys data_addr;
int pitch;
static void *bounce_buffer;
- static target_phys_addr_t bounce_len;
+ static Phys bounce_len;
if (!s->rfbi.enable || s->rfbi.busy)
return;
@@ -663,7 +663,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
omap_dispc_interrupt_update(s);
}
-static uint64_t omap_rfbi_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_rfbi_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -730,7 +730,7 @@ static uint64_t omap_rfbi_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
+static void omap_rfbi_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
@@ -864,7 +864,7 @@ static void omap_rfbi_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_venc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_venc_read(void *opaque, Phys addr,
unsigned size)
{
if (size != 4) {
@@ -924,7 +924,7 @@ static uint64_t omap_venc_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_venc_write(void *opaque, target_phys_addr_t addr,
+static void omap_venc_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
if (size != 4) {
@@ -986,7 +986,7 @@ static void omap_venc_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_im3_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_im3_read(void *opaque, Phys addr,
unsigned size)
{
if (size != 4) {
@@ -1012,7 +1012,7 @@ static uint64_t omap_im3_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_im3_write(void *opaque, target_phys_addr_t addr,
+static void omap_im3_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
if (size != 4) {
@@ -1041,7 +1041,7 @@ static void omap_im3_write(void *opaque,
target_phys_addr_t addr,
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
MemoryRegion *sysmem,
- target_phys_addr_t l3_base,
+ Phys l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2)
diff --git a/hw/omap_gpio.c b/hw/omap_gpio.c
index 29147be..f7e30bc 100644
--- a/hw/omap_gpio.c
+++ b/hw/omap_gpio.c
@@ -61,7 +61,7 @@ static void omap_gpio_set(void *opaque, int line, int level)
}
}
-static uint64_t omap_gpio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_gpio_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
@@ -99,7 +99,7 @@ static uint64_t omap_gpio_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_gpio_write(void *opaque, target_phys_addr_t addr,
+static void omap_gpio_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
@@ -300,7 +300,7 @@ static void omap2_gpio_module_reset(struct omap2_gpio_s *s)
s->delay = 0;
}
-static uint32_t omap2_gpio_module_read(void *opaque, target_phys_addr_t addr)
+static uint32_t omap2_gpio_module_read(void *opaque, Phys addr)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
@@ -372,7 +372,7 @@ static uint32_t omap2_gpio_module_read(void *opaque,
target_phys_addr_t addr)
return 0;
}
-static void omap2_gpio_module_write(void *opaque, target_phys_addr_t addr,
+static void omap2_gpio_module_write(void *opaque, Phys addr,
uint32_t value)
{
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
@@ -514,12 +514,12 @@ static void omap2_gpio_module_write(void *opaque,
target_phys_addr_t addr,
}
}
-static uint32_t omap2_gpio_module_readp(void *opaque, target_phys_addr_t addr)
+static uint32_t omap2_gpio_module_readp(void *opaque, Phys addr)
{
return omap2_gpio_module_read(opaque, addr & ~3) >> ((addr & 3) << 3);
}
-static void omap2_gpio_module_writep(void *opaque, target_phys_addr_t addr,
+static void omap2_gpio_module_writep(void *opaque, Phys addr,
uint32_t value)
{
uint32_t cur = 0;
@@ -604,7 +604,7 @@ static void omap2_gpif_reset(DeviceState *dev)
s->gpo = 0;
}
-static uint64_t omap2_gpif_top_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap2_gpif_top_read(void *opaque, Phys addr,
unsigned size)
{
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
@@ -633,7 +633,7 @@ static uint64_t omap2_gpif_top_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap2_gpif_top_write(void *opaque, target_phys_addr_t addr,
+static void omap2_gpif_top_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap2_gpif_s *s = (struct omap2_gpif_s *) opaque;
diff --git a/hw/omap_gpmc.c b/hw/omap_gpmc.c
index 2fc4137..2479d03 100644
--- a/hw/omap_gpmc.c
+++ b/hw/omap_gpmc.c
@@ -121,7 +121,7 @@ static void omap_gpmc_dma_update(struct omap_gpmc_s *s, int
value)
* all addresses in the region behave like accesses to the relevant
* GPMC_NAND_DATA_i register (which is actually implemented to call these)
*/
-static uint64_t omap_nand_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_nand_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
@@ -200,7 +200,7 @@ static void omap_nand_setio(DeviceState *dev, uint64_t
value,
}
}
-static void omap_nand_write(void *opaque, target_phys_addr_t addr,
+static void omap_nand_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
@@ -281,7 +281,7 @@ static void fill_prefetch_fifo(struct omap_gpmc_s *s)
* engine is enabled -- all addresses in the region behave alike:
* data is read or written to the FIFO.
*/
-static uint64_t omap_gpmc_prefetch_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_gpmc_prefetch_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
@@ -311,7 +311,7 @@ static uint64_t omap_gpmc_prefetch_read(void *opaque,
target_phys_addr_t addr,
return data;
}
-static void omap_gpmc_prefetch_write(void *opaque, target_phys_addr_t addr,
+static void omap_gpmc_prefetch_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
@@ -484,7 +484,7 @@ void omap_gpmc_reset(struct omap_gpmc_s *s)
ecc_reset(&s->ecc[i]);
}
-static int gpmc_wordaccess_only(target_phys_addr_t addr)
+static int gpmc_wordaccess_only(Phys addr)
{
/* Return true if the register offset is to a register that
* only permits word width accesses.
@@ -502,7 +502,7 @@ static int gpmc_wordaccess_only(target_phys_addr_t addr)
return 1;
}
-static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_gpmc_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
@@ -614,7 +614,7 @@ static uint64_t omap_gpmc_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
+static void omap_gpmc_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
@@ -819,7 +819,7 @@ static void omap_gpmc_write(void *opaque,
target_phys_addr_t addr,
};
struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq, qemu_irq drq)
{
int cs;
diff --git a/hw/omap_gptimer.c b/hw/omap_gptimer.c
index 7a14519..3e4055e 100644
--- a/hw/omap_gptimer.c
+++ b/hw/omap_gptimer.c
@@ -258,7 +258,7 @@ void omap_gp_timer_reset(struct omap_gp_timer_s *s)
omap_gp_timer_update(s);
}
-static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_gp_timer_readw(void *opaque, Phys addr)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
@@ -324,7 +324,7 @@ static uint32_t omap_gp_timer_readw(void *opaque,
target_phys_addr_t addr)
return 0;
}
-static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_gp_timer_readh(void *opaque, Phys addr)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
uint32_t ret;
@@ -338,7 +338,7 @@ static uint32_t omap_gp_timer_readh(void *opaque,
target_phys_addr_t addr)
}
}
-static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_gp_timer_write(void *opaque, Phys addr,
uint32_t value)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
@@ -438,7 +438,7 @@ static void omap_gp_timer_write(void *opaque,
target_phys_addr_t addr,
}
}
-static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
+static void omap_gp_timer_writeh(void *opaque, Phys addr,
uint32_t value)
{
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
diff --git a/hw/omap_i2c.c b/hw/omap_i2c.c
index 5ec422c..70fecdf 100644
--- a/hw/omap_i2c.c
+++ b/hw/omap_i2c.c
@@ -141,7 +141,7 @@ void omap_i2c_reset(struct omap_i2c_s *s)
s->test = 0;
}
-static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_i2c_read(void *opaque, Phys addr)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
@@ -240,7 +240,7 @@ static uint32_t omap_i2c_read(void *opaque,
target_phys_addr_t addr)
return 0;
}
-static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
+static void omap_i2c_write(void *opaque, Phys addr,
uint32_t value)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
@@ -382,7 +382,7 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t
addr,
}
}
-static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
+static void omap_i2c_writeb(void *opaque, Phys addr,
uint32_t value)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
@@ -427,7 +427,7 @@ static void omap_i2c_writeb(void *opaque,
target_phys_addr_t addr,
};
struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq,
qemu_irq *dma,
omap_clk clk)
diff --git a/hw/omap_intc.c b/hw/omap_intc.c
index fc53ec7..296dc17 100644
--- a/hw/omap_intc.c
+++ b/hw/omap_intc.c
@@ -145,7 +145,7 @@ static void omap_set_intr_noedge(void *opaque, int irq, int
req)
bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
}
-static uint64_t omap_inth_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_inth_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
@@ -223,7 +223,7 @@ static uint64_t omap_inth_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_inth_write(void *opaque, target_phys_addr_t addr,
+static void omap_inth_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
@@ -385,7 +385,7 @@ static int omap_intc_init(SysBusDevice *dev)
}
};
-static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap2_inth_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
@@ -466,7 +466,7 @@ static uint64_t omap2_inth_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
+static void omap2_inth_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
diff --git a/hw/omap_l4.c b/hw/omap_l4.c
index dbad7f6..22e54b4 100644
--- a/hw/omap_l4.c
+++ b/hw/omap_l4.c
@@ -22,13 +22,13 @@
struct omap_l4_s {
MemoryRegion *address_space;
- target_phys_addr_t base;
+ Phys base;
int ta_num;
struct omap_target_agent_s ta[0];
};
struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
- target_phys_addr_t base, int ta_num)
+ Phys base, int ta_num)
{
struct omap_l4_s *bus = g_malloc0(
sizeof(*bus) + ta_num * sizeof(*bus->ta));
@@ -40,19 +40,19 @@ struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
return bus;
}
-target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
+Phys omap_l4_region_base(struct omap_target_agent_s *ta,
int region)
{
return ta->bus->base + ta->start[region].offset;
}
-target_phys_addr_t omap_l4_region_size(struct omap_target_agent_s *ta,
+Phys omap_l4_region_size(struct omap_target_agent_s *ta,
int region)
{
return ta->start[region].size;
}
-static uint64_t omap_l4ta_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_l4ta_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
@@ -76,7 +76,7 @@ static uint64_t omap_l4ta_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
+static void omap_l4ta_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
@@ -143,10 +143,10 @@ struct omap_target_agent_s *omap_l4ta_get(struct
omap_l4_s *bus,
return ta;
}
-target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta,
+Phys omap_l4_attach(struct omap_target_agent_s *ta,
int region, MemoryRegion *mr)
{
- target_phys_addr_t base;
+ Phys base;
if (region < 0 || region >= ta->regions) {
fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
diff --git a/hw/omap_lcdc.c b/hw/omap_lcdc.c
index f265306..a7073b9 100644
--- a/hw/omap_lcdc.c
+++ b/hw/omap_lcdc.c
@@ -117,7 +117,7 @@ static void omap_update_display(void *opaque)
draw_line_func draw_line;
int size, height, first, last;
int width, linesize, step, bpp, frame_offset;
- target_phys_addr_t frame_base;
+ Phys frame_base;
if (!omap_lcd || omap_lcd->plm == 1 ||
!omap_lcd->enable ||
!ds_get_bits_per_pixel(omap_lcd->state))
@@ -325,7 +325,7 @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) {
}
}
-static uint64_t omap_lcdc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_lcdc_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
@@ -358,7 +358,7 @@ static uint64_t omap_lcdc_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
+static void omap_lcdc_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
@@ -431,7 +431,7 @@ void omap_lcdc_reset(struct omap_lcd_panel_s *s)
}
struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq,
struct omap_dma_lcd_channel_s *dma,
omap_clk clk)
diff --git a/hw/omap_mmc.c b/hw/omap_mmc.c
index aec0285..c4b7819 100644
--- a/hw/omap_mmc.c
+++ b/hw/omap_mmc.c
@@ -306,7 +306,7 @@ void omap_mmc_reset(struct omap_mmc_s *host)
host->clkdiv = 0;
}
-static uint64_t omap_mmc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t omap_mmc_read(void *opaque, Phys offset,
unsigned size)
{
uint16_t i;
@@ -399,7 +399,7 @@ static uint64_t omap_mmc_read(void *opaque,
target_phys_addr_t offset,
return 0;
}
-static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
+static void omap_mmc_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
int i;
@@ -572,7 +572,7 @@ static void omap_mmc_cover_cb(void *opaque, int line, int
level)
}
}
-struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
+struct omap_mmc_s *omap_mmc_init(Phys base,
MemoryRegion *sysmem,
BlockDriverState *bd,
qemu_irq irq, qemu_irq dma[], omap_clk clk)
diff --git a/hw/omap_sdrc.c b/hw/omap_sdrc.c
index 784e326..a36b46c 100644
--- a/hw/omap_sdrc.c
+++ b/hw/omap_sdrc.c
@@ -31,7 +31,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s)
s->config = 0x10;
}
-static uint64_t omap_sdrc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_sdrc_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
@@ -86,7 +86,7 @@ static uint64_t omap_sdrc_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
+static void omap_sdrc_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
@@ -154,7 +154,7 @@ static void omap_sdrc_write(void *opaque,
target_phys_addr_t addr,
};
struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
- target_phys_addr_t base)
+ Phys base)
{
struct omap_sdrc_s *s = (struct omap_sdrc_s *)
g_malloc0(sizeof(struct omap_sdrc_s));
diff --git a/hw/omap_spi.c b/hw/omap_spi.c
index 8f2b697..1db524b 100644
--- a/hw/omap_spi.c
+++ b/hw/omap_spi.c
@@ -130,7 +130,7 @@ void omap_mcspi_reset(struct omap_mcspi_s *s)
omap_mcspi_interrupt_update(s);
}
-static uint64_t omap_mcspi_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mcspi_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
@@ -204,7 +204,7 @@ static uint64_t omap_mcspi_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
+static void omap_mcspi_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c
index 4e8ec4a..a326d48 100644
--- a/hw/omap_sx1.c
+++ b/hw/omap_sx1.c
@@ -59,7 +59,7 @@
* - 1 RTC
*/
-static uint64_t static_read(void *opaque, target_phys_addr_t offset,
+static uint64_t static_read(void *opaque, Phys offset,
unsigned size)
{
uint32_t *val = (uint32_t *) opaque;
@@ -68,7 +68,7 @@ static uint64_t static_read(void *opaque, target_phys_addr_t
offset,
return *val >> ((offset & mask) << 3);
}
-static void static_write(void *opaque, target_phys_addr_t offset,
+static void static_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
#ifdef SPY
diff --git a/hw/omap_synctimer.c b/hw/omap_synctimer.c
index 367f26e..fd35a5a 100644
--- a/hw/omap_synctimer.c
+++ b/hw/omap_synctimer.c
@@ -36,7 +36,7 @@ void omap_synctimer_reset(struct omap_synctimer_s *s)
s->val = omap_synctimer_read(s);
}
-static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_synctimer_readw(void *opaque, Phys addr)
{
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
@@ -52,7 +52,7 @@ static uint32_t omap_synctimer_readw(void *opaque,
target_phys_addr_t addr)
return 0;
}
-static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_synctimer_readh(void *opaque, Phys addr)
{
struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
uint32_t ret;
@@ -66,7 +66,7 @@ static uint32_t omap_synctimer_readh(void *opaque,
target_phys_addr_t addr)
}
}
-static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
+static void omap_synctimer_write(void *opaque, Phys addr,
uint32_t value)
{
OMAP_BAD_REG(addr);
diff --git a/hw/omap_tap.c b/hw/omap_tap.c
index 0277c73..eaafaad 100644
--- a/hw/omap_tap.c
+++ b/hw/omap_tap.c
@@ -22,7 +22,7 @@
#include "omap.h"
/* TEST-Chip-level TAP */
-static uint64_t omap_tap_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_tap_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
@@ -91,7 +91,7 @@ static uint64_t omap_tap_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_tap_write(void *opaque, target_phys_addr_t addr,
+static void omap_tap_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
if (size != 4) {
diff --git a/hw/omap_uart.c b/hw/omap_uart.c
index 167d5c4..96d0655 100644
--- a/hw/omap_uart.c
+++ b/hw/omap_uart.c
@@ -27,7 +27,7 @@
/* UARTs */
struct omap_uart_s {
MemoryRegion iomem;
- target_phys_addr_t base;
+ Phys base;
SerialState *serial; /* TODO */
struct omap_target_agent_s *ta;
omap_clk fclk;
@@ -51,7 +51,7 @@ void omap_uart_reset(struct omap_uart_s *s)
s->clksel = 0;
}
-struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
+struct omap_uart_s *omap_uart_init(Phys base,
qemu_irq irq, omap_clk fclk, omap_clk iclk,
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr)
@@ -69,7 +69,7 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
return s;
}
-static uint64_t omap_uart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_uart_read(void *opaque, Phys addr,
unsigned size)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
@@ -107,7 +107,7 @@ static uint64_t omap_uart_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void omap_uart_write(void *opaque, target_phys_addr_t addr,
+static void omap_uart_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
@@ -165,7 +165,7 @@ struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
qemu_irq txdma, qemu_irq rxdma,
const char *label, CharDriverState *chr)
{
- target_phys_addr_t base = omap_l4_attach(ta, 0, NULL);
+ Phys base = omap_l4_attach(ta, 0, NULL);
struct omap_uart_s *s = omap_uart_init(base, irq,
fclk, iclk, txdma, rxdma, label, chr);
diff --git a/hw/onenand.c b/hw/onenand.c
index 33c9718..d829e75 100644
--- a/hw/onenand.c
+++ b/hw/onenand.c
@@ -42,7 +42,7 @@
uint16_t ver;
} id;
int shift;
- target_phys_addr_t base;
+ Phys base;
qemu_irq intr;
qemu_irq rdy;
BlockDriverState *bdrv;
@@ -588,7 +588,7 @@ static void onenand_command(OneNANDState *s)
onenand_intr_update(s);
}
-static uint64_t onenand_read(void *opaque, target_phys_addr_t addr,
+static uint64_t onenand_read(void *opaque, Phys addr,
unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
@@ -653,7 +653,7 @@ static uint64_t onenand_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void onenand_write(void *opaque, target_phys_addr_t addr,
+static void onenand_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
@@ -760,7 +760,7 @@ static int onenand_initfn(SysBusDevice *dev)
OneNANDState *s = (OneNANDState *)dev;
uint32_t size = 1 << (24 + ((s->id.dev >> 4) & 7));
void *ram;
- s->base = (target_phys_addr_t)-1;
+ s->base = (Phys)-1;
s->rdy = NULL;
s->blocks = size >> BLOCK_SHIFT;
s->secs = size >> 9;
diff --git a/hw/opencores_eth.c b/hw/opencores_eth.c
index f7cc1b4..89f675a 100644
--- a/hw/opencores_eth.c
+++ b/hw/opencores_eth.c
@@ -553,7 +553,7 @@ static void open_eth_check_start_xmit(OpenEthState *s)
}
static uint64_t open_eth_reg_read(void *opaque,
- target_phys_addr_t addr, unsigned int size)
+ Phys addr, unsigned int size)
{
static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = {
};
@@ -645,7 +645,7 @@ static void open_eth_mii_tx_host_write(OpenEthState *s,
uint32_t val)
}
static void open_eth_reg_write(void *opaque,
- target_phys_addr_t addr, uint64_t val, unsigned int size)
+ Phys addr, uint64_t val, unsigned int size)
{
static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = {
[MODER] = open_eth_moder_host_write,
@@ -669,7 +669,7 @@ static void open_eth_reg_write(void *opaque,
}
static uint64_t open_eth_desc_read(void *opaque,
- target_phys_addr_t addr, unsigned int size)
+ Phys addr, unsigned int size)
{
OpenEthState *s = opaque;
uint64_t v = 0;
@@ -681,7 +681,7 @@ static uint64_t open_eth_desc_read(void *opaque,
}
static void open_eth_desc_write(void *opaque,
- target_phys_addr_t addr, uint64_t val, unsigned int size)
+ Phys addr, uint64_t val, unsigned int size)
{
OpenEthState *s = opaque;
diff --git a/hw/openpic.c b/hw/openpic.c
index 22fc275..039d98e 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -167,9 +167,9 @@ static int get_current_cpu(void)
return cpu_single_env->cpu_index;
}
-static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t
addr,
+static uint32_t openpic_cpu_read_internal(void *opaque, Phys addr,
int idx);
-static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
+static void openpic_cpu_write_internal(void *opaque, Phys addr,
uint32_t val, int idx);
enum {
@@ -585,7 +585,7 @@ static void write_mailbox_register (openpic_t *opp, int
n_mbx,
#endif
#endif /* 0 : Code provision for Intel model */
-static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void openpic_gbl_write (void *opaque, Phys addr, uint32_t val)
{
openpic_t *opp = opaque;
IRQ_dst_t *dst;
@@ -649,7 +649,7 @@ static void openpic_gbl_write (void *opaque,
target_phys_addr_t addr, uint32_t v
}
}
-static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
+static uint32_t openpic_gbl_read (void *opaque, Phys addr)
{
openpic_t *opp = opaque;
uint32_t retval;
@@ -812,7 +812,7 @@ static uint32_t openpic_src_read (void *opaque, uint32_t
addr)
return retval;
}
-static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
+static void openpic_cpu_write_internal(void *opaque, Phys addr,
uint32_t val, int idx)
{
openpic_t *opp = opaque;
@@ -872,12 +872,12 @@ static void openpic_cpu_write_internal(void *opaque,
target_phys_addr_t addr,
}
}
-static void openpic_cpu_write(void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void openpic_cpu_write(void *opaque, Phys addr, uint32_t val)
{
openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
}
-static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t
addr,
+static uint32_t openpic_cpu_read_internal(void *opaque, Phys addr,
int idx)
{
openpic_t *opp = opaque;
@@ -953,18 +953,18 @@ static uint32_t openpic_cpu_read_internal(void *opaque,
target_phys_addr_t addr,
return retval;
}
-static uint32_t openpic_cpu_read(void *opaque, target_phys_addr_t addr)
+static uint32_t openpic_cpu_read(void *opaque, Phys addr)
{
return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
}
static void openpic_buggy_write (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ Phys addr, uint32_t val)
{
printf("Invalid OPENPIC write access !\n");
}
-static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
+static uint32_t openpic_buggy_read (void *opaque, Phys addr)
{
printf("Invalid OPENPIC read access !\n");
@@ -972,7 +972,7 @@ static uint32_t openpic_buggy_read (void *opaque,
target_phys_addr_t addr)
}
static void openpic_writel (void *opaque,
- target_phys_addr_t addr, uint32_t val)
+ Phys addr, uint32_t val)
{
openpic_t *opp = opaque;
@@ -993,7 +993,7 @@ static void openpic_writel (void *opaque,
}
}
-static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
+static uint32_t openpic_readl (void *opaque,Phys addr)
{
openpic_t *opp = opaque;
uint32_t retval;
@@ -1017,7 +1017,7 @@ static uint32_t openpic_readl (void
*opaque,target_phys_addr_t addr)
return retval;
}
-static uint64_t openpic_read(void *opaque, target_phys_addr_t addr,
+static uint64_t openpic_read(void *opaque, Phys addr,
unsigned size)
{
openpic_t *opp = opaque;
@@ -1028,7 +1028,7 @@ static uint64_t openpic_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void openpic_write(void *opaque, target_phys_addr_t addr,
+static void openpic_write(void *opaque, Phys addr,
uint64_t data, unsigned size)
{
openpic_t *opp = opaque;
@@ -1307,7 +1307,7 @@ static void mpic_reset (void *opaque)
mpp->glbc = 0x00000000;
}
-static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void mpic_timer_write (void *opaque, Phys addr, uint32_t val)
{
openpic_t *mpp = opaque;
int idx, cpu;
@@ -1340,7 +1340,7 @@ static void mpic_timer_write (void *opaque,
target_phys_addr_t addr, uint32_t va
}
}
-static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_timer_read (void *opaque, Phys addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
@@ -1375,7 +1375,7 @@ static uint32_t mpic_timer_read (void *opaque,
target_phys_addr_t addr)
return retval;
}
-static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
+static void mpic_src_ext_write (void *opaque, Phys addr,
uint32_t val)
{
openpic_t *mpp = opaque;
@@ -1398,7 +1398,7 @@ static void mpic_src_ext_write (void *opaque,
target_phys_addr_t addr,
}
}
-static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_src_ext_read (void *opaque, Phys addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
@@ -1425,7 +1425,7 @@ static uint32_t mpic_src_ext_read (void *opaque,
target_phys_addr_t addr)
return retval;
}
-static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
+static void mpic_src_int_write (void *opaque, Phys addr,
uint32_t val)
{
openpic_t *mpp = opaque;
@@ -1448,7 +1448,7 @@ static void mpic_src_int_write (void *opaque,
target_phys_addr_t addr,
}
}
-static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_src_int_read (void *opaque, Phys addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
@@ -1475,7 +1475,7 @@ static uint32_t mpic_src_int_read (void *opaque,
target_phys_addr_t addr)
return retval;
}
-static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
+static void mpic_src_msg_write (void *opaque, Phys addr,
uint32_t val)
{
openpic_t *mpp = opaque;
@@ -1498,7 +1498,7 @@ static void mpic_src_msg_write (void *opaque,
target_phys_addr_t addr,
}
}
-static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_src_msg_read (void *opaque, Phys addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
@@ -1525,7 +1525,7 @@ static uint32_t mpic_src_msg_read (void *opaque,
target_phys_addr_t addr)
return retval;
}
-static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
+static void mpic_src_msi_write (void *opaque, Phys addr,
uint32_t val)
{
openpic_t *mpp = opaque;
@@ -1547,7 +1547,7 @@ static void mpic_src_msi_write (void *opaque,
target_phys_addr_t addr,
}
}
}
-static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
+static uint32_t mpic_src_msi_read (void *opaque, Phys addr)
{
openpic_t *mpp = opaque;
uint32_t retval;
@@ -1672,7 +1672,7 @@ static uint32_t mpic_src_msi_read (void *opaque,
target_phys_addr_t addr)
.endianness = DEVICE_BIG_ENDIAN,
};
-qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
+qemu_irq *mpic_init (MemoryRegion *address_space, Phys base,
int nb_cpus, qemu_irq **irqs, qemu_irq irq_out)
{
openpic_t *mpp;
@@ -1680,7 +1680,7 @@ static uint32_t mpic_src_msi_read (void *opaque,
target_phys_addr_t addr)
struct {
const char *name;
MemoryRegionOps const *ops;
- target_phys_addr_t start_addr;
+ Phys start_addr;
ram_addr_t size;
} const list[] = {
{"glb", &mpic_glb_ops, MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
diff --git a/hw/openpic.h b/hw/openpic.h
index 715f084..5dad8ca 100644
--- a/hw/openpic.h
+++ b/hw/openpic.h
@@ -13,6 +13,6 @@ enum {
qemu_irq *openpic_init (PCIBus *bus, MemoryRegion **pmem, int nb_cpus,
qemu_irq **irqs, qemu_irq irq_out);
-qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
+qemu_irq *mpic_init (MemoryRegion *address_space, Phys base,
int nb_cpus, qemu_irq **irqs, qemu_irq irq_out);
#endif /* __OPENPIC_H__ */
diff --git a/hw/palm.c b/hw/palm.c
index b1252ab..d193530 100644
--- a/hw/palm.c
+++ b/hw/palm.c
@@ -27,25 +27,25 @@
#include "loader.h"
#include "exec-memory.h"
-static uint32_t static_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t static_readb(void *opaque, Phys offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 3) << 3);
}
-static uint32_t static_readh(void *opaque, target_phys_addr_t offset)
+static uint32_t static_readh(void *opaque, Phys offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 1) << 3);
}
-static uint32_t static_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t static_readw(void *opaque, Phys offset)
{
uint32_t *val = (uint32_t *) opaque;
return *val >> ((offset & 0) << 3);
}
-static void static_write(void *opaque, target_phys_addr_t offset,
+static void static_write(void *opaque, Phys offset,
uint32_t value)
{
#ifdef SPY
diff --git a/hw/parallel.c b/hw/parallel.c
index c4c5dbe..3f68814 100644
--- a/hw/parallel.c
+++ b/hw/parallel.c
@@ -511,7 +511,7 @@ static int parallel_isa_initfn(ISADevice *dev)
}
/* Memory mapped interface */
-static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readb (void *opaque, Phys addr)
{
ParallelState *s = opaque;
@@ -519,14 +519,14 @@ static uint32_t parallel_mm_readb (void *opaque,
target_phys_addr_t addr)
}
static void parallel_mm_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
ParallelState *s = opaque;
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
}
-static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readw (void *opaque, Phys addr)
{
ParallelState *s = opaque;
@@ -534,14 +534,14 @@ static uint32_t parallel_mm_readw (void *opaque,
target_phys_addr_t addr)
}
static void parallel_mm_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
ParallelState *s = opaque;
parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
}
-static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t parallel_mm_readl (void *opaque, Phys addr)
{
ParallelState *s = opaque;
@@ -549,7 +549,7 @@ static uint32_t parallel_mm_readl (void *opaque,
target_phys_addr_t addr)
}
static void parallel_mm_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
ParallelState *s = opaque;
@@ -566,7 +566,7 @@ static void parallel_mm_writel (void *opaque,
/* If fd is zero, it means that the parallel device uses the console */
bool parallel_mm_init(MemoryRegion *address_space,
- target_phys_addr_t base, int it_shift, qemu_irq irq,
+ Phys base, int it_shift, qemu_irq irq,
CharDriverState *chr)
{
ParallelState *s;
diff --git a/hw/pc.c b/hw/pc.c
index 85304cf..390e738 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -661,13 +661,13 @@ static void load_linux(void *fw_cfg,
const char *kernel_filename,
const char *initrd_filename,
const char *kernel_cmdline,
- target_phys_addr_t max_ram_size)
+ Phys max_ram_size)
{
uint16_t protocol;
int setup_size, kernel_size, initrd_size = 0, cmdline_size;
uint32_t initrd_max;
uint8_t header[8192], *setup, *kernel, *initrd_data;
- target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
+ Phys real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
FILE *f;
char *vmode;
diff --git a/hw/pc.h b/hw/pc.h
index 13e41f1..ee60ecb 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -17,7 +17,7 @@
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
CharDriverState *chr);
SerialState *serial_mm_init(MemoryRegion *address_space,
- target_phys_addr_t base, int it_shift,
+ Phys base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, enum device_endian);
static inline bool serial_isa_init(ISABus *bus, int index,
@@ -57,7 +57,7 @@ static inline bool parallel_init(ISABus *bus, int index,
CharDriverState *chr)
}
bool parallel_mm_init(MemoryRegion *address_space,
- target_phys_addr_t base, int it_shift, qemu_irq irq,
+ Phys base, int it_shift, qemu_irq irq,
CharDriverState *chr);
/* i8259.c */
@@ -120,7 +120,7 @@ void vmmouse_set_data(const uint32_t *data);
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
MemoryRegion *region, ram_addr_t size,
- target_phys_addr_t mask);
+ Phys mask);
void i8042_isa_mouse_fake_event(void *opaque);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
@@ -187,10 +187,10 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int
*piix_devfn,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- target_phys_addr_t pci_hole_start,
- target_phys_addr_t pci_hole_size,
- target_phys_addr_t pci_hole64_start,
- target_phys_addr_t pci_hole64_size,
+ Phys pci_hole_start,
+ Phys pci_hole_size,
+ Phys pci_hole64_start,
+ Phys pci_hole64_size,
MemoryRegion *pci_memory,
MemoryRegion *ram_memory);
@@ -220,8 +220,8 @@ static inline DeviceState *isa_vga_init(ISABus *bus)
}
DeviceState *pci_vga_init(PCIBus *bus);
-int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift,
+int isa_vga_mm_init(Phys vram_base,
+ Phys ctrl_base, int it_shift,
MemoryRegion *address_space);
/* cirrus_vga.c */
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index b70431f..7b22080 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -142,7 +142,7 @@ static void pc_init1(MemoryRegion *system_memory,
below_4g_mem_size,
0x100000000ULL - below_4g_mem_size,
0x100000000ULL + above_4g_mem_size,
- (sizeof(target_phys_addr_t) == 4
+ (sizeof(Phys) == 4
? 0
: ((uint64_t)1 << 62)),
pci_memory, ram_memory);
diff --git a/hw/pci.h b/hw/pci.h
index 625e717..f5e95e4 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -531,7 +531,7 @@ PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
dma_addr_t *plen, DMADirection dir)
{
- target_phys_addr_t len = *plen;
+ Phys len = *plen;
void *buf;
buf = cpu_physical_memory_map(addr, &len, dir ==
DMA_DIRECTION_FROM_DEVICE);
diff --git a/hw/pci_host.c b/hw/pci_host.c
index 44c6c20..bb85160 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -94,7 +94,7 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
return val;
}
-static void pci_host_config_write(void *opaque, target_phys_addr_t addr,
+static void pci_host_config_write(void *opaque, Phys addr,
uint64_t val, unsigned len)
{
PCIHostState *s = opaque;
@@ -104,7 +104,7 @@ static void pci_host_config_write(void *opaque,
target_phys_addr_t addr,
s->config_reg = val;
}
-static uint64_t pci_host_config_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pci_host_config_read(void *opaque, Phys addr,
unsigned len)
{
PCIHostState *s = opaque;
@@ -115,7 +115,7 @@ static uint64_t pci_host_config_read(void *opaque,
target_phys_addr_t addr,
return val;
}
-static void pci_host_data_write(void *opaque, target_phys_addr_t addr,
+static void pci_host_data_write(void *opaque, Phys addr,
uint64_t val, unsigned len)
{
PCIHostState *s = opaque;
@@ -126,7 +126,7 @@ static void pci_host_data_write(void *opaque,
target_phys_addr_t addr,
}
static uint64_t pci_host_data_read(void *opaque,
- target_phys_addr_t addr, unsigned len)
+ Phys addr, unsigned len)
{
PCIHostState *s = opaque;
uint32_t val;
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index 28bbe72..4670ba9 100644
--- a/hw/pcie_host.c
+++ b/hw/pcie_host.c
@@ -53,7 +53,7 @@
PCIE_MMCFG_DEVFN(mmcfg_addr));
}
-static void pcie_mmcfg_data_write(void *opaque, target_phys_addr_t mmcfg_addr,
+static void pcie_mmcfg_data_write(void *opaque, Phys mmcfg_addr,
uint64_t val, unsigned len)
{
PCIExpressHost *e = opaque;
@@ -76,7 +76,7 @@ static void pcie_mmcfg_data_write(void *opaque,
target_phys_addr_t mmcfg_addr,
}
static uint64_t pcie_mmcfg_data_read(void *opaque,
- target_phys_addr_t mmcfg_addr,
+ Phys mmcfg_addr,
unsigned len)
{
PCIExpressHost *e = opaque;
@@ -105,7 +105,7 @@ static uint64_t pcie_mmcfg_data_read(void *opaque,
};
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
-#define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL)
+#define PCIE_BASE_ADDR_UNMAPPED ((Phys)-1ULL)
int pcie_host_init(PCIExpressHost *e, uint32_t size)
{
@@ -127,7 +127,7 @@ void pcie_host_mmcfg_unmap(PCIExpressHost *e)
}
}
-void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr)
+void pcie_host_mmcfg_map(PCIExpressHost *e, Phys addr)
{
e->base_addr = addr;
memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
@@ -135,7 +135,7 @@ void pcie_host_mmcfg_map(PCIExpressHost *e,
target_phys_addr_t addr)
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr)
+ Phys addr)
{
pcie_host_mmcfg_unmap(e);
if (enable) {
diff --git a/hw/pcie_host.h b/hw/pcie_host.h
index 0074508..9bc54c9 100644
--- a/hw/pcie_host.h
+++ b/hw/pcie_host.h
@@ -30,10 +30,10 @@ struct PCIExpressHost {
/* express part */
/* base address where MMCONFIG area is mapped. */
- target_phys_addr_t base_addr;
+ Phys base_addr;
/* the size of MMCONFIG area. It's host bridge dependent */
- target_phys_addr_t size;
+ Phys size;
/* MMCONFIG mmio area */
MemoryRegion mmio;
@@ -41,9 +41,9 @@ struct PCIExpressHost {
int pcie_host_init(PCIExpressHost *e, uint32_t size);
void pcie_host_mmcfg_unmap(PCIExpressHost *e);
-void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr);
+void pcie_host_mmcfg_map(PCIExpressHost *e, Phys addr);
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr);
+ Phys addr);
#endif /* PCIE_HOST_H */
diff --git a/hw/pckbd.c b/hw/pckbd.c
index 06b40c5..a3597e3 100644
--- a/hw/pckbd.c
+++ b/hw/pckbd.c
@@ -139,7 +139,7 @@
qemu_irq irq_kbd;
qemu_irq irq_mouse;
qemu_irq *a20_out;
- target_phys_addr_t mask;
+ Phys mask;
} KBDState;
/* update irq and KBD_STAT_[MOUSE_]OBF */
@@ -380,7 +380,7 @@ static void kbd_reset(void *opaque)
};
/* Memory mapped interface */
-static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t kbd_mm_readb (void *opaque, Phys addr)
{
KBDState *s = opaque;
@@ -390,7 +390,7 @@ static uint32_t kbd_mm_readb (void *opaque,
target_phys_addr_t addr)
return kbd_read_data(s, 0) & 0xff;
}
-static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t
value)
+static void kbd_mm_writeb (void *opaque, Phys addr, uint32_t value)
{
KBDState *s = opaque;
@@ -410,7 +410,7 @@ static void kbd_mm_writeb (void *opaque, target_phys_addr_t
addr, uint32_t value
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
MemoryRegion *region, ram_addr_t size,
- target_phys_addr_t mask)
+ Phys mask)
{
KBDState *s = g_malloc0(sizeof(KBDState));
diff --git a/hw/pcnet-pci.c b/hw/pcnet-pci.c
index 4e164da..662c770 100644
--- a/hw/pcnet-pci.c
+++ b/hw/pcnet-pci.c
@@ -71,7 +71,7 @@ static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
return val;
}
-static uint64_t pcnet_ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pcnet_ioport_read(void *opaque, Phys addr,
unsigned size)
{
PCNetState *d = opaque;
@@ -98,7 +98,7 @@ static uint64_t pcnet_ioport_read(void *opaque,
target_phys_addr_t addr,
return ((uint64_t)1 << (size * 8)) - 1;
}
-static void pcnet_ioport_write(void *opaque, target_phys_addr_t addr,
+static void pcnet_ioport_write(void *opaque, Phys addr,
uint64_t data, unsigned size)
{
PCNetState *d = opaque;
@@ -130,7 +130,7 @@ static void pcnet_ioport_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void pcnet_mmio_writeb(void *opaque, Phys addr, uint32_t val)
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
@@ -141,7 +141,7 @@ static void pcnet_mmio_writeb(void *opaque,
target_phys_addr_t addr, uint32_t va
pcnet_aprom_writeb(d, addr & 0x0f, val);
}
-static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t pcnet_mmio_readb(void *opaque, Phys addr)
{
PCNetState *d = opaque;
uint32_t val = -1;
@@ -154,7 +154,7 @@ static uint32_t pcnet_mmio_readb(void *opaque,
target_phys_addr_t addr)
return val;
}
-static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void pcnet_mmio_writew(void *opaque, Phys addr, uint32_t val)
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
@@ -170,7 +170,7 @@ static void pcnet_mmio_writew(void *opaque,
target_phys_addr_t addr, uint32_t va
}
}
-static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t pcnet_mmio_readw(void *opaque, Phys addr)
{
PCNetState *d = opaque;
uint32_t val = -1;
@@ -189,7 +189,7 @@ static uint32_t pcnet_mmio_readw(void *opaque,
target_phys_addr_t addr)
return val;
}
-static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void pcnet_mmio_writel(void *opaque, Phys addr, uint32_t val)
{
PCNetState *d = opaque;
#ifdef PCNET_DEBUG_IO
@@ -207,7 +207,7 @@ static void pcnet_mmio_writel(void *opaque,
target_phys_addr_t addr, uint32_t va
}
}
-static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t pcnet_mmio_readl(void *opaque, Phys addr)
{
PCNetState *d = opaque;
uint32_t val;
@@ -252,13 +252,13 @@ static uint32_t pcnet_mmio_readl(void *opaque,
target_phys_addr_t addr)
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t
addr,
+static void pci_physical_memory_write(void *dma_opaque, Phys addr,
uint8_t *buf, int len, int do_bswap)
{
pci_dma_write(dma_opaque, addr, buf, len);
}
-static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
+static void pci_physical_memory_read(void *dma_opaque, Phys addr,
uint8_t *buf, int len, int do_bswap)
{
pci_dma_read(dma_opaque, addr, buf, len);
diff --git a/hw/pcnet.c b/hw/pcnet.c
index cba253b..da90320 100644
--- a/hw/pcnet.c
+++ b/hw/pcnet.c
@@ -292,7 +292,7 @@ struct pcnet_RMD {
GET_FIELD((R)->msg_length, RMDM, ZEROS))
static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd,
- target_phys_addr_t addr)
+ Phys addr)
{
if (!BCR_SSIZE32(s)) {
struct {
@@ -322,7 +322,7 @@ static inline void pcnet_tmd_load(PCNetState *s, struct
pcnet_TMD *tmd,
}
static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd,
- target_phys_addr_t addr)
+ Phys addr)
{
if (!BCR_SSIZE32(s)) {
struct {
@@ -358,7 +358,7 @@ static inline void pcnet_tmd_store(PCNetState *s, const
struct pcnet_TMD *tmd,
}
static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd,
- target_phys_addr_t addr)
+ Phys addr)
{
if (!BCR_SSIZE32(s)) {
struct {
@@ -388,7 +388,7 @@ static inline void pcnet_rmd_load(PCNetState *s, struct
pcnet_RMD *rmd,
}
static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd,
- target_phys_addr_t addr)
+ Phys addr)
{
if (!BCR_SSIZE32(s)) {
struct {
@@ -659,7 +659,7 @@ static inline int ladr_match(PCNetState *s, const uint8_t
*buf, int size)
return 0;
}
-static inline target_phys_addr_t pcnet_rdra_addr(PCNetState *s, int idx)
+static inline Phys pcnet_rdra_addr(PCNetState *s, int idx)
{
while (idx < 1) idx += CSR_RCVRL(s);
return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8));
@@ -898,19 +898,19 @@ static void pcnet_rdte_poll(PCNetState *s)
if (s->rdra) {
int bad = 0;
#if 1
- target_phys_addr_t crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
- target_phys_addr_t nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
- target_phys_addr_t nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
+ Phys crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
+ Phys nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
+ Phys nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
#else
- target_phys_addr_t crda = s->rdra +
+ Phys crda = s->rdra +
(CSR_RCVRL(s) - CSR_RCVRC(s)) *
(BCR_SWSTYLE(s) ? 16 : 8 );
int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1;
- target_phys_addr_t nrda = s->rdra +
+ Phys nrda = s->rdra +
(CSR_RCVRL(s) - nrdc) *
(BCR_SWSTYLE(s) ? 16 : 8 );
int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1;
- target_phys_addr_t nnrd = s->rdra +
+ Phys nnrd = s->rdra +
(CSR_RCVRL(s) - nnrc) *
(BCR_SWSTYLE(s) ? 16 : 8 );
#endif
@@ -970,7 +970,7 @@ static int pcnet_tdte_poll(PCNetState *s)
{
s->csr[34] = s->csr[35] = 0;
if (s->tdra) {
- target_phys_addr_t cxda = s->tdra +
+ Phys cxda = s->tdra +
(CSR_XMTRL(s) - CSR_XMTRC(s)) *
(BCR_SWSTYLE(s) ? 16 : 8);
int bad = 0;
@@ -1050,7 +1050,7 @@ ssize_t pcnet_receive(VLANClientState *nc, const uint8_t
*buf, size_t size_)
if (!(CSR_CRST(s) & 0x8000) && s->rdra) {
struct pcnet_RMD rmd;
int rcvrc = CSR_RCVRC(s)-1,i;
- target_phys_addr_t nrda;
+ Phys nrda;
for (i = CSR_RCVRL(s)-1; i > 0; i--, rcvrc--) {
if (rcvrc <= 1)
rcvrc = CSR_RCVRL(s);
@@ -1078,7 +1078,7 @@ ssize_t pcnet_receive(VLANClientState *nc, const uint8_t
*buf, size_t size_)
CSR_MISSC(s)++;
} else {
uint8_t *src = s->buffer;
- target_phys_addr_t crda = CSR_CRDA(s);
+ Phys crda = CSR_CRDA(s);
struct pcnet_RMD rmd;
int pktcount = 0;
@@ -1118,7 +1118,7 @@ ssize_t pcnet_receive(VLANClientState *nc, const uint8_t
*buf, size_t size_)
#define PCNET_RECV_STORE() do { \
int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),remaining); \
- target_phys_addr_t rbadr = PHYSADDR(s, rmd.rbadr); \
+ Phys rbadr = PHYSADDR(s, rmd.rbadr); \
s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \
src += count; remaining -= count; \
SET_FIELD(&rmd.status, RMDS, OWN, 0); \
@@ -1129,7 +1129,7 @@ ssize_t pcnet_receive(VLANClientState *nc, const uint8_t
*buf, size_t size_)
remaining = size;
PCNET_RECV_STORE();
if ((remaining > 0) && CSR_NRDA(s)) {
- target_phys_addr_t nrda = CSR_NRDA(s);
+ Phys nrda = CSR_NRDA(s);
#ifdef PCNET_DEBUG_RMD
PRINT_RMD(&rmd);
#endif
@@ -1206,7 +1206,7 @@ void pcnet_set_link_status(VLANClientState *nc)
static void pcnet_transmit(PCNetState *s)
{
- target_phys_addr_t xmit_cxda = 0;
+ Phys xmit_cxda = 0;
int count = CSR_XMTRL(s)-1;
int add_crc = 0;
diff --git a/hw/pcnet.h b/hw/pcnet.h
index edc81c9..dcb124b 100644
--- a/hw/pcnet.h
+++ b/hw/pcnet.h
@@ -41,9 +41,9 @@ struct PCNetState_st {
MemoryRegion mmio;
uint8_t buffer[4096];
qemu_irq irq;
- void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr,
+ void (*phys_mem_read)(void *dma_opaque, Phys addr,
uint8_t *buf, int len, int do_bswap);
- void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr,
+ void (*phys_mem_write)(void *dma_opaque, Phys addr,
uint8_t *buf, int len, int do_bswap);
void *dma_opaque;
int tx_busy;
diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c
index 98978f8..10fb5e1 100644
--- a/hw/petalogix_ml605_mmu.c
+++ b/hw/petalogix_ml605_mmu.c
@@ -72,10 +72,10 @@ static void main_cpu_reset(void *opaque)
}
#define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
-static int petalogix_load_device_tree(target_phys_addr_t addr,
+static int petalogix_load_device_tree(Phys addr,
uint32_t ramsize,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size,
+ Phys initrd_base,
+ Phys initrd_size,
const char *kernel_cmdline)
{
char *path;
@@ -148,7 +148,7 @@ static uint64_t translate_kernel_address(void *opaque,
uint64_t addr)
int kernel_size;
DriveInfo *dinfo;
int i;
- target_phys_addr_t ddr_base = MEMORY_BASEADDR;
+ Phys ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
@@ -227,7 +227,7 @@ static uint64_t translate_kernel_address(void *opaque,
uint64_t addr)
/* If it wasn't an ELF image, try an u-boot image. */
if (kernel_size < 0) {
- target_phys_addr_t uentry, loadaddr;
+ Phys uentry, loadaddr;
kernel_size = load_uimage(kernel_filename, &uentry, &loadaddr, 0);
boot_info.bootstrap_pc = uentry;
diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c
index d448a41..e64a934 100644
--- a/hw/petalogix_s3adsp1800_mmu.c
+++ b/hw/petalogix_s3adsp1800_mmu.c
@@ -60,10 +60,10 @@ static void main_cpu_reset(void *opaque)
}
#define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb"
-static int petalogix_load_device_tree(target_phys_addr_t addr,
+static int petalogix_load_device_tree(Phys addr,
uint32_t ramsize,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size,
+ Phys initrd_base,
+ Phys initrd_size,
const char *kernel_cmdline)
{
char *path;
@@ -125,7 +125,7 @@ static uint64_t translate_kernel_address(void *opaque,
uint64_t addr)
int kernel_size;
DriveInfo *dinfo;
int i;
- target_phys_addr_t ddr_base = 0x90000000;
+ Phys ddr_base = 0x90000000;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
@@ -192,7 +192,7 @@ static uint64_t translate_kernel_address(void *opaque,
uint64_t addr)
/* If it wasn't an ELF image, try an u-boot image. */
if (kernel_size < 0) {
- target_phys_addr_t uentry, loadaddr;
+ Phys uentry, loadaddr;
kernel_size = load_uimage(kernel_filename, &uentry, &loadaddr, 0);
boot_info.bootstrap_pc = uentry;
diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
index ee0c3ba..cfaf937 100644
--- a/hw/pflash_cfi01.c
+++ b/hw/pflash_cfi01.c
@@ -60,9 +60,9 @@
struct pflash_t {
BlockDriverState *bs;
- target_phys_addr_t base;
- target_phys_addr_t sector_len;
- target_phys_addr_t total_len;
+ Phys base;
+ Phys sector_len;
+ Phys total_len;
int width;
int wcycle; /* if 0, the flash is read normally */
int bypass;
@@ -72,7 +72,7 @@ struct pflash_t {
uint16_t ident[4];
uint8_t cfi_len;
uint8_t cfi_table[0x52];
- target_phys_addr_t counter;
+ Phys counter;
unsigned int writeblock_size;
QEMUTimer *timer;
MemoryRegion mem;
@@ -95,10 +95,10 @@ static void pflash_timer (void *opaque)
pfl->cmd = 0;
}
-static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
+static uint32_t pflash_read (pflash_t *pfl, Phys offset,
int width, int be)
{
- target_phys_addr_t boff;
+ Phys boff;
uint32_t ret;
uint8_t *p;
@@ -211,7 +211,7 @@ static void pflash_update(pflash_t *pfl, int offset,
}
}
-static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset,
+static inline void pflash_data_write(pflash_t *pfl, Phys offset,
uint32_t value, int width, int be)
{
uint8_t *p = pfl->storage;
@@ -249,7 +249,7 @@ static inline void pflash_data_write(pflash_t *pfl,
target_phys_addr_t offset,
}
-static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
+static void pflash_write(pflash_t *pfl, Phys offset,
uint32_t value, int width, int be)
{
uint8_t *p;
@@ -377,7 +377,7 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t
offset,
pfl->status |= 0x80;
if (!pfl->counter) {
- target_phys_addr_t mask = pfl->writeblock_size - 1;
+ Phys mask = pfl->writeblock_size - 1;
mask = ~mask;
DPRINTF("%s: block write finished\n", __func__);
@@ -430,57 +430,57 @@ static void pflash_write(pflash_t *pfl,
target_phys_addr_t offset,
}
-static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readb_be(void *opaque, Phys addr)
{
return pflash_read(opaque, addr, 1, 1);
}
-static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readb_le(void *opaque, Phys addr)
{
return pflash_read(opaque, addr, 1, 0);
}
-static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readw_be(void *opaque, Phys addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2, 1);
}
-static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readw_le(void *opaque, Phys addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2, 0);
}
-static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_be(void *opaque, Phys addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4, 1);
}
-static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_le(void *opaque, Phys addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4, 0);
}
-static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writeb_be(void *opaque, Phys addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 1);
}
-static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writeb_le(void *opaque, Phys addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 0);
}
-static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writew_be(void *opaque, Phys addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -488,7 +488,7 @@ static void pflash_writew_be(void *opaque,
target_phys_addr_t addr,
pflash_write(pfl, addr, value, 2, 1);
}
-static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writew_le(void *opaque, Phys addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -496,7 +496,7 @@ static void pflash_writew_le(void *opaque,
target_phys_addr_t addr,
pflash_write(pfl, addr, value, 2, 0);
}
-static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writel_be(void *opaque, Phys addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -504,7 +504,7 @@ static void pflash_writel_be(void *opaque,
target_phys_addr_t addr,
pflash_write(pfl, addr, value, 4, 1);
}
-static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writel_le(void *opaque, Phys addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -564,16 +564,16 @@ static int ctz32 (uint32_t n)
return ret;
}
-pflash_t *pflash_cfi01_register(target_phys_addr_t base,
+pflash_t *pflash_cfi01_register(Phys base,
DeviceState *qdev, const char *name,
- target_phys_addr_t size,
+ Phys size,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, int be)
{
pflash_t *pfl;
- target_phys_addr_t total_len;
+ Phys total_len;
int ret;
total_len = sector_len * nb_blocs;
diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c
index a9e88b9..c63ce63 100644
--- a/hw/pflash_cfi02.c
+++ b/hw/pflash_cfi02.c
@@ -55,7 +55,7 @@
struct pflash_t {
BlockDriverState *bs;
- target_phys_addr_t base;
+ Phys base;
uint32_t sector_len;
uint32_t chip_len;
int mappings;
@@ -88,7 +88,7 @@ struct pflash_t {
static void pflash_setup_mappings(pflash_t *pfl)
{
unsigned i;
- target_phys_addr_t size = memory_region_size(&pfl->orig_mem);
+ Phys size = memory_region_size(&pfl->orig_mem);
memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
@@ -120,10 +120,10 @@ static void pflash_timer (void *opaque)
pfl->cmd = 0;
}
-static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
+static uint32_t pflash_read (pflash_t *pfl, Phys offset,
int width, int be)
{
- target_phys_addr_t boff;
+ Phys boff;
uint32_t ret;
uint8_t *p;
@@ -240,10 +240,10 @@ static void pflash_update(pflash_t *pfl, int offset,
}
}
-static void pflash_write (pflash_t *pfl, target_phys_addr_t offset,
+static void pflash_write (pflash_t *pfl, Phys offset,
uint32_t value, int width, int be)
{
- target_phys_addr_t boff;
+ Phys boff;
uint8_t *p;
uint8_t cmd;
@@ -470,57 +470,57 @@ static void pflash_write (pflash_t *pfl,
target_phys_addr_t offset,
}
-static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readb_be(void *opaque, Phys addr)
{
return pflash_read(opaque, addr, 1, 1);
}
-static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readb_le(void *opaque, Phys addr)
{
return pflash_read(opaque, addr, 1, 0);
}
-static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readw_be(void *opaque, Phys addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2, 1);
}
-static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readw_le(void *opaque, Phys addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 2, 0);
}
-static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_be(void *opaque, Phys addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4, 1);
}
-static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
+static uint32_t pflash_readl_le(void *opaque, Phys addr)
{
pflash_t *pfl = opaque;
return pflash_read(pfl, addr, 4, 0);
}
-static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writeb_be(void *opaque, Phys addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 1);
}
-static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writeb_le(void *opaque, Phys addr,
uint32_t value)
{
pflash_write(opaque, addr, value, 1, 0);
}
-static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writew_be(void *opaque, Phys addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -528,7 +528,7 @@ static void pflash_writew_be(void *opaque,
target_phys_addr_t addr,
pflash_write(pfl, addr, value, 2, 1);
}
-static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writew_le(void *opaque, Phys addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -536,7 +536,7 @@ static void pflash_writew_le(void *opaque,
target_phys_addr_t addr,
pflash_write(pfl, addr, value, 2, 0);
}
-static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
+static void pflash_writel_be(void *opaque, Phys addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -544,7 +544,7 @@ static void pflash_writel_be(void *opaque,
target_phys_addr_t addr,
pflash_write(pfl, addr, value, 4, 1);
}
-static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
+static void pflash_writel_le(void *opaque, Phys addr,
uint32_t value)
{
pflash_t *pfl = opaque;
@@ -604,9 +604,9 @@ static int ctz32 (uint32_t n)
return ret;
}
-pflash_t *pflash_cfi02_register(target_phys_addr_t base,
+pflash_t *pflash_cfi02_register(Phys base,
DeviceState *qdev, const char *name,
- target_phys_addr_t size,
+ Phys size,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 3652522..f82e50a 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -256,10 +256,10 @@ static int i440fx_initfn(PCIDevice *dev)
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- target_phys_addr_t pci_hole_start,
- target_phys_addr_t pci_hole_size,
- target_phys_addr_t pci_hole64_start,
- target_phys_addr_t pci_hole64_size,
+ Phys pci_hole_start,
+ Phys pci_hole_size,
+ Phys pci_hole64_start,
+ Phys pci_hole64_size,
MemoryRegion *pci_address_space,
MemoryRegion *ram_memory)
{
@@ -338,10 +338,10 @@ static int i440fx_initfn(PCIDevice *dev)
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- target_phys_addr_t pci_hole_start,
- target_phys_addr_t pci_hole_size,
- target_phys_addr_t pci_hole64_start,
- target_phys_addr_t pci_hole64_size,
+ Phys pci_hole_start,
+ Phys pci_hole_size,
+ Phys pci_hole64_start,
+ Phys pci_hole64_size,
MemoryRegion *pci_memory, MemoryRegion *ram_memory)
{
diff --git a/hw/pl011.c b/hw/pl011.c
index 1b05d76..43210d3 100644
--- a/hw/pl011.c
+++ b/hw/pl011.c
@@ -54,7 +54,7 @@ static void pl011_update(pl011_state *s)
qemu_set_irq(s->irq, flags != 0);
}
-static uint64_t pl011_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl011_read(void *opaque, Phys offset,
unsigned size)
{
pl011_state *s = (pl011_state *)opaque;
@@ -124,7 +124,7 @@ static void pl011_set_read_trigger(pl011_state *s)
s->read_trigger = 1;
}
-static void pl011_write(void *opaque, target_phys_addr_t offset,
+static void pl011_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
pl011_state *s = (pl011_state *)opaque;
diff --git a/hw/pl022.c b/hw/pl022.c
index d43e4a2..5f41b0e 100644
--- a/hw/pl022.c
+++ b/hw/pl022.c
@@ -131,7 +131,7 @@ static void pl022_xfer(pl022_state *s)
pl022_update(s);
}
-static uint64_t pl022_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl022_read(void *opaque, Phys offset,
unsigned size)
{
pl022_state *s = (pl022_state *)opaque;
@@ -174,7 +174,7 @@ static uint64_t pl022_read(void *opaque, target_phys_addr_t
offset,
}
}
-static void pl022_write(void *opaque, target_phys_addr_t offset,
+static void pl022_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
pl022_state *s = (pl022_state *)opaque;
diff --git a/hw/pl031.c b/hw/pl031.c
index a007ff0..8262714 100644
--- a/hw/pl031.c
+++ b/hw/pl031.c
@@ -106,7 +106,7 @@ static void pl031_set_alarm(pl031_state *s)
}
}
-static uint64_t pl031_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl031_read(void *opaque, Phys offset,
unsigned size)
{
pl031_state *s = (pl031_state *)opaque;
@@ -142,7 +142,7 @@ static uint64_t pl031_read(void *opaque, target_phys_addr_t
offset,
return 0;
}
-static void pl031_write(void * opaque, target_phys_addr_t offset,
+static void pl031_write(void * opaque, Phys offset,
uint64_t value, unsigned size)
{
pl031_state *s = (pl031_state *)opaque;
diff --git a/hw/pl041.c b/hw/pl041.c
index 4585ccf..87c55ec 100644
--- a/hw/pl041.c
+++ b/hw/pl041.c
@@ -97,7 +97,7 @@
#if defined(PL041_DEBUG_LEVEL)
-static const char *get_reg_name(target_phys_addr_t offset)
+static const char *get_reg_name(Phys offset)
{
if (offset <= PL041_dr1_7) {
return pl041_regs_name[offset >> 2];
@@ -327,7 +327,7 @@ static void pl041_request_data(void *opaque)
pl041_isr1_update(s);
}
-static uint64_t pl041_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl041_read(void *opaque, Phys offset,
unsigned size)
{
pl041_state *s = (pl041_state *)opaque;
@@ -361,7 +361,7 @@ static uint64_t pl041_read(void *opaque, target_phys_addr_t
offset,
return value;
}
-static void pl041_write(void *opaque, target_phys_addr_t offset,
+static void pl041_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
pl041_state *s = (pl041_state *)opaque;
diff --git a/hw/pl050.c b/hw/pl050.c
index 8182a1c..af8b0aa 100644
--- a/hw/pl050.c
+++ b/hw/pl050.c
@@ -58,7 +58,7 @@ static void pl050_update(void *opaque, int level)
qemu_set_irq(s->irq, raise);
}
-static uint64_t pl050_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl050_read(void *opaque, Phys offset,
unsigned size)
{
pl050_state *s = (pl050_state *)opaque;
@@ -100,7 +100,7 @@ static uint64_t pl050_read(void *opaque, target_phys_addr_t
offset,
}
}
-static void pl050_write(void *opaque, target_phys_addr_t offset,
+static void pl050_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
pl050_state *s = (pl050_state *)opaque;
diff --git a/hw/pl061.c b/hw/pl061.c
index f33ae84..9604d4b 100644
--- a/hw/pl061.c
+++ b/hw/pl061.c
@@ -113,7 +113,7 @@ static void pl061_update(pl061_state *s)
/* FIXME: Implement input interrupts. */
}
-static uint64_t pl061_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl061_read(void *opaque, Phys offset,
unsigned size)
{
pl061_state *s = (pl061_state *)opaque;
@@ -169,7 +169,7 @@ static uint64_t pl061_read(void *opaque, target_phys_addr_t
offset,
}
}
-static void pl061_write(void *opaque, target_phys_addr_t offset,
+static void pl061_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
pl061_state *s = (pl061_state *)opaque;
diff --git a/hw/pl080.c b/hw/pl080.c
index e001df9..59f160b 100644
--- a/hw/pl080.c
+++ b/hw/pl080.c
@@ -218,7 +218,7 @@ static void pl080_run(pl080_state *s)
}
}
-static uint64_t pl080_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl080_read(void *opaque, Phys offset,
unsigned size)
{
pl080_state *s = (pl080_state *)opaque;
@@ -286,7 +286,7 @@ static uint64_t pl080_read(void *opaque, target_phys_addr_t
offset,
}
}
-static void pl080_write(void *opaque, target_phys_addr_t offset,
+static void pl080_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
pl080_state *s = (pl080_state *)opaque;
diff --git a/hw/pl110.c b/hw/pl110.c
index 0e1f415..dedd89f 100644
--- a/hw/pl110.c
+++ b/hw/pl110.c
@@ -305,7 +305,7 @@ static void pl110_update(pl110_state *s)
/* TODO: Implement interrupts. */
}
-static uint64_t pl110_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl110_read(void *opaque, Phys offset,
unsigned size)
{
pl110_state *s = (pl110_state *)opaque;
@@ -354,7 +354,7 @@ static uint64_t pl110_read(void *opaque, target_phys_addr_t
offset,
}
}
-static void pl110_write(void *opaque, target_phys_addr_t offset,
+static void pl110_write(void *opaque, Phys offset,
uint64_t val, unsigned size)
{
pl110_state *s = (pl110_state *)opaque;
diff --git a/hw/pl181.c b/hw/pl181.c
index b79aa41..831948d 100644
--- a/hw/pl181.c
+++ b/hw/pl181.c
@@ -285,7 +285,7 @@ static void pl181_fifo_run(pl181_state *s)
}
}
-static uint64_t pl181_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl181_read(void *opaque, Phys offset,
unsigned size)
{
pl181_state *s = (pl181_state *)opaque;
@@ -368,7 +368,7 @@ static uint64_t pl181_read(void *opaque, target_phys_addr_t
offset,
}
}
-static void pl181_write(void *opaque, target_phys_addr_t offset,
+static void pl181_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
pl181_state *s = (pl181_state *)opaque;
diff --git a/hw/pl190.c b/hw/pl190.c
index 6fc2656..2ad1904 100644
--- a/hw/pl190.c
+++ b/hw/pl190.c
@@ -85,7 +85,7 @@ static void pl190_update_vectors(pl190_state *s)
pl190_update(s);
}
-static uint64_t pl190_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pl190_read(void *opaque, Phys offset,
unsigned size)
{
pl190_state *s = (pl190_state *)opaque;
@@ -142,7 +142,7 @@ static uint64_t pl190_read(void *opaque, target_phys_addr_t
offset,
}
}
-static void pl190_write(void *opaque, target_phys_addr_t offset,
+static void pl190_write(void *opaque, Phys offset,
uint64_t val, unsigned size)
{
pl190_state *s = (pl190_state *)opaque;
diff --git a/hw/ppc405.h b/hw/ppc405.h
index d8fdf09..32f67de 100644
--- a/hw/ppc405.h
+++ b/hw/ppc405.h
@@ -61,20 +61,20 @@ ram_addr_t ppc405_set_bootinfo (CPUState *env,
ppc4xx_bd_info_t *bd,
CPUState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
- target_phys_addr_t ram_bases[4],
- target_phys_addr_t ram_sizes[4],
+ Phys ram_bases[4],
+ Phys ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init);
CPUState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
- target_phys_addr_t ram_bases[2],
- target_phys_addr_t ram_sizes[2],
+ Phys ram_bases[2],
+ Phys ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init);
/* IBM STBxxx microcontrollers */
CPUState *ppc_stb025_init (MemoryRegion ram_memories[2],
- target_phys_addr_t ram_bases[2],
- target_phys_addr_t ram_sizes[2],
+ Phys ram_bases[2],
+ Phys ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
ram_addr_t *offsetp);
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index 476775d..9f8c0c0 100644
--- a/hw/ppc405_boards.c
+++ b/hw/ppc405_boards.c
@@ -60,7 +60,7 @@ struct ref405ep_fpga_t {
uint8_t reg1;
};
-static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t ref405ep_fpga_readb (void *opaque, Phys addr)
{
ref405ep_fpga_t *fpga;
uint32_t ret;
@@ -82,7 +82,7 @@ static uint32_t ref405ep_fpga_readb (void *opaque,
target_phys_addr_t addr)
}
static void ref405ep_fpga_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
ref405ep_fpga_t *fpga;
@@ -99,7 +99,7 @@ static void ref405ep_fpga_writeb (void *opaque,
}
}
-static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t ref405ep_fpga_readw (void *opaque, Phys addr)
{
uint32_t ret;
@@ -110,13 +110,13 @@ static uint32_t ref405ep_fpga_readw (void *opaque,
target_phys_addr_t addr)
}
static void ref405ep_fpga_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
}
-static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t ref405ep_fpga_readl (void *opaque, Phys addr)
{
uint32_t ret;
@@ -129,7 +129,7 @@ static uint32_t ref405ep_fpga_readl (void *opaque,
target_phys_addr_t addr)
}
static void ref405ep_fpga_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
@@ -185,7 +185,7 @@ static void ref405ep_init (ram_addr_t ram_size,
MemoryRegion *sram = g_new(MemoryRegion, 1);
ram_addr_t bdloc;
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
- target_phys_addr_t ram_bases[2], ram_sizes[2];
+ Phys ram_bases[2], ram_sizes[2];
target_ulong sram_size;
long bios_size;
//int phy_addr = 0;
@@ -390,7 +390,7 @@ struct taihu_cpld_t {
uint8_t reg1;
};
-static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t taihu_cpld_readb (void *opaque, Phys addr)
{
taihu_cpld_t *cpld;
uint32_t ret;
@@ -412,7 +412,7 @@ static uint32_t taihu_cpld_readb (void *opaque,
target_phys_addr_t addr)
}
static void taihu_cpld_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
taihu_cpld_t *cpld;
@@ -429,7 +429,7 @@ static void taihu_cpld_writeb (void *opaque,
}
}
-static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t taihu_cpld_readw (void *opaque, Phys addr)
{
uint32_t ret;
@@ -440,13 +440,13 @@ static uint32_t taihu_cpld_readw (void *opaque,
target_phys_addr_t addr)
}
static void taihu_cpld_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
}
-static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t taihu_cpld_readl (void *opaque, Phys addr)
{
uint32_t ret;
@@ -459,7 +459,7 @@ static uint32_t taihu_cpld_readl (void *opaque,
target_phys_addr_t addr)
}
static void taihu_cpld_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
@@ -507,7 +507,7 @@ static void taihu_405ep_init(ram_addr_t ram_size,
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *bios;
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
- target_phys_addr_t ram_bases[2], ram_sizes[2];
+ Phys ram_bases[2], ram_sizes[2];
long bios_size;
target_ulong kernel_base, initrd_base;
long kernel_size, initrd_size;
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 98079fa..45e3586 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -265,7 +265,7 @@ struct ppc4xx_opba_t {
uint8_t pr;
};
-static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t opba_readb (void *opaque, Phys addr)
{
ppc4xx_opba_t *opba;
uint32_t ret;
@@ -290,7 +290,7 @@ static uint32_t opba_readb (void *opaque,
target_phys_addr_t addr)
}
static void opba_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
ppc4xx_opba_t *opba;
@@ -311,7 +311,7 @@ static void opba_writeb (void *opaque,
}
}
-static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t opba_readw (void *opaque, Phys addr)
{
uint32_t ret;
@@ -325,7 +325,7 @@ static uint32_t opba_readw (void *opaque,
target_phys_addr_t addr)
}
static void opba_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -335,7 +335,7 @@ static void opba_writew (void *opaque,
opba_writeb(opaque, addr + 1, value);
}
-static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t opba_readl (void *opaque, Phys addr)
{
uint32_t ret;
@@ -349,7 +349,7 @@ static uint32_t opba_readl (void *opaque,
target_phys_addr_t addr)
}
static void opba_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -376,7 +376,7 @@ static void ppc4xx_opba_reset (void *opaque)
opba->pr = 0x11;
}
-static void ppc4xx_opba_init(target_phys_addr_t base)
+static void ppc4xx_opba_init(Phys base)
{
ppc4xx_opba_t *opba;
@@ -732,7 +732,7 @@ struct ppc405_gpio_t {
uint32_t isr1l;
};
-static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc405_gpio_readb (void *opaque, Phys addr)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -742,7 +742,7 @@ static uint32_t ppc405_gpio_readb (void *opaque,
target_phys_addr_t addr)
}
static void ppc405_gpio_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -750,7 +750,7 @@ static void ppc405_gpio_writeb (void *opaque,
#endif
}
-static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc405_gpio_readw (void *opaque, Phys addr)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -760,7 +760,7 @@ static uint32_t ppc405_gpio_readw (void *opaque,
target_phys_addr_t addr)
}
static void ppc405_gpio_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -768,7 +768,7 @@ static void ppc405_gpio_writew (void *opaque,
#endif
}
-static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc405_gpio_readl (void *opaque, Phys addr)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -778,7 +778,7 @@ static uint32_t ppc405_gpio_readl (void *opaque,
target_phys_addr_t addr)
}
static void ppc405_gpio_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -798,7 +798,7 @@ static void ppc405_gpio_reset (void *opaque)
{
}
-static void ppc405_gpio_init(target_phys_addr_t base)
+static void ppc405_gpio_init(Phys base)
{
ppc405_gpio_t *gpio;
@@ -1004,7 +1004,7 @@ struct ppc4xx_i2c_t {
uint8_t directcntl;
};
-static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_i2c_readb (void *opaque, Phys addr)
{
ppc4xx_i2c_t *i2c;
uint32_t ret;
@@ -1072,7 +1072,7 @@ static uint32_t ppc4xx_i2c_readb (void *opaque,
target_phys_addr_t addr)
}
static void ppc4xx_i2c_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
ppc4xx_i2c_t *i2c;
@@ -1131,7 +1131,7 @@ static void ppc4xx_i2c_writeb (void *opaque,
}
}
-static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_i2c_readw (void *opaque, Phys addr)
{
uint32_t ret;
@@ -1145,7 +1145,7 @@ static uint32_t ppc4xx_i2c_readw (void *opaque,
target_phys_addr_t addr)
}
static void ppc4xx_i2c_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -1155,7 +1155,7 @@ static void ppc4xx_i2c_writew (void *opaque,
ppc4xx_i2c_writeb(opaque, addr + 1, value);
}
-static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_i2c_readl (void *opaque, Phys addr)
{
uint32_t ret;
@@ -1171,7 +1171,7 @@ static uint32_t ppc4xx_i2c_readl (void *opaque,
target_phys_addr_t addr)
}
static void ppc4xx_i2c_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -1207,7 +1207,7 @@ static void ppc4xx_i2c_reset (void *opaque)
i2c->directcntl = 0x0F;
}
-static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
+static void ppc405_i2c_init(Phys base, qemu_irq irq)
{
ppc4xx_i2c_t *i2c;
@@ -1239,7 +1239,7 @@ struct ppc4xx_gpt_t {
uint32_t mask[5];
};
-static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_gpt_readb (void *opaque, Phys addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -1249,7 +1249,7 @@ static uint32_t ppc4xx_gpt_readb (void *opaque,
target_phys_addr_t addr)
}
static void ppc4xx_gpt_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -1258,7 +1258,7 @@ static void ppc4xx_gpt_writeb (void *opaque,
/* XXX: generate a bus fault */
}
-static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_gpt_readw (void *opaque, Phys addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -1268,7 +1268,7 @@ static uint32_t ppc4xx_gpt_readw (void *opaque,
target_phys_addr_t addr)
}
static void ppc4xx_gpt_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
@@ -1329,7 +1329,7 @@ static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
/* XXX: TODO */
}
-static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t ppc4xx_gpt_readl (void *opaque, Phys addr)
{
ppc4xx_gpt_t *gpt;
uint32_t ret;
@@ -1385,7 +1385,7 @@ static uint32_t ppc4xx_gpt_readl (void *opaque,
target_phys_addr_t addr)
}
static void ppc4xx_gpt_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
ppc4xx_gpt_t *gpt;
int idx;
@@ -1482,7 +1482,7 @@ static void ppc4xx_gpt_reset (void *opaque)
}
}
-static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
+static void ppc4xx_gpt_init(Phys base, qemu_irq irqs[5])
{
ppc4xx_gpt_t *gpt;
int i;
@@ -2110,8 +2110,8 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t
clk_setup[7],
CPUState *ppc405cr_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[4],
- target_phys_addr_t ram_bases[4],
- target_phys_addr_t ram_sizes[4],
+ Phys ram_bases[4],
+ Phys ram_sizes[4],
uint32_t sysclk, qemu_irq **picp,
int do_init)
{
@@ -2459,8 +2459,8 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t
clk_setup[8],
CPUState *ppc405ep_init(MemoryRegion *address_space_mem,
MemoryRegion ram_memories[2],
- target_phys_addr_t ram_bases[2],
- target_phys_addr_t ram_sizes[2],
+ Phys ram_bases[2],
+ Phys ram_sizes[2],
uint32_t sysclk, qemu_irq **picp,
int do_init)
{
diff --git a/hw/ppc440.c b/hw/ppc440.c
index cd8a95d..8c72199 100644
--- a/hw/ppc440.c
+++ b/hw/ppc440.c
@@ -40,8 +40,8 @@
{
MemoryRegion *ram_memories
= g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
- target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
- target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
+ Phys ram_bases[PPC440EP_SDRAM_NR_BANKS];
+ Phys ram_sizes[PPC440EP_SDRAM_NR_BANKS];
CPUState *env;
qemu_irq *pic;
qemu_irq *irqs;
diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c
index b734e3a..4b5a735 100644
--- a/hw/ppc440_bamboo.c
+++ b/hw/ppc440_bamboo.c
@@ -32,10 +32,10 @@
#define FDT_ADDR 0x1800000
#define RAMDISK_ADDR 0x1900000
-static int bamboo_load_device_tree(target_phys_addr_t addr,
+static int bamboo_load_device_tree(Phys addr,
uint32_t ramsize,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size,
+ Phys initrd_base,
+ Phys initrd_size,
const char *kernel_cmdline)
{
int ret = -1;
@@ -114,8 +114,8 @@ static void bamboo_init(ram_addr_t ram_size,
CPUState *env;
uint64_t elf_entry;
uint64_t elf_lowaddr;
- target_phys_addr_t entry = 0;
- target_phys_addr_t loadaddr = 0;
+ Phys entry = 0;
+ Phys loadaddr = 0;
target_long initrd_size = 0;
int success;
int i;
diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h
index f969e44..a5a4177 100644
--- a/hw/ppc4xx.h
+++ b/hw/ppc4xx.h
@@ -43,20 +43,20 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
MemoryRegion ram_memories[],
- target_phys_addr_t ram_bases[],
- target_phys_addr_t ram_sizes[],
+ Phys ram_bases[],
+ Phys ram_sizes[],
const unsigned int sdram_bank_sizes[]);
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
MemoryRegion ram_memories[],
- target_phys_addr_t *ram_bases,
- target_phys_addr_t *ram_sizes,
+ Phys *ram_bases,
+ Phys *ram_sizes,
int do_init);
PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
- target_phys_addr_t config_space,
- target_phys_addr_t int_ack,
- target_phys_addr_t special_cycle,
- target_phys_addr_t registers);
+ Phys config_space,
+ Phys int_ack,
+ Phys special_cycle,
+ Phys registers);
#endif /* !defined(PPC_4XX_H) */
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index 26040ac..43617c0 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -316,8 +316,8 @@ struct ppc4xx_sdram_t {
int nbanks;
MemoryRegion containers[4]; /* used for clipping */
MemoryRegion *ram_memories;
- target_phys_addr_t ram_bases[4];
- target_phys_addr_t ram_sizes[4];
+ Phys ram_bases[4];
+ Phys ram_sizes[4];
uint32_t besr0;
uint32_t besr1;
uint32_t bear;
@@ -338,11 +338,11 @@ enum {
};
/* XXX: TOFIX: some patches have made this code become inconsistent:
- * there are type inconsistencies, mixing target_phys_addr_t, target_ulong
+ * there are type inconsistencies, mixing Phys, target_ulong
* and uint32_t
*/
-static uint32_t sdram_bcr (target_phys_addr_t ram_base,
- target_phys_addr_t ram_size)
+static uint32_t sdram_bcr (Phys ram_base,
+ Phys ram_size)
{
uint32_t bcr;
@@ -379,7 +379,7 @@ static uint32_t sdram_bcr (target_phys_addr_t ram_base,
return bcr;
}
-static inline target_phys_addr_t sdram_base(uint32_t bcr)
+static inline Phys sdram_base(uint32_t bcr)
{
return bcr & 0xFF800000;
}
@@ -636,8 +636,8 @@ static void sdram_reset (void *opaque)
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
MemoryRegion *ram_memories,
- target_phys_addr_t *ram_bases,
- target_phys_addr_t *ram_sizes,
+ Phys *ram_bases,
+ Phys *ram_sizes,
int do_init)
{
ppc4xx_sdram_t *sdram;
@@ -646,12 +646,12 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int
nbanks,
sdram->irq = irq;
sdram->nbanks = nbanks;
sdram->ram_memories = ram_memories;
- memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
+ memset(sdram->ram_bases, 0, 4 * sizeof(Phys));
memcpy(sdram->ram_bases, ram_bases,
- nbanks * sizeof(target_phys_addr_t));
- memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
+ nbanks * sizeof(Phys));
+ memset(sdram->ram_sizes, 0, 4 * sizeof(Phys));
memcpy(sdram->ram_sizes, ram_sizes,
- nbanks * sizeof(target_phys_addr_t));
+ nbanks * sizeof(Phys));
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
@@ -670,8 +670,8 @@ void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int
nbanks,
* sizes varies by SoC. */
ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
MemoryRegion ram_memories[],
- target_phys_addr_t ram_bases[],
- target_phys_addr_t ram_sizes[],
+ Phys ram_bases[],
+ Phys ram_sizes[],
const unsigned int sdram_bank_sizes[])
{
ram_addr_t size_left = ram_size;
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index 2c69210..3c72989 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -86,7 +86,7 @@ struct PPC4xxPCIState {
#define PCI_REG_SIZE 0x40
-static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pci4xx_cfgaddr_read(void *opaque, Phys addr,
unsigned size)
{
PPC4xxPCIState *ppc4xx_pci = opaque;
@@ -94,7 +94,7 @@ static uint64_t pci4xx_cfgaddr_read(void *opaque,
target_phys_addr_t addr,
return ppc4xx_pci->pci_state.config_reg;
}
-static void pci4xx_cfgaddr_write(void *opaque, target_phys_addr_t addr,
+static void pci4xx_cfgaddr_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
PPC4xxPCIState *ppc4xx_pci = opaque;
@@ -108,7 +108,7 @@ static void pci4xx_cfgaddr_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
+static void ppc4xx_pci_reg_write4(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
struct PPC4xxPCIState *pci = opaque;
@@ -176,7 +176,7 @@ static void ppc4xx_pci_reg_write4(void *opaque,
target_phys_addr_t offset,
}
}
-static uint64_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset,
+static uint64_t ppc4xx_pci_reg_read4(void *opaque, Phys offset,
unsigned size)
{
struct PPC4xxPCIState *pci = opaque;
@@ -323,10 +323,10 @@ static void ppc4xx_pci_set_irq(void *opaque, int irq_num,
int level)
/* XXX Interrupt acknowledge cycles not supported. */
PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
- target_phys_addr_t config_space,
- target_phys_addr_t int_ack,
- target_phys_addr_t special_cycle,
- target_phys_addr_t registers)
+ Phys config_space,
+ Phys int_ack,
+ Phys special_cycle,
+ Phys registers)
{
PPC4xxPCIState *controller;
static int ppc4xx_pci_id;
diff --git a/hw/ppc_mac.h b/hw/ppc_mac.h
index af75e45..f2d4a23 100644
--- a/hw/ppc_mac.h
+++ b/hw/ppc_mac.h
@@ -70,10 +70,10 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,
/* Mac NVRAM */
typedef struct MacIONVRAMState MacIONVRAMState;
-MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,
+MacIONVRAMState *macio_nvram_init (Phys size,
unsigned int it_shift);
void macio_nvram_setup_bar(MacIONVRAMState *s, MemoryRegion *bar,
- target_phys_addr_t mem_base);
+ Phys mem_base);
void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
uint32_t macio_nvram_read (void *opaque, uint32_t addr);
void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val);
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index a746c9c..f67b296 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -84,13 +84,13 @@
#endif
/* UniN device */
-static void unin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void unin_write(void *opaque, Phys addr, uint64_t value,
unsigned size)
{
UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value);
}
-static uint64_t unin_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t unin_read(void *opaque, Phys addr, unsigned size)
{
uint32_t value;
@@ -117,7 +117,7 @@ static uint64_t translate_kernel_address(void *opaque,
uint64_t addr)
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}
-static target_phys_addr_t round_page(target_phys_addr_t addr)
+static Phys round_page(Phys addr)
{
return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
}
@@ -136,7 +136,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
int linux_boot, i;
MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
- target_phys_addr_t kernel_base, initrd_base, cmdline_base = 0;
+ Phys kernel_base, initrd_base, cmdline_base = 0;
long kernel_size, initrd_size;
PCIBus *pci_bus;
MacIONVRAMState *nvr;
diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c
index 9295a34..9f54483 100644
--- a/hw/ppc_oldworld.c
+++ b/hw/ppc_oldworld.c
@@ -61,7 +61,7 @@ static uint64_t translate_kernel_address(void *opaque,
uint64_t addr)
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}
-static target_phys_addr_t round_page(target_phys_addr_t addr)
+static Phys round_page(Phys addr)
{
return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
}
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 47dab3f..d6beaea 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -116,7 +116,7 @@ static uint32_t speaker_ioport_read (void *opaque, uint32_t
addr)
/* PCI intack register */
/* Read-only register (?) */
-static void PPC_intack_write (void *opaque, target_phys_addr_t addr,
+static void PPC_intack_write (void *opaque, Phys addr,
uint64_t value, unsigned size)
{
#if 0
@@ -125,7 +125,7 @@ static void PPC_intack_write (void *opaque,
target_phys_addr_t addr,
#endif
}
-static uint64_t PPC_intack_read(void *opaque, target_phys_addr_t addr,
+static uint64_t PPC_intack_read(void *opaque, Phys addr,
unsigned size)
{
uint32_t retval = 0;
@@ -174,27 +174,27 @@ static uint64_t PPC_intack_read(void *opaque,
target_phys_addr_t addr,
} XCSR;
static void PPC_XCSR_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
static void PPC_XCSR_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
static void PPC_XCSR_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
value);
}
-static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_XCSR_readb (void *opaque, Phys addr)
{
uint32_t retval = 0;
@@ -204,7 +204,7 @@ static uint32_t PPC_XCSR_readb (void *opaque,
target_phys_addr_t addr)
return retval;
}
-static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_XCSR_readw (void *opaque, Phys addr)
{
uint32_t retval = 0;
@@ -214,7 +214,7 @@ static uint32_t PPC_XCSR_readw (void *opaque,
target_phys_addr_t addr)
return retval;
}
-static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_XCSR_readl (void *opaque, Phys addr)
{
uint32_t retval = 0;
@@ -402,8 +402,8 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t
addr)
return retval;
}
-static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
- target_phys_addr_t addr)
+static inline Phys prep_IO_address(sysctrl_t *sysctrl,
+ Phys addr)
{
if (sysctrl->contiguous_map == 0) {
/* 64 KB contiguous space for IOs */
@@ -416,7 +416,7 @@ static inline target_phys_addr_t prep_IO_address(sysctrl_t
*sysctrl,
return addr;
}
-static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
+static void PPC_prep_io_writeb (void *opaque, Phys addr,
uint32_t value)
{
sysctrl_t *sysctrl = opaque;
@@ -425,7 +425,7 @@ static void PPC_prep_io_writeb (void *opaque,
target_phys_addr_t addr,
cpu_outb(addr, value);
}
-static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_prep_io_readb (void *opaque, Phys addr)
{
sysctrl_t *sysctrl = opaque;
uint32_t ret;
@@ -436,7 +436,7 @@ static uint32_t PPC_prep_io_readb (void *opaque,
target_phys_addr_t addr)
return ret;
}
-static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
+static void PPC_prep_io_writew (void *opaque, Phys addr,
uint32_t value)
{
sysctrl_t *sysctrl = opaque;
@@ -446,7 +446,7 @@ static void PPC_prep_io_writew (void *opaque,
target_phys_addr_t addr,
cpu_outw(addr, value);
}
-static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_prep_io_readw (void *opaque, Phys addr)
{
sysctrl_t *sysctrl = opaque;
uint32_t ret;
@@ -458,7 +458,7 @@ static uint32_t PPC_prep_io_readw (void *opaque,
target_phys_addr_t addr)
return ret;
}
-static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
+static void PPC_prep_io_writel (void *opaque, Phys addr,
uint32_t value)
{
sysctrl_t *sysctrl = opaque;
@@ -468,7 +468,7 @@ static void PPC_prep_io_writel (void *opaque,
target_phys_addr_t addr,
cpu_outl(addr, value);
}
-static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_prep_io_readl (void *opaque, Phys addr)
{
sysctrl_t *sysctrl = opaque;
uint32_t ret;
@@ -570,7 +570,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
bios_size = -1;
}
if (bios_size > 0 && bios_size <= BIOS_SIZE) {
- target_phys_addr_t bios_addr;
+ Phys bios_addr;
bios_size = (bios_size + 0xfff) & ~0xfff;
bios_addr = (uint32_t)(-bios_size);
memory_region_set_readonly(bios, true);
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index d69f78c..863273c 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -59,10 +59,10 @@ struct boot_info
};
static int mpc8544_load_device_tree(CPUState *env,
- target_phys_addr_t addr,
+ Phys addr,
uint32_t ramsize,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size,
+ Phys initrd_base,
+ Phys initrd_size,
const char *kernel_cmdline)
{
int ret = -1;
@@ -173,17 +173,17 @@ static int mpc8544_load_device_tree(CPUState *env,
}
/* Create -kernel TLB entries for BookE, linearly spanning 256MB. */
-static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
+static inline Phys booke206_page_size_to_tlb(uint64_t size)
{
return ffs(size >> 10) - 1;
}
static void mmubooke_create_initial_mapping(CPUState *env,
target_ulong va,
- target_phys_addr_t pa)
+ Phys pa)
{
ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
- target_phys_addr_t size;
+ Phys size;
size = (booke206_page_size_to_tlb(256 * 1024 * 1024) << MAS1_TSIZE_SHIFT);
tlb->mas1 = MAS1_VALID | size;
@@ -234,8 +234,8 @@ static void mpc8544ds_init(ram_addr_t ram_size,
CPUState *env = NULL;
uint64_t elf_entry;
uint64_t elf_lowaddr;
- target_phys_addr_t entry=0;
- target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
+ Phys entry=0;
+ Phys loadaddr=UIMAGE_LOAD_BASE;
target_long kernel_size=0;
target_ulong dt_base = 0;
target_ulong initrd_base = 0;
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index b606206..fe90988 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -85,7 +85,7 @@ struct PPCE500PCIState {
typedef struct PPCE500PCIState PPCE500PCIState;
-static uint64_t pci_reg_read4(void *opaque, target_phys_addr_t addr,
+static uint64_t pci_reg_read4(void *opaque, Phys addr,
unsigned size)
{
PPCE500PCIState *pci = opaque;
@@ -154,7 +154,7 @@ static uint64_t pci_reg_read4(void *opaque,
target_phys_addr_t addr,
return value;
}
-static void pci_reg_write4(void *opaque, target_phys_addr_t addr,
+static void pci_reg_write4(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
PPCE500PCIState *pci = opaque;
diff --git a/hw/ppce500_spin.c b/hw/ppce500_spin.c
index df74953..45e312e 100644
--- a/hw/ppce500_spin.c
+++ b/hw/ppce500_spin.c
@@ -68,18 +68,18 @@ static void spin_reset(void *opaque)
}
/* Create -kernel TLB entries for BookE, linearly spanning 256MB. */
-static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
+static inline Phys booke206_page_size_to_tlb(uint64_t size)
{
return (ffs(size >> 10) - 1) >> 1;
}
static void mmubooke_create_initial_mapping(CPUState *env,
target_ulong va,
- target_phys_addr_t pa,
- target_phys_addr_t len)
+ Phys pa,
+ Phys len)
{
ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1);
- target_phys_addr_t size;
+ Phys size;
size = (booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT);
tlb->mas1 = MAS1_VALID | size;
@@ -93,8 +93,8 @@ static void spin_kick(void *data)
SpinKick *kick = data;
CPUState *env = kick->env;
SpinInfo *curspin = kick->spin;
- target_phys_addr_t map_size = 64 * 1024 * 1024;
- target_phys_addr_t map_start;
+ Phys map_size = 64 * 1024 * 1024;
+ Phys map_start;
cpu_synchronize_state(env);
stl_p(&curspin->pir, env->spr[SPR_PIR]);
@@ -115,7 +115,7 @@ static void spin_kick(void *data)
qemu_cpu_kick(env);
}
-static void spin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
+static void spin_write(void *opaque, Phys addr, uint64_t value,
unsigned len)
{
SpinState *s = opaque;
@@ -164,7 +164,7 @@ static void spin_write(void *opaque, target_phys_addr_t
addr, uint64_t value,
}
}
-static uint64_t spin_read(void *opaque, target_phys_addr_t addr, unsigned len)
+static uint64_t spin_read(void *opaque, Phys addr, unsigned len)
{
SpinState *s = opaque;
uint8_t *spin_p = &((uint8_t*)s->spin)[addr];
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index ea9fb69..3d7c079 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -29,7 +29,7 @@
typedef PCIHostState PREPPCIState;
-static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
+static inline uint32_t PPC_PCIIO_config(Phys addr)
{
int i;
@@ -40,27 +40,27 @@ static inline uint32_t PPC_PCIIO_config(target_phys_addr_t
addr)
return (addr & 0x7ff) | (i << 11);
}
-static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void PPC_PCIIO_writeb (void *opaque, Phys addr, uint32_t val)
{
PREPPCIState *s = opaque;
pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
}
-static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void PPC_PCIIO_writew (void *opaque, Phys addr, uint32_t val)
{
PREPPCIState *s = opaque;
val = bswap16(val);
pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
}
-static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t
val)
+static void PPC_PCIIO_writel (void *opaque, Phys addr, uint32_t val)
{
PREPPCIState *s = opaque;
val = bswap32(val);
pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
}
-static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_PCIIO_readb (void *opaque, Phys addr)
{
PREPPCIState *s = opaque;
uint32_t val;
@@ -68,7 +68,7 @@ static uint32_t PPC_PCIIO_readb (void *opaque,
target_phys_addr_t addr)
return val;
}
-static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_PCIIO_readw (void *opaque, Phys addr)
{
PREPPCIState *s = opaque;
uint32_t val;
@@ -77,7 +77,7 @@ static uint32_t PPC_PCIIO_readw (void *opaque,
target_phys_addr_t addr)
return val;
}
-static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t PPC_PCIIO_readl (void *opaque, Phys addr)
{
PREPPCIState *s = opaque;
uint32_t val;
diff --git a/hw/pxa.h b/hw/pxa.h
index e778739..e0f2ada 100644
--- a/hw/pxa.h
+++ b/hw/pxa.h
@@ -65,28 +65,28 @@
# define PXA2XX_INTERNAL_SIZE 0x40000
/* pxa2xx_pic.c */
-DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
+DeviceState *pxa2xx_pic_init(Phys base, CPUState *env);
/* pxa2xx_gpio.c */
-DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
+DeviceState *pxa2xx_gpio_init(Phys base,
CPUState *env, DeviceState *pic, int lines);
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
/* pxa2xx_dma.c */
-DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq);
-DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq);
+DeviceState *pxa255_dma_init(Phys base, qemu_irq irq);
+DeviceState *pxa27x_dma_init(Phys base, qemu_irq irq);
/* pxa2xx_lcd.c */
typedef struct PXA2xxLCDState PXA2xxLCDState;
PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
- target_phys_addr_t base, qemu_irq irq);
+ Phys base, qemu_irq irq);
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);
/* pxa2xx_mmci.c */
typedef struct PXA2xxMMCIState PXA2xxMMCIState;
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
BlockDriverState *bd, qemu_irq irq,
qemu_irq rx_dma, qemu_irq tx_dma);
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
@@ -95,7 +95,7 @@ void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq
readonly,
/* pxa2xx_pcmcia.c */
typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
- target_phys_addr_t base);
+ Phys base);
int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
int pxa2xx_pcmcia_dettach(void *opaque);
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
@@ -107,14 +107,14 @@ struct keymap {
};
typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq);
void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
int size);
/* pxa2xx.c */
typedef struct PXA2xxI2CState PXA2xxI2CState;
-PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
+PXA2xxI2CState *pxa2xx_i2c_init(Phys base,
qemu_irq irq, uint32_t page_size);
i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
@@ -142,16 +142,16 @@ typedef struct {
PXA2xxKeyPadState *kp;
/* Power management */
- target_phys_addr_t pm_base;
+ Phys pm_base;
uint32_t pm_regs[0x40];
/* Clock management */
- target_phys_addr_t cm_base;
+ Phys cm_base;
uint32_t cm_regs[4];
uint32_t clkcfg;
/* Memory management */
- target_phys_addr_t mm_base;
+ Phys mm_base;
uint32_t mm_regs[0x1a];
/* Performance monitoring */
diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index 6ddd500..bb9b223 100644
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -17,7 +17,7 @@
#include "blockdev.h"
static struct {
- target_phys_addr_t io_base;
+ Phys io_base;
int irqn;
} pxa255_serial[] = {
{ 0x40100000, PXA2XX_PIC_FFUART },
@@ -33,7 +33,7 @@
};
typedef struct PXASSPDef {
- target_phys_addr_t io_base;
+ Phys io_base;
int irqn;
} PXASSPDef;
@@ -88,7 +88,7 @@
#define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
#define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
-static uint64_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_pm_read(void *opaque, Phys addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -107,7 +107,7 @@ static uint64_t pxa2xx_pm_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_pm_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -160,7 +160,7 @@ static void pxa2xx_pm_write(void *opaque,
target_phys_addr_t addr,
#define OSCC 0x08 /* Oscillator Configuration register */
#define CCSR 0x0c /* Core Clock Status register */
-static uint64_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_cm_read(void *opaque, Phys addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -181,7 +181,7 @@ static uint64_t pxa2xx_cm_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_cm_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -454,7 +454,7 @@ static void pxa2xx_cp14_write(void *opaque, int op2, int
reg, int crm,
#define BSCNTR3 0x60 /* Memory Buffer Strength Control
register 3 */
#define SA1110 0x64 /* SA-1110 Memory Compatibility register */
-static uint64_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_mm_read(void *opaque, Phys addr,
unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -471,7 +471,7 @@ static uint64_t pxa2xx_mm_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_mm_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
PXA2xxState *s = (PXA2xxState *) opaque;
@@ -616,7 +616,7 @@ static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
pxa2xx_ssp_int_update(s);
}
-static uint64_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_ssp_read(void *opaque, Phys addr,
unsigned size)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
@@ -662,7 +662,7 @@ static uint64_t pxa2xx_ssp_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_ssp_write(void *opaque, Phys addr,
uint64_t value64, unsigned size)
{
PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
@@ -992,7 +992,7 @@ static inline void pxa2xx_rtc_pi_tick(void *opaque)
pxa2xx_rtc_int_update(s);
}
-static uint64_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_rtc_read(void *opaque, Phys addr,
unsigned size)
{
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
@@ -1038,7 +1038,7 @@ static uint64_t pxa2xx_rtc_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_rtc_write(void *opaque, Phys addr,
uint64_t value64, unsigned size)
{
PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
@@ -1334,7 +1334,7 @@ static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
return 1;
}
-static uint64_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_i2c_read(void *opaque, Phys addr,
unsigned size)
{
PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
@@ -1362,7 +1362,7 @@ static uint64_t pxa2xx_i2c_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_i2c_write(void *opaque, Phys addr,
uint64_t value64, unsigned size)
{
PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
@@ -1481,7 +1481,7 @@ static int pxa2xx_i2c_slave_init(i2c_slave *i2c)
.send = pxa2xx_i2c_tx
};
-PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
+PXA2xxI2CState *pxa2xx_i2c_init(Phys base,
qemu_irq irq, uint32_t region_size)
{
DeviceState *dev;
@@ -1594,7 +1594,7 @@ static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
#define SADIV 0x60 /* Serial Audio Clock Divider register */
#define SADR 0x80 /* Serial Audio Data register */
-static uint64_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_i2s_read(void *opaque, Phys addr,
unsigned size)
{
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
@@ -1626,7 +1626,7 @@ static uint64_t pxa2xx_i2s_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_i2s_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
@@ -1728,7 +1728,7 @@ static void pxa2xx_i2s_data_req(void *opaque, int tx, int
rx)
}
static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
{
PXA2xxI2SState *s = (PXA2xxI2SState *)
@@ -1823,7 +1823,7 @@ static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
#define ICSR1 0x18 /* FICP Status register 1 */
#define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
-static uint64_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pxa2xx_fir_read(void *opaque, Phys addr,
unsigned size)
{
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
@@ -1861,7 +1861,7 @@ static uint64_t pxa2xx_fir_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
+static void pxa2xx_fir_write(void *opaque, Phys addr,
uint64_t value64, unsigned size)
{
PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
@@ -1985,7 +1985,7 @@ static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int
version_id)
}
static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
CharDriverState *chr)
{
diff --git a/hw/pxa2xx_dma.c b/hw/pxa2xx_dma.c
index cb28107..20d25c6 100644
--- a/hw/pxa2xx_dma.c
+++ b/hw/pxa2xx_dma.c
@@ -18,9 +18,9 @@
#define PXA2XX_DMA_NUM_REQUESTS 75
typedef struct {
- target_phys_addr_t descr;
- target_phys_addr_t src;
- target_phys_addr_t dest;
+ Phys descr;
+ Phys src;
+ Phys dest;
uint32_t cmd;
uint32_t state;
int request;
@@ -147,7 +147,7 @@ static inline void pxa2xx_dma_descriptor_fetch(
PXA2xxDMAState *s, int ch)
{
uint32_t desc[4];
- target_phys_addr_t daddr = s->chan[ch].descr & ~0xf;
+ Phys daddr = s->chan[ch].descr & ~0xf;
if ((s->chan[ch].descr & DDADR_BREN) && (s->chan[ch].state & DCSR_CMPST))
daddr += 32;
@@ -251,7 +251,7 @@ static void pxa2xx_dma_run(PXA2xxDMAState *s)
}
}
-static uint64_t pxa2xx_dma_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_dma_read(void *opaque, Phys offset,
unsigned size)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
@@ -310,7 +310,7 @@ static uint64_t pxa2xx_dma_read(void *opaque,
target_phys_addr_t offset,
return 7;
}
-static void pxa2xx_dma_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_dma_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
@@ -473,7 +473,7 @@ static int pxa2xx_dma_init(SysBusDevice *dev)
return 0;
}
-DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq)
+DeviceState *pxa27x_dma_init(Phys base, qemu_irq irq)
{
DeviceState *dev;
@@ -487,7 +487,7 @@ static int pxa2xx_dma_init(SysBusDevice *dev)
return dev;
}
-DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq)
+DeviceState *pxa255_dma_init(Phys base, qemu_irq irq)
{
DeviceState *dev;
diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
index cc58c40..939548d 100644
--- a/hw/pxa2xx_gpio.c
+++ b/hw/pxa2xx_gpio.c
@@ -138,7 +138,7 @@ static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
}
}
-static uint64_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_gpio_read(void *opaque, Phys offset,
unsigned size)
{
PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
@@ -190,7 +190,7 @@ static uint64_t pxa2xx_gpio_read(void *opaque,
target_phys_addr_t offset,
return 0;
}
-static void pxa2xx_gpio_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_gpio_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
@@ -248,7 +248,7 @@ static void pxa2xx_gpio_write(void *opaque,
target_phys_addr_t offset,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
+DeviceState *pxa2xx_gpio_init(Phys base,
CPUState *env, DeviceState *pic, int lines)
{
DeviceState *dev;
diff --git a/hw/pxa2xx_keypad.c b/hw/pxa2xx_keypad.c
index f86323f..261aeb2 100644
--- a/hw/pxa2xx_keypad.c
+++ b/hw/pxa2xx_keypad.c
@@ -175,7 +175,7 @@ static void pxa27x_keyboard_event (PXA2xxKeyPadState *kp,
int keycode)
return;
}
-static uint64_t pxa2xx_keypad_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_keypad_read(void *opaque, Phys offset,
unsigned size)
{
PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
@@ -237,7 +237,7 @@ static uint64_t pxa2xx_keypad_read(void *opaque,
target_phys_addr_t offset,
return 0;
}
-static void pxa2xx_keypad_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_keypad_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
PXA2xxKeyPadState *s = (PXA2xxKeyPadState *) opaque;
@@ -303,7 +303,7 @@ static void pxa2xx_keypad_write(void *opaque,
target_phys_addr_t offset,
};
PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
qemu_irq irq)
{
PXA2xxKeyPadState *s;
diff --git a/hw/pxa2xx_lcd.c b/hw/pxa2xx_lcd.c
index 5dd4ef0..20a9f34 100644
--- a/hw/pxa2xx_lcd.c
+++ b/hw/pxa2xx_lcd.c
@@ -16,15 +16,15 @@
#include "framebuffer.h"
struct DMAChannel {
- target_phys_addr_t branch;
+ Phys branch;
uint8_t up;
uint8_t palette[1024];
uint8_t pbuffer[1024];
- void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
+ void (*redraw)(PXA2xxLCDState *s, Phys addr,
int *miny, int *maxy);
- target_phys_addr_t descriptor;
- target_phys_addr_t source;
+ Phys descriptor;
+ Phys source;
uint32_t id;
uint32_t command;
};
@@ -288,7 +288,7 @@ static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s)
static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
{
PXAFrameDescriptor desc;
- target_phys_addr_t descptr;
+ Phys descptr;
int i;
for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
@@ -317,7 +317,7 @@ static void pxa2xx_descriptor_load(PXA2xxLCDState *s)
}
}
-static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_lcdc_read(void *opaque, Phys offset,
unsigned size)
{
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
@@ -411,7 +411,7 @@ static uint64_t pxa2xx_lcdc_read(void *opaque,
target_phys_addr_t offset,
return 0;
}
-static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_lcdc_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
@@ -663,7 +663,7 @@ static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch,
int bpp)
}
static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
- target_phys_addr_t addr, int *miny, int *maxy)
+ Phys addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
@@ -690,7 +690,7 @@ static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s,
}
static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
- target_phys_addr_t addr, int *miny, int *maxy)
+ Phys addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
@@ -718,7 +718,7 @@ static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s,
}
static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s,
- target_phys_addr_t addr, int *miny, int *maxy)
+ Phys addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
@@ -748,7 +748,7 @@ static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState
*s,
}
static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s,
- target_phys_addr_t addr, int *miny, int *maxy)
+ Phys addr, int *miny, int *maxy)
{
int src_width, dest_width;
drawfn fn = NULL;
@@ -802,7 +802,7 @@ static void pxa2xx_lcdc_resize(PXA2xxLCDState *s)
static void pxa2xx_update_display(void *opaque)
{
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
- target_phys_addr_t fbptr;
+ Phys fbptr;
int miny, maxy;
int ch;
if (!(s->control[0] & LCCR0_ENB))
@@ -979,7 +979,7 @@ static int pxa2xx_lcdc_post_load(void *opaque, int
version_id)
#include "pxa2xx_template.h"
PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
- target_phys_addr_t base, qemu_irq irq)
+ Phys base, qemu_irq irq)
{
PXA2xxLCDState *s;
diff --git a/hw/pxa2xx_mmci.c b/hw/pxa2xx_mmci.c
index f47c79c..0767692 100644
--- a/hw/pxa2xx_mmci.c
+++ b/hw/pxa2xx_mmci.c
@@ -212,7 +212,7 @@ static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
pxa2xx_mmci_fifo_update(s);
}
-static uint32_t pxa2xx_mmci_read(void *opaque, target_phys_addr_t offset)
+static uint32_t pxa2xx_mmci_read(void *opaque, Phys offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
uint32_t ret;
@@ -274,7 +274,7 @@ static uint32_t pxa2xx_mmci_read(void *opaque,
target_phys_addr_t offset)
}
static void pxa2xx_mmci_write(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+ Phys offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
@@ -383,21 +383,21 @@ static void pxa2xx_mmci_write(void *opaque,
}
}
-static uint32_t pxa2xx_mmci_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t pxa2xx_mmci_readb(void *opaque, Phys offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 1;
return pxa2xx_mmci_read(opaque, offset);
}
-static uint32_t pxa2xx_mmci_readh(void *opaque, target_phys_addr_t offset)
+static uint32_t pxa2xx_mmci_readh(void *opaque, Phys offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 2;
return pxa2xx_mmci_read(opaque, offset);
}
-static uint32_t pxa2xx_mmci_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t pxa2xx_mmci_readw(void *opaque, Phys offset)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 4;
@@ -405,7 +405,7 @@ static uint32_t pxa2xx_mmci_readw(void *opaque,
target_phys_addr_t offset)
}
static void pxa2xx_mmci_writeb(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+ Phys offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 1;
@@ -413,7 +413,7 @@ static void pxa2xx_mmci_writeb(void *opaque,
}
static void pxa2xx_mmci_writeh(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+ Phys offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 2;
@@ -421,7 +421,7 @@ static void pxa2xx_mmci_writeh(void *opaque,
}
static void pxa2xx_mmci_writew(void *opaque,
- target_phys_addr_t offset, uint32_t value)
+ Phys offset, uint32_t value)
{
PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
s->ac_width = 4;
@@ -519,7 +519,7 @@ static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int
version_id)
}
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
- target_phys_addr_t base,
+ Phys base,
BlockDriverState *bd, qemu_irq irq,
qemu_irq rx_dma, qemu_irq tx_dma)
{
diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c
index dc522dc..0a13bd9 100644
--- a/hw/pxa2xx_pcmcia.c
+++ b/hw/pxa2xx_pcmcia.c
@@ -24,7 +24,7 @@ struct PXA2xxPCMCIAState {
};
static uint64_t pxa2xx_pcmcia_common_read(void *opaque,
- target_phys_addr_t offset, unsigned size)
+ Phys offset, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -35,7 +35,7 @@ static uint64_t pxa2xx_pcmcia_common_read(void *opaque,
return 0;
}
-static void pxa2xx_pcmcia_common_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_pcmcia_common_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -46,7 +46,7 @@ static void pxa2xx_pcmcia_common_write(void *opaque,
target_phys_addr_t offset,
}
static uint64_t pxa2xx_pcmcia_attr_read(void *opaque,
- target_phys_addr_t offset, unsigned size)
+ Phys offset, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -57,7 +57,7 @@ static uint64_t pxa2xx_pcmcia_attr_read(void *opaque,
return 0;
}
-static void pxa2xx_pcmcia_attr_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_pcmcia_attr_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -68,7 +68,7 @@ static void pxa2xx_pcmcia_attr_write(void *opaque,
target_phys_addr_t offset,
}
static uint64_t pxa2xx_pcmcia_io_read(void *opaque,
- target_phys_addr_t offset, unsigned size)
+ Phys offset, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -79,7 +79,7 @@ static uint64_t pxa2xx_pcmcia_io_read(void *opaque,
return 0;
}
-static void pxa2xx_pcmcia_io_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_pcmcia_io_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
@@ -117,7 +117,7 @@ static void pxa2xx_pcmcia_set_irq(void *opaque, int line,
int level)
}
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
- target_phys_addr_t base)
+ Phys base)
{
PXA2xxPCMCIAState *s;
diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c
index 92effbc..c020e7c 100644
--- a/hw/pxa2xx_pic.c
+++ b/hw/pxa2xx_pic.c
@@ -116,7 +116,7 @@ static inline uint32_t pxa2xx_pic_highest(PXA2xxPICState
*s) {
return ichp;
}
-static uint64_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_pic_mem_read(void *opaque, Phys offset,
unsigned size)
{
PXA2xxPICState *s = (PXA2xxPICState *) opaque;
@@ -156,7 +156,7 @@ static uint64_t pxa2xx_pic_mem_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_pic_mem_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
PXA2xxPICState *s = (PXA2xxPICState *) opaque;
@@ -208,7 +208,7 @@ static void pxa2xx_pic_mem_write(void *opaque,
target_phys_addr_t offset,
static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm)
{
- target_phys_addr_t offset;
+ Phys offset;
if (pxa2xx_cp_reg_map[reg] == -1) {
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
@@ -222,7 +222,7 @@ static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2,
int reg, int crm)
static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm,
uint32_t value)
{
- target_phys_addr_t offset;
+ Phys offset;
if (pxa2xx_cp_reg_map[reg] == -1) {
printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
@@ -245,7 +245,7 @@ static int pxa2xx_pic_post_load(void *opaque, int
version_id)
return 0;
}
-DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
+DeviceState *pxa2xx_pic_init(Phys base, CPUState *env)
{
DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
diff --git a/hw/pxa2xx_timer.c b/hw/pxa2xx_timer.c
index 50e2678..9597884 100644
--- a/hw/pxa2xx_timer.c
+++ b/hw/pxa2xx_timer.c
@@ -149,7 +149,7 @@ static void pxa2xx_timer_update4(void *opaque, uint64_t
now_qemu, int n)
qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
}
-static uint64_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset,
+static uint64_t pxa2xx_timer_read(void *opaque, Phys offset,
unsigned size)
{
PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
@@ -227,7 +227,7 @@ static uint64_t pxa2xx_timer_read(void *opaque,
target_phys_addr_t offset,
return 0;
}
-static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
+static void pxa2xx_timer_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
int i, tm = 0;
diff --git a/hw/qdev-addr.c b/hw/qdev-addr.c
index 5ddda2d..39a4e40 100644
--- a/hw/qdev-addr.c
+++ b/hw/qdev-addr.c
@@ -6,7 +6,7 @@
static int parse_taddr(DeviceState *dev, Property *prop, const char *str)
{
- target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
+ Phys *ptr = qdev_get_prop_ptr(dev, prop);
*ptr = strtoull(str, NULL, 16);
return 0;
@@ -14,7 +14,7 @@ static int parse_taddr(DeviceState *dev, Property *prop,
const char *str)
static int print_taddr(DeviceState *dev, Property *prop, char *dest, size_t
len)
{
- target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
+ Phys *ptr = qdev_get_prop_ptr(dev, prop);
return snprintf(dest, len, "0x" TARGET_FMT_plx, *ptr);
}
@@ -22,7 +22,7 @@ static void get_taddr(DeviceState *dev, Visitor *v, void
*opaque,
const char *name, Error **errp)
{
Property *prop = opaque;
- target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
+ Phys *ptr = qdev_get_prop_ptr(dev, prop);
int64_t value;
value = *ptr;
@@ -33,7 +33,7 @@ static void set_taddr(DeviceState *dev, Visitor *v, void
*opaque,
const char *name, Error **errp)
{
Property *prop = opaque;
- target_phys_addr_t *ptr = qdev_get_prop_ptr(dev, prop);
+ Phys *ptr = qdev_get_prop_ptr(dev, prop);
Error *local_err = NULL;
int64_t value;
@@ -47,12 +47,12 @@ static void set_taddr(DeviceState *dev, Visitor *v, void
*opaque,
error_propagate(errp, local_err);
return;
}
- if ((uint64_t)value <= (uint64_t) ~(target_phys_addr_t)0) {
+ if ((uint64_t)value <= (uint64_t) ~(Phys)0) {
*ptr = value;
} else {
error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE,
dev->id?:"", name, value, (uint64_t) 0,
- (uint64_t) ~(target_phys_addr_t)0);
+ (uint64_t) ~(Phys)0);
}
}
@@ -60,14 +60,14 @@ static void set_taddr(DeviceState *dev, Visitor *v, void
*opaque,
PropertyInfo qdev_prop_taddr = {
.name = "taddr",
.type = PROP_TYPE_TADDR,
- .size = sizeof(target_phys_addr_t),
+ .size = sizeof(Phys),
.parse = parse_taddr,
.print = print_taddr,
.get = get_taddr,
.set = set_taddr,
};
-void qdev_prop_set_taddr(DeviceState *dev, const char *name,
target_phys_addr_t value)
+void qdev_prop_set_taddr(DeviceState *dev, const char *name, Phys value)
{
qdev_prop_set(dev, name, &value, PROP_TYPE_TADDR);
}
diff --git a/hw/qdev-addr.h b/hw/qdev-addr.h
index a0ddf38..b7b3229 100644
--- a/hw/qdev-addr.h
+++ b/hw/qdev-addr.h
@@ -1,5 +1,5 @@
#define DEFINE_PROP_TADDR(_n, _s, _f, _d) \
- DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_taddr, target_phys_addr_t)
+ DEFINE_PROP_DEFAULT(_n, _s, _f, _d, qdev_prop_taddr, Phys)
extern PropertyInfo qdev_prop_taddr;
-void qdev_prop_set_taddr(DeviceState *dev, const char *name,
target_phys_addr_t value);
+void qdev_prop_set_taddr(DeviceState *dev, const char *name, Phys value);
diff --git a/hw/qxl.c b/hw/qxl.c
index ac81927..ef95679 100644
--- a/hw/qxl.c
+++ b/hw/qxl.c
@@ -1133,7 +1133,7 @@ static void qxl_set_mode(PCIQXLDevice *d, int modenr, int
loadvm)
qxl_rom_set_dirty(d);
}
-static void ioport_write(void *opaque, target_phys_addr_t addr,
+static void ioport_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
PCIQXLDevice *d = opaque;
@@ -1347,7 +1347,7 @@ static void ioport_write(void *opaque, target_phys_addr_t
addr,
#endif
}
-static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
+static uint64_t ioport_read(void *opaque, Phys addr,
unsigned size)
{
PCIQXLDevice *d = opaque;
diff --git a/hw/r2d.c b/hw/r2d.c
index c80f9e3..bb2751b 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -127,7 +127,7 @@ static void r2d_fpga_irq_set(void *opaque, int n, int level)
update_irl(fpga);
}
-static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
+static uint32_t r2d_fpga_read(void *opaque, Phys addr)
{
r2d_fpga_t *s = opaque;
@@ -146,7 +146,7 @@ static uint32_t r2d_fpga_read(void *opaque,
target_phys_addr_t addr)
}
static void
-r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
+r2d_fpga_write(void *opaque, Phys addr, uint32_t value)
{
r2d_fpga_t *s = opaque;
@@ -178,7 +178,7 @@ static uint32_t r2d_fpga_read(void *opaque,
target_phys_addr_t addr)
};
static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
- target_phys_addr_t base, qemu_irq irl)
+ Phys base, qemu_irq irl)
{
r2d_fpga_t *s;
diff --git a/hw/rc4030.c b/hw/rc4030.c
index 9f39b30..59fb234 100644
--- a/hw/rc4030.c
+++ b/hw/rc4030.c
@@ -112,7 +112,7 @@ static void set_next_tick(rc4030State *s)
}
/* called for accesses to rc4030 */
-static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t rc4030_readl(void *opaque, Phys addr)
{
rc4030State *s = opaque;
uint32_t val;
@@ -250,7 +250,7 @@ static uint32_t rc4030_readl(void *opaque,
target_phys_addr_t addr)
return val;
}
-static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t rc4030_readw(void *opaque, Phys addr)
{
uint32_t v = rc4030_readl(opaque, addr & ~0x3);
if (addr & 0x2)
@@ -259,13 +259,13 @@ static uint32_t rc4030_readw(void *opaque,
target_phys_addr_t addr)
return v & 0xffff;
}
-static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t rc4030_readb(void *opaque, Phys addr)
{
uint32_t v = rc4030_readl(opaque, addr & ~0x3);
return (v >> (8 * (addr & 0x3))) & 0xff;
}
-static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rc4030_writel(void *opaque, Phys addr, uint32_t val)
{
rc4030State *s = opaque;
addr &= 0x3fff;
@@ -308,7 +308,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t
addr, uint32_t val)
case 0x0060:
/* HACK */
if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
- target_phys_addr_t dest = s->cache_ptag & ~0x1;
+ Phys dest = s->cache_ptag & ~0x1;
dest += (s->cache_maint & 0x3) << 3;
cpu_physical_memory_write(dest, &val, 4);
}
@@ -390,7 +390,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t
addr, uint32_t val)
}
}
-static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rc4030_writew(void *opaque, Phys addr, uint32_t val)
{
uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
@@ -401,7 +401,7 @@ static void rc4030_writew(void *opaque, target_phys_addr_t
addr, uint32_t val)
rc4030_writel(opaque, addr & ~0x3, val);
}
-static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void rc4030_writeb(void *opaque, Phys addr, uint32_t val)
{
uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
@@ -479,7 +479,7 @@ static void rc4030_periodic_timer(void *opaque)
qemu_irq_raise(s->timer_irq);
}
-static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t jazzio_readw(void *opaque, Phys addr)
{
rc4030State *s = opaque;
uint32_t val;
@@ -517,14 +517,14 @@ static uint32_t jazzio_readw(void *opaque,
target_phys_addr_t addr)
return val;
}
-static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t jazzio_readb(void *opaque, Phys addr)
{
uint32_t v;
v = jazzio_readw(opaque, addr & ~0x1);
return (v >> (8 * (addr & 0x1))) & 0xff;
}
-static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t jazzio_readl(void *opaque, Phys addr)
{
uint32_t v;
v = jazzio_readw(opaque, addr);
@@ -532,7 +532,7 @@ static uint32_t jazzio_readl(void *opaque,
target_phys_addr_t addr)
return v;
}
-static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void jazzio_writew(void *opaque, Phys addr, uint32_t val)
{
rc4030State *s = opaque;
addr &= 0xfff;
@@ -551,7 +551,7 @@ static void jazzio_writew(void *opaque, target_phys_addr_t
addr, uint32_t val)
}
}
-static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void jazzio_writeb(void *opaque, Phys addr, uint32_t val)
{
uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
@@ -566,7 +566,7 @@ static void jazzio_writeb(void *opaque, target_phys_addr_t
addr, uint32_t val)
jazzio_writew(opaque, addr & ~0x1, val);
}
-static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void jazzio_writel(void *opaque, Phys addr, uint32_t val)
{
jazzio_writew(opaque, addr, val & 0xffff);
jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff);
@@ -672,11 +672,11 @@ static void rc4030_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, s->itr);
}
-void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf,
int len, int is_write)
+void rc4030_dma_memory_rw(void *opaque, Phys addr, uint8_t *buf, int len, int
is_write)
{
rc4030State *s = opaque;
- target_phys_addr_t entry_addr;
- target_phys_addr_t phys_addr;
+ Phys entry_addr;
+ Phys phys_addr;
dma_pagetable_entry entry;
int index;
int ncpy, i;
@@ -713,7 +713,7 @@ void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t
addr, uint8_t *buf, i
static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int
is_write)
{
rc4030State *s = opaque;
- target_phys_addr_t dma_addr;
+ Phys dma_addr;
int dev_to_mem;
s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR |
DMA_FLAG_ADDR_INTR);
diff --git a/hw/realview.c b/hw/realview.c
index d4191e9..5cdaffb 100644
--- a/hw/realview.c
+++ b/hw/realview.c
@@ -30,7 +30,7 @@
int in;
} RealViewI2CState;
-static uint64_t realview_i2c_read(void *opaque, target_phys_addr_t offset,
+static uint64_t realview_i2c_read(void *opaque, Phys offset,
unsigned size)
{
RealViewI2CState *s = (RealViewI2CState *)opaque;
@@ -43,7 +43,7 @@ static uint64_t realview_i2c_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void realview_i2c_write(void *opaque, target_phys_addr_t offset,
+static void realview_i2c_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
RealViewI2CState *s = (RealViewI2CState *)opaque;
diff --git a/hw/rtl8139.c b/hw/rtl8139.c
index 0ae9f57..8d3c07d 100644
--- a/hw/rtl8139.c
+++ b/hw/rtl8139.c
@@ -800,7 +800,7 @@ static void rtl8139_write_buffer(RTL8139State *s, const
void *buf, int size)
static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
{
#if TARGET_PHYS_ADDR_BITS > 32
- return low | ((target_phys_addr_t)high << 32);
+ return low | ((Phys)high << 32);
#else
return low;
#endif
@@ -2474,7 +2474,7 @@ static void rtl8139_TxStatus_write(RTL8139State *s,
uint32_t txRegOffset, uint32
if (descriptor == 0 && (val & 0x8))
{
- target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] &
~0x3f, s->TxStatus[1]);
+ Phys tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f,
s->TxStatus[1]);
/* dump tally counters to specified memory location */
RTL8139TallyCounters_dma_write(s, tc_addr);
@@ -3208,33 +3208,33 @@ static uint32_t rtl8139_ioport_readl(void *opaque,
uint32_t addr)
/* */
-static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
+static void rtl8139_mmio_writeb(void *opaque, Phys addr, uint32_t val)
{
rtl8139_io_writeb(opaque, addr & 0xFF, val);
}
-static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
+static void rtl8139_mmio_writew(void *opaque, Phys addr, uint32_t val)
{
rtl8139_io_writew(opaque, addr & 0xFF, val);
}
-static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr,
uint32_t val)
+static void rtl8139_mmio_writel(void *opaque, Phys addr, uint32_t val)
{
rtl8139_io_writel(opaque, addr & 0xFF, val);
}
-static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t rtl8139_mmio_readb(void *opaque, Phys addr)
{
return rtl8139_io_readb(opaque, addr & 0xFF);
}
-static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t rtl8139_mmio_readw(void *opaque, Phys addr)
{
uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
return val;
}
-static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t rtl8139_mmio_readl(void *opaque, Phys addr)
{
uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
return val;
diff --git a/hw/s390-virtio-bus.c b/hw/s390-virtio-bus.c
index c4b9a99..6b12cbb 100644
--- a/hw/s390-virtio-bus.c
+++ b/hw/s390-virtio-bus.c
@@ -61,7 +61,7 @@ struct BusInfo s390_virtio_bus_info = {
static ram_addr_t s390_virtio_device_num_vq(VirtIOS390Device *dev);
/* length of VirtIO device pages */
-const target_phys_addr_t virtio_size = S390_DEVICE_PAGES * TARGET_PAGE_SIZE;
+const Phys virtio_size = S390_DEVICE_PAGES * TARGET_PAGE_SIZE;
VirtIOS390Bus *s390_virtio_bus_init(ram_addr_t *ram_size)
{
diff --git a/hw/s390-virtio.c b/hw/s390-virtio.c
index 2210b8a..74a7644 100644
--- a/hw/s390-virtio.c
+++ b/hw/s390-virtio.c
@@ -166,8 +166,8 @@ static void s390_init(ram_addr_t my_ram_size,
int shift = 0;
uint8_t *storage_keys;
void *virtio_region;
- target_phys_addr_t virtio_region_len;
- target_phys_addr_t virtio_region_start;
+ Phys virtio_region_len;
+ Phys virtio_region_start;
int i;
/* s390x ram size detection needs a 16bit multiplier + an increment. So
diff --git a/hw/sbi.c b/hw/sbi.c
index 8965a71..6dbc303 100644
--- a/hw/sbi.c
+++ b/hw/sbi.c
@@ -52,7 +52,7 @@ static void sbi_set_irq(void *opaque, int irq, int level)
{
}
-static uint64_t sbi_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sbi_mem_read(void *opaque, Phys addr,
unsigned size)
{
SBIState *s = opaque;
@@ -69,7 +69,7 @@ static uint64_t sbi_mem_read(void *opaque, target_phys_addr_t
addr,
return ret;
}
-static void sbi_mem_write(void *opaque, target_phys_addr_t addr,
+static void sbi_mem_write(void *opaque, Phys addr,
uint64_t val, unsigned dize)
{
SBIState *s = opaque;
diff --git a/hw/serial.c b/hw/serial.c
index d35c7a9..154583b 100644
--- a/hw/serial.c
+++ b/hw/serial.c
@@ -821,14 +821,14 @@ static int serial_isa_initfn(ISADevice *dev)
}
/* Memory mapped interface */
-static uint64_t serial_mm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t serial_mm_read(void *opaque, Phys addr,
unsigned size)
{
SerialState *s = opaque;
return serial_ioport_read(s, addr >> s->it_shift);
}
-static void serial_mm_write(void *opaque, target_phys_addr_t addr,
+static void serial_mm_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
SerialState *s = opaque;
@@ -855,7 +855,7 @@ static void serial_mm_write(void *opaque,
target_phys_addr_t addr,
};
SerialState *serial_mm_init(MemoryRegion *address_space,
- target_phys_addr_t base, int it_shift,
+ Phys base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, enum device_endian end)
{
diff --git a/hw/sh.h b/hw/sh.h
index 6488db2..67f96d0 100644
--- a/hw/sh.h
+++ b/hw/sh.h
@@ -31,7 +31,7 @@ int sh7750_register_io_device(struct SH7750State *s,
#define TMU012_FEAT_TOCR (1 << 0)
#define TMU012_FEAT_3CHAN (1 << 1)
#define TMU012_FEAT_EXTCLK (1 << 2)
-void tmu012_init(struct MemoryRegion *sysmem, target_phys_addr_t base,
+void tmu012_init(struct MemoryRegion *sysmem, Phys base,
int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1);
@@ -40,7 +40,7 @@ void tmu012_init(struct MemoryRegion *sysmem,
target_phys_addr_t base,
/* sh_serial.c */
#define SH_SERIAL_FEAT_SCIF (1 << 0)
void sh_serial_init(MemoryRegion *sysmem,
- target_phys_addr_t base, int feat,
+ Phys base, int feat,
uint32_t freq, CharDriverState *chr,
qemu_irq eri_source,
qemu_irq rxi_source,
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 4f4d8e7..bdf0620 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -197,19 +197,19 @@ static void portb_changed(SH7750State * s, uint16_t prev)
Memory
**********************************************************************/
-static void error_access(const char *kind, target_phys_addr_t addr)
+static void error_access(const char *kind, Phys addr)
{
fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
kind, regname(addr), addr);
}
-static void ignore_access(const char *kind, target_phys_addr_t addr)
+static void ignore_access(const char *kind, Phys addr)
{
fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
kind, regname(addr), addr);
}
-static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t sh7750_mem_readb(void *opaque, Phys addr)
{
switch (addr) {
default:
@@ -218,7 +218,7 @@ static uint32_t sh7750_mem_readb(void *opaque,
target_phys_addr_t addr)
}
}
-static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t sh7750_mem_readw(void *opaque, Phys addr)
{
SH7750State *s = opaque;
@@ -252,7 +252,7 @@ static uint32_t sh7750_mem_readw(void *opaque,
target_phys_addr_t addr)
}
}
-static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t sh7750_mem_readl(void *opaque, Phys addr)
{
SH7750State *s = opaque;
@@ -301,7 +301,7 @@ static uint32_t sh7750_mem_readl(void *opaque,
target_phys_addr_t addr)
#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
&& a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ##
_REGNB))
-static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void sh7750_mem_writeb(void *opaque, Phys addr,
uint32_t mem_value)
{
@@ -314,7 +314,7 @@ static void sh7750_mem_writeb(void *opaque,
target_phys_addr_t addr,
abort();
}
-static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
+static void sh7750_mem_writew(void *opaque, Phys addr,
uint32_t mem_value)
{
SH7750State *s = opaque;
@@ -366,7 +366,7 @@ static void sh7750_mem_writew(void *opaque,
target_phys_addr_t addr,
}
}
-static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
+static void sh7750_mem_writel(void *opaque, Phys addr,
uint32_t mem_value)
{
SH7750State *s = opaque;
@@ -624,14 +624,14 @@ enum {
#define MM_UTLB_DATA (7)
#define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24)
-static uint64_t invalid_read(void *opaque, target_phys_addr_t addr)
+static uint64_t invalid_read(void *opaque, Phys addr)
{
abort();
return 0;
}
-static uint64_t sh7750_mmct_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sh7750_mmct_read(void *opaque, Phys addr,
unsigned size)
{
SH7750State *s = opaque;
@@ -669,13 +669,13 @@ static uint64_t sh7750_mmct_read(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void invalid_write(void *opaque, target_phys_addr_t addr,
+static void invalid_write(void *opaque, Phys addr,
uint64_t mem_value)
{
abort();
}
-static void sh7750_mmct_write(void *opaque, target_phys_addr_t addr,
+static void sh7750_mmct_write(void *opaque, Phys addr,
uint64_t mem_value, unsigned size)
{
SH7750State *s = opaque;
diff --git a/hw/sh_intc.c b/hw/sh_intc.c
index b24ec77..fbf741b 100644
--- a/hw/sh_intc.c
+++ b/hw/sh_intc.c
@@ -219,7 +219,7 @@ static void sh_intc_toggle_mask(struct intc_desc *desc,
intc_enum id,
#endif
}
-static uint64_t sh_intc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t sh_intc_read(void *opaque, Phys offset,
unsigned size)
{
struct intc_desc *desc = opaque;
@@ -238,7 +238,7 @@ static uint64_t sh_intc_read(void *opaque,
target_phys_addr_t offset,
return *valuep;
}
-static void sh_intc_write(void *opaque, target_phys_addr_t offset,
+static void sh_intc_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
struct intc_desc *desc = opaque;
diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index d4d028d..45a5b83 100644
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -41,7 +41,7 @@
uint32_t iobr;
} SHPCIState;
-static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint64_t val,
+static void sh_pci_reg_write (void *p, Phys addr, uint64_t val,
unsigned size)
{
SHPCIState *pcic = p;
@@ -69,7 +69,7 @@ static void sh_pci_reg_write (void *p, target_phys_addr_t
addr, uint64_t val,
}
}
-static uint64_t sh_pci_reg_read (void *p, target_phys_addr_t addr,
+static uint64_t sh_pci_reg_read (void *p, Phys addr,
unsigned size)
{
SHPCIState *pcic = p;
diff --git a/hw/sh_serial.c b/hw/sh_serial.c
index 43b0eb1..fd1137a 100644
--- a/hw/sh_serial.c
+++ b/hw/sh_serial.c
@@ -78,7 +78,7 @@ static void sh_serial_clear_fifo(sh_serial_state * s)
s->rx_tail = 0;
}
-static void sh_serial_write(void *opaque, target_phys_addr_t offs,
+static void sh_serial_write(void *opaque, Phys offs,
uint64_t val, unsigned size)
{
sh_serial_state *s = opaque;
@@ -190,7 +190,7 @@ static void sh_serial_write(void *opaque,
target_phys_addr_t offs,
abort();
}
-static uint64_t sh_serial_read(void *opaque, target_phys_addr_t offs,
+static uint64_t sh_serial_read(void *opaque, Phys offs,
unsigned size)
{
sh_serial_state *s = opaque;
@@ -351,7 +351,7 @@ static void sh_serial_event(void *opaque, int event)
};
void sh_serial_init(MemoryRegion *sysmem,
- target_phys_addr_t base, int feat,
+ Phys base, int feat,
uint32_t freq, CharDriverState *chr,
qemu_irq eri_source,
qemu_irq rxi_source,
diff --git a/hw/sh_timer.c b/hw/sh_timer.c
index d2c0cec..5bf6f3e 100644
--- a/hw/sh_timer.c
+++ b/hw/sh_timer.c
@@ -58,7 +58,7 @@ static void sh_timer_update(sh_timer_state *s)
s->int_level = new_level;
}
-static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
+static uint32_t sh_timer_read(void *opaque, Phys offset)
{
sh_timer_state *s = (sh_timer_state *)opaque;
@@ -78,7 +78,7 @@ static uint32_t sh_timer_read(void *opaque,
target_phys_addr_t offset)
}
}
-static void sh_timer_write(void *opaque, target_phys_addr_t offset,
+static void sh_timer_write(void *opaque, Phys offset,
uint32_t value)
{
sh_timer_state *s = (sh_timer_state *)opaque;
@@ -221,7 +221,7 @@ static void sh_timer_tick(void *opaque)
int feat;
} tmu012_state;
-static uint64_t tmu012_read(void *opaque, target_phys_addr_t offset,
+static uint64_t tmu012_read(void *opaque, Phys offset,
unsigned size)
{
tmu012_state *s = (tmu012_state *)opaque;
@@ -252,7 +252,7 @@ static uint64_t tmu012_read(void *opaque,
target_phys_addr_t offset,
return 0;
}
-static void tmu012_write(void *opaque, target_phys_addr_t offset,
+static void tmu012_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
tmu012_state *s = (tmu012_state *)opaque;
@@ -302,7 +302,7 @@ static void tmu012_write(void *opaque, target_phys_addr_t
offset,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-void tmu012_init(MemoryRegion *sysmem, target_phys_addr_t base,
+void tmu012_init(MemoryRegion *sysmem, Phys base,
int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1)
diff --git a/hw/sharpsl.h b/hw/sharpsl.h
index 0b3a774..747a04c 100644
--- a/hw/sharpsl.h
+++ b/hw/sharpsl.h
@@ -12,6 +12,6 @@
/* zaurus.c */
#define SL_PXA_PARAM_BASE 0xa0000a00
-void sl_bootparam_write(target_phys_addr_t ptr);
+void sl_bootparam_write(Phys ptr);
#endif
diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c
index 9925e64..21193ff 100644
--- a/hw/slavio_intctl.c
+++ b/hw/slavio_intctl.c
@@ -78,7 +78,7 @@
static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
// per-cpu interrupt controller
-static uint64_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_intctl_mem_readl(void *opaque, Phys addr,
unsigned size)
{
SLAVIO_CPUINTCTLState *s = opaque;
@@ -98,7 +98,7 @@ static uint64_t slavio_intctl_mem_readl(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
+static void slavio_intctl_mem_writel(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
SLAVIO_CPUINTCTLState *s = opaque;
@@ -135,7 +135,7 @@ static void slavio_intctl_mem_writel(void *opaque,
target_phys_addr_t addr,
};
// master system interrupt controller
-static uint64_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_intctlm_mem_readl(void *opaque, Phys addr,
unsigned size)
{
SLAVIO_INTCTLState *s = opaque;
@@ -161,7 +161,7 @@ static uint64_t slavio_intctlm_mem_readl(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
+static void slavio_intctlm_mem_writel(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
SLAVIO_INTCTLState *s = opaque;
diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c
index 484301c..040fa9c 100644
--- a/hw/slavio_misc.c
+++ b/hw/slavio_misc.c
@@ -107,7 +107,7 @@ static void slavio_set_power_fail(void *opaque, int irq,
int power_failing)
slavio_misc_update_irq(s);
}
-static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_cfg_mem_writeb(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
@@ -117,7 +117,7 @@ static void slavio_cfg_mem_writeb(void *opaque,
target_phys_addr_t addr,
slavio_misc_update_irq(s);
}
-static uint64_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_cfg_mem_readb(void *opaque, Phys addr,
unsigned size)
{
MiscState *s = opaque;
@@ -138,7 +138,7 @@ static uint64_t slavio_cfg_mem_readb(void *opaque,
target_phys_addr_t addr,
},
};
-static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_diag_mem_writeb(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
@@ -147,7 +147,7 @@ static void slavio_diag_mem_writeb(void *opaque,
target_phys_addr_t addr,
s->diag = val & 0xff;
}
-static uint64_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_diag_mem_readb(void *opaque, Phys addr,
unsigned size)
{
MiscState *s = opaque;
@@ -168,7 +168,7 @@ static uint64_t slavio_diag_mem_readb(void *opaque,
target_phys_addr_t addr,
},
};
-static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_mdm_mem_writeb(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
@@ -177,7 +177,7 @@ static void slavio_mdm_mem_writeb(void *opaque,
target_phys_addr_t addr,
s->mctrl = val & 0xff;
}
-static uint64_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_mdm_mem_readb(void *opaque, Phys addr,
unsigned size)
{
MiscState *s = opaque;
@@ -198,7 +198,7 @@ static uint64_t slavio_mdm_mem_readb(void *opaque,
target_phys_addr_t addr,
},
};
-static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_aux1_mem_writeb(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
@@ -215,7 +215,7 @@ static void slavio_aux1_mem_writeb(void *opaque,
target_phys_addr_t addr,
s->aux1 = val & 0xff;
}
-static uint64_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_aux1_mem_readb(void *opaque, Phys addr,
unsigned size)
{
MiscState *s = opaque;
@@ -236,7 +236,7 @@ static uint64_t slavio_aux1_mem_readb(void *opaque,
target_phys_addr_t addr,
},
};
-static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_aux2_mem_writeb(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
@@ -252,7 +252,7 @@ static void slavio_aux2_mem_writeb(void *opaque,
target_phys_addr_t addr,
slavio_misc_update_irq(s);
}
-static uint64_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_aux2_mem_readb(void *opaque, Phys addr,
unsigned size)
{
MiscState *s = opaque;
@@ -273,7 +273,7 @@ static uint64_t slavio_aux2_mem_readb(void *opaque,
target_phys_addr_t addr,
},
};
-static void apc_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void apc_mem_writeb(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
APCState *s = opaque;
@@ -282,7 +282,7 @@ static void apc_mem_writeb(void *opaque, target_phys_addr_t
addr,
qemu_irq_raise(s->cpu_halt);
}
-static uint64_t apc_mem_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t apc_mem_readb(void *opaque, Phys addr,
unsigned size)
{
uint32_t ret = 0;
@@ -301,7 +301,7 @@ static uint64_t apc_mem_readb(void *opaque,
target_phys_addr_t addr,
}
};
-static uint64_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_sysctrl_mem_readl(void *opaque, Phys addr,
unsigned size)
{
MiscState *s = opaque;
@@ -318,7 +318,7 @@ static uint64_t slavio_sysctrl_mem_readl(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
+static void slavio_sysctrl_mem_writel(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
@@ -346,7 +346,7 @@ static void slavio_sysctrl_mem_writel(void *opaque,
target_phys_addr_t addr,
},
};
-static uint64_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_led_mem_readw(void *opaque, Phys addr,
unsigned size)
{
MiscState *s = opaque;
@@ -363,7 +363,7 @@ static uint64_t slavio_led_mem_readw(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
+static void slavio_led_mem_writew(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
MiscState *s = opaque;
diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c
index 2353c43..5332027 100644
--- a/hw/slavio_timer.c
+++ b/hw/slavio_timer.c
@@ -129,7 +129,7 @@ static void slavio_timer_irq(void *opaque)
}
}
-static uint64_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t slavio_timer_mem_readl(void *opaque, Phys addr,
unsigned size)
{
TimerContext *tc = opaque;
@@ -189,7 +189,7 @@ static uint64_t slavio_timer_mem_readl(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
+static void slavio_timer_mem_writel(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
TimerContext *tc = opaque;
diff --git a/hw/sm501.c b/hw/sm501.c
index 326531c..0a55111 100644
--- a/hw/sm501.c
+++ b/hw/sm501.c
@@ -456,7 +456,7 @@
DisplayState *ds;
/* status & internal resources */
- target_phys_addr_t base;
+ Phys base;
uint32_t local_mem_size_index;
uint8_t * local_mem;
MemoryRegion local_mem_region;
@@ -726,7 +726,7 @@ static void sm501_2d_operation(SM501State * s)
}
}
-static uint64_t sm501_system_config_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sm501_system_config_read(void *opaque, Phys addr,
unsigned size)
{
SM501State * s = (SM501State *)opaque;
@@ -779,7 +779,7 @@ static uint64_t sm501_system_config_read(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void sm501_system_config_write(void *opaque, target_phys_addr_t addr,
+static void sm501_system_config_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
SM501State * s = (SM501State *)opaque;
@@ -837,7 +837,7 @@ static void sm501_system_config_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
+static uint32_t sm501_palette_read(void *opaque, Phys addr)
{
SM501State * s = (SM501State *)opaque;
SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
@@ -850,7 +850,7 @@ static uint32_t sm501_palette_read(void *opaque,
target_phys_addr_t addr)
}
static void sm501_palette_write(void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
SM501State * s = (SM501State *)opaque;
SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
@@ -863,7 +863,7 @@ static void sm501_palette_write(void *opaque,
*(uint32_t*)&s->dc_palette[addr] = value;
}
-static uint64_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sm501_disp_ctrl_read(void *opaque, Phys addr,
unsigned size)
{
SM501State * s = (SM501State *)opaque;
@@ -958,7 +958,7 @@ static uint64_t sm501_disp_ctrl_read(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void sm501_disp_ctrl_write(void *opaque, target_phys_addr_t addr,
+static void sm501_disp_ctrl_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
SM501State * s = (SM501State *)opaque;
@@ -1073,7 +1073,7 @@ static void sm501_disp_ctrl_write(void *opaque,
target_phys_addr_t addr,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t sm501_2d_engine_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sm501_2d_engine_read(void *opaque, Phys addr,
unsigned size)
{
SM501State * s = (SM501State *)opaque;
@@ -1093,7 +1093,7 @@ static uint64_t sm501_2d_engine_read(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void sm501_2d_engine_write(void *opaque, target_phys_addr_t addr,
+static void sm501_2d_engine_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
SM501State * s = (SM501State *)opaque;
diff --git a/hw/smc91c111.c b/hw/smc91c111.c
index 82b8811..f2f4227 100644
--- a/hw/smc91c111.c
+++ b/hw/smc91c111.c
@@ -276,7 +276,7 @@ static void smc91c111_reset(DeviceState *dev)
#define SET_LOW(name, val) s->name = (s->name & 0xff00) | val
#define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8)
-static void smc91c111_writeb(void *opaque, target_phys_addr_t offset,
+static void smc91c111_writeb(void *opaque, Phys offset,
uint32_t value)
{
smc91c111_state *s = (smc91c111_state *)opaque;
@@ -451,7 +451,7 @@ static void smc91c111_writeb(void *opaque,
target_phys_addr_t offset,
hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset);
}
-static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t smc91c111_readb(void *opaque, Phys offset)
{
smc91c111_state *s = (smc91c111_state *)opaque;
@@ -595,14 +595,14 @@ static uint32_t smc91c111_readb(void *opaque,
target_phys_addr_t offset)
return 0;
}
-static void smc91c111_writew(void *opaque, target_phys_addr_t offset,
+static void smc91c111_writew(void *opaque, Phys offset,
uint32_t value)
{
smc91c111_writeb(opaque, offset, value & 0xff);
smc91c111_writeb(opaque, offset + 1, value >> 8);
}
-static void smc91c111_writel(void *opaque, target_phys_addr_t offset,
+static void smc91c111_writel(void *opaque, Phys offset,
uint32_t value)
{
/* 32-bit writes to offset 0xc only actually write to the bank select
@@ -612,7 +612,7 @@ static void smc91c111_writel(void *opaque,
target_phys_addr_t offset,
smc91c111_writew(opaque, offset + 2, value >> 16);
}
-static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t smc91c111_readw(void *opaque, Phys offset)
{
uint32_t val;
val = smc91c111_readb(opaque, offset);
@@ -620,7 +620,7 @@ static uint32_t smc91c111_readw(void *opaque,
target_phys_addr_t offset)
return val;
}
-static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t smc91c111_readl(void *opaque, Phys offset)
{
uint32_t val;
val = smc91c111_readw(opaque, offset);
diff --git a/hw/soc_dma.c b/hw/soc_dma.c
index 03bc846..e70664a 100644
--- a/hw/soc_dma.c
+++ b/hw/soc_dma.c
@@ -64,7 +64,7 @@ struct dma_s {
struct memmap_entry_s {
enum soc_dma_port_type type;
- target_phys_addr_t addr;
+ Phys addr;
union {
struct {
void *opaque;
@@ -105,7 +105,7 @@ static void soc_dma_ch_run(void *opaque)
}
static inline struct memmap_entry_s *soc_dma_lookup(struct dma_s *dma,
- target_phys_addr_t addr)
+ Phys addr)
{
struct memmap_entry_s *lo;
int hi;
@@ -255,7 +255,7 @@ struct soc_dma_s *soc_dma_init(int n)
return &s->soc;
}
-void soc_dma_port_add_fifo(struct soc_dma_s *soc, target_phys_addr_t virt_base,
+void soc_dma_port_add_fifo(struct soc_dma_s *soc, Phys virt_base,
soc_dma_io_t fn, void *opaque, int out)
{
struct memmap_entry_s *entry;
@@ -308,7 +308,7 @@ void soc_dma_port_add_fifo(struct soc_dma_s *soc,
target_phys_addr_t virt_base,
}
void soc_dma_port_add_mem(struct soc_dma_s *soc, uint8_t *phys_base,
- target_phys_addr_t virt_base, size_t size)
+ Phys virt_base, size_t size)
{
struct memmap_entry_s *entry;
struct dma_s *dma = (struct dma_s *) soc;
diff --git a/hw/soc_dma.h b/hw/soc_dma.h
index 904b26c..568a98b 100644
--- a/hw/soc_dma.h
+++ b/hw/soc_dma.h
@@ -51,7 +51,7 @@ struct soc_dma_ch_s {
int bytes;
/* Initialised by the DMA module, call soc_dma_ch_update after writing. */
enum soc_dma_access_type type[2];
- target_phys_addr_t vaddr[2]; /* Updated by .transfer_fn(). */
+ Phys vaddr[2]; /* Updated by .transfer_fn(). */
/* Private */
void *paddr[2];
soc_dma_io_t io_fn[2];
@@ -91,19 +91,19 @@ void soc_dma_ch_update(struct soc_dma_ch_s *ch);
void soc_dma_reset(struct soc_dma_s *s);
struct soc_dma_s *soc_dma_init(int n);
-void soc_dma_port_add_fifo(struct soc_dma_s *dma, target_phys_addr_t virt_base,
+void soc_dma_port_add_fifo(struct soc_dma_s *dma, Phys virt_base,
soc_dma_io_t fn, void *opaque, int out);
void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base,
- target_phys_addr_t virt_base, size_t size);
+ Phys virt_base, size_t size);
static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma,
- target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
+ Phys virt_base, soc_dma_io_t fn, void *opaque)
{
return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0);
}
static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma,
- target_phys_addr_t virt_base, soc_dma_io_t fn, void *opaque)
+ Phys virt_base, soc_dma_io_t fn, void *opaque)
{
return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1);
}
diff --git a/hw/spapr.c b/hw/spapr.c
index 161b585..398e7be 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -98,9 +98,9 @@ qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num)
}
static void *spapr_create_fdt_skel(const char *cpu_model,
- target_phys_addr_t rma_size,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size,
+ Phys rma_size,
+ Phys initrd_base,
+ Phys initrd_size,
const char *boot_device,
const char *kernel_cmdline,
long hash_shift)
@@ -317,9 +317,9 @@ qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t
*irq_num)
}
static void spapr_finalize_fdt(sPAPREnvironment *spapr,
- target_phys_addr_t fdt_addr,
- target_phys_addr_t rtas_addr,
- target_phys_addr_t rtas_size)
+ Phys fdt_addr,
+ Phys rtas_addr,
+ Phys rtas_size)
{
int ret;
void *fdt;
@@ -401,7 +401,7 @@ static void ppc_spapr_init(ram_addr_t ram_size,
int i;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
- target_phys_addr_t rma_alloc_size, rma_size;
+ Phys rma_alloc_size, rma_size;
uint32_t initrd_base;
long kernel_size, initrd_size, fw_size;
long pteg_shift = 17;
diff --git a/hw/spapr.h b/hw/spapr.h
index d624841..4c27804 100644
--- a/hw/spapr.h
+++ b/hw/spapr.h
@@ -12,10 +12,10 @@ typedef struct sPAPREnvironment {
QLIST_HEAD(, sPAPRPHBState) phbs;
struct icp_state *icp;
- target_phys_addr_t ram_limit;
+ Phys ram_limit;
void *htab;
long htab_size;
- target_phys_addr_t fdt_addr, rtas_addr;
+ Phys fdt_addr, rtas_addr;
long rtas_size;
void *fdt_skel;
target_ulong entry_point;
@@ -304,7 +304,7 @@ void spapr_rtas_register(const char *name, spapr_rtas_fn
fn);
target_ulong spapr_rtas_call(sPAPREnvironment *spapr,
uint32_t token, uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets);
-int spapr_rtas_device_tree_setup(void *fdt, target_phys_addr_t rtas_addr,
- target_phys_addr_t rtas_size);
+int spapr_rtas_device_tree_setup(void *fdt, Phys rtas_addr,
+ Phys rtas_size);
#endif /* !defined (__HW_SPAPR_H__) */
diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
index 9b6a032..722b27e 100644
--- a/hw/spapr_pci.c
+++ b/hw/spapr_pci.c
@@ -205,7 +205,7 @@ static void spapr_register_devices(void)
device_init(spapr_register_devices)
-static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t spapr_io_read(void *opaque, Phys addr,
unsigned size)
{
switch (size) {
@@ -219,7 +219,7 @@ static uint64_t spapr_io_read(void *opaque,
target_phys_addr_t addr,
assert(0);
}
-static void spapr_io_write(void *opaque, target_phys_addr_t addr,
+static void spapr_io_write(void *opaque, Phys addr,
uint64_t data, unsigned size)
{
switch (size) {
diff --git a/hw/spapr_pci.h b/hw/spapr_pci.h
index 213340c..08a9e85 100644
--- a/hw/spapr_pci.h
+++ b/hw/spapr_pci.h
@@ -35,7 +35,7 @@ typedef struct sPAPRPHBState {
uint64_t buid;
MemoryRegion memspace, iospace;
- target_phys_addr_t mem_win_addr, io_win_addr;
+ Phys mem_win_addr, io_win_addr;
MemoryRegion memwindow, iowindow;
struct {
diff --git a/hw/spapr_rtas.c b/hw/spapr_rtas.c
index d1ac74c..4b7424d 100644
--- a/hw/spapr_rtas.c
+++ b/hw/spapr_rtas.c
@@ -232,8 +232,8 @@ void spapr_rtas_register(const char *name, spapr_rtas_fn fn)
rtas_next++;
}
-int spapr_rtas_device_tree_setup(void *fdt, target_phys_addr_t rtas_addr,
- target_phys_addr_t rtas_size)
+int spapr_rtas_device_tree_setup(void *fdt, Phys rtas_addr,
+ Phys rtas_size)
{
int ret;
int i;
diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c
index 035d2e2..80f4975 100644
--- a/hw/sparc32_dma.c
+++ b/hw/sparc32_dma.c
@@ -78,7 +78,7 @@ enum {
};
/* Note: on sparc, the lance 16 bit bus is swapped */
-void ledma_memory_read(void *opaque, target_phys_addr_t addr,
+void ledma_memory_read(void *opaque, Phys addr,
uint8_t *buf, int len, int do_bswap)
{
DMAState *s = opaque;
@@ -98,7 +98,7 @@ void ledma_memory_read(void *opaque, target_phys_addr_t addr,
}
}
-void ledma_memory_write(void *opaque, target_phys_addr_t addr,
+void ledma_memory_write(void *opaque, Phys addr,
uint8_t *buf, int len, int do_bswap)
{
DMAState *s = opaque;
@@ -165,7 +165,7 @@ void espdma_memory_write(void *opaque, uint8_t *buf, int
len)
s->dmaregs[1] += len;
}
-static uint64_t dma_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t dma_mem_read(void *opaque, Phys addr,
unsigned size)
{
DMAState *s = opaque;
@@ -182,7 +182,7 @@ static uint64_t dma_mem_read(void *opaque,
target_phys_addr_t addr,
return s->dmaregs[saddr];
}
-static void dma_mem_write(void *opaque, target_phys_addr_t addr,
+static void dma_mem_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
DMAState *s = opaque;
diff --git a/hw/sparc32_dma.h b/hw/sparc32_dma.h
index 8b72c37..20c8dec 100644
--- a/hw/sparc32_dma.h
+++ b/hw/sparc32_dma.h
@@ -2,9 +2,9 @@
#define SPARC32_DMA_H
/* sparc32_dma.c */
-void ledma_memory_read(void *opaque, target_phys_addr_t addr,
+void ledma_memory_read(void *opaque, Phys addr,
uint8_t *buf, int len, int do_bswap);
-void ledma_memory_write(void *opaque, target_phys_addr_t addr,
+void ledma_memory_write(void *opaque, Phys addr,
uint8_t *buf, int len, int do_bswap);
void espdma_memory_read(void *opaque, uint8_t *buf, int len);
void espdma_memory_write(void *opaque, uint8_t *buf, int len);
diff --git a/hw/spitz.c b/hw/spitz.c
index 82a133d..df4345e 100644
--- a/hw/spitz.c
+++ b/hw/spitz.c
@@ -57,7 +57,7 @@
ECCState ecc;
} SLNANDState;
-static uint64_t sl_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t sl_read(void *opaque, Phys addr, unsigned size)
{
SLNANDState *s = (SLNANDState *) opaque;
int ryby;
@@ -99,7 +99,7 @@ static uint64_t sl_read(void *opaque, target_phys_addr_t
addr, unsigned size)
return 0;
}
-static void sl_write(void *opaque, target_phys_addr_t addr,
+static void sl_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
SLNANDState *s = (SLNANDState *) opaque;
diff --git a/hw/stellaris.c b/hw/stellaris.c
index 7a73074..34a5433 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -141,7 +141,7 @@ static void gptm_tick(void *opaque)
gptm_update_irq(s);
}
-static uint64_t gptm_read(void *opaque, target_phys_addr_t offset,
+static uint64_t gptm_read(void *opaque, Phys offset,
unsigned size)
{
gptm_state *s = (gptm_state *)opaque;
@@ -190,7 +190,7 @@ static uint64_t gptm_read(void *opaque, target_phys_addr_t
offset,
}
}
-static void gptm_write(void *opaque, target_phys_addr_t offset,
+static void gptm_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
gptm_state *s = (gptm_state *)opaque;
@@ -410,7 +410,7 @@ static int ssys_board_class(const ssys_state *s)
}
}
-static uint64_t ssys_read(void *opaque, target_phys_addr_t offset,
+static uint64_t ssys_read(void *opaque, Phys offset,
unsigned size)
{
ssys_state *s = (ssys_state *)opaque;
@@ -515,7 +515,7 @@ static void ssys_calculate_system_clock(ssys_state *s)
}
}
-static void ssys_write(void *opaque, target_phys_addr_t offset,
+static void ssys_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
ssys_state *s = (ssys_state *)opaque;
@@ -701,7 +701,7 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq,
#define STELLARIS_I2C_MCS_IDLE 0x20
#define STELLARIS_I2C_MCS_BUSBSY 0x40
-static uint64_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset,
+static uint64_t stellaris_i2c_read(void *opaque, Phys offset,
unsigned size)
{
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
@@ -738,7 +738,7 @@ static void stellaris_i2c_update(stellaris_i2c_state *s)
qemu_set_irq(s->irq, level);
}
-static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset,
+static void stellaris_i2c_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
@@ -989,7 +989,7 @@ static void stellaris_adc_reset(stellaris_adc_state *s)
}
}
-static uint64_t stellaris_adc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t stellaris_adc_read(void *opaque, Phys offset,
unsigned size)
{
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
@@ -1037,7 +1037,7 @@ static uint64_t stellaris_adc_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
+static void stellaris_adc_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
stellaris_adc_state *s = (stellaris_adc_state *)opaque;
diff --git a/hw/stellaris_enet.c b/hw/stellaris_enet.c
index 866c9a2..87e4633 100644
--- a/hw/stellaris_enet.c
+++ b/hw/stellaris_enet.c
@@ -130,7 +130,7 @@ static int stellaris_enet_can_receive(VLANClientState *nc)
return (s->np < 31);
}
-static uint64_t stellaris_enet_read(void *opaque, target_phys_addr_t offset,
+static uint64_t stellaris_enet_read(void *opaque, Phys offset,
unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
@@ -198,7 +198,7 @@ static uint64_t stellaris_enet_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
+static void stellaris_enet_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
diff --git a/hw/strongarm.c b/hw/strongarm.c
index 69c1179..8e020e9 100644
--- a/hw/strongarm.c
+++ b/hw/strongarm.c
@@ -56,7 +56,7 @@
#endif
static struct {
- target_phys_addr_t io_base;
+ Phys io_base;
int irq;
} sa_serial[] = {
{ 0x80010000, SA_PIC_UART1 },
@@ -110,7 +110,7 @@ static void strongarm_pic_set_irq(void *opaque, int irq,
int level)
strongarm_pic_update(s);
}
-static uint64_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset,
+static uint64_t strongarm_pic_mem_read(void *opaque, Phys offset,
unsigned size)
{
StrongARMPICState *s = opaque;
@@ -135,7 +135,7 @@ static uint64_t strongarm_pic_mem_read(void *opaque,
target_phys_addr_t offset,
}
}
-static void strongarm_pic_mem_write(void *opaque, target_phys_addr_t offset,
+static void strongarm_pic_mem_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
StrongARMPICState *s = opaque;
@@ -282,7 +282,7 @@ static inline void strongarm_rtc_hz_tick(void *opaque)
strongarm_rtc_int_update(s);
}
-static uint64_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t strongarm_rtc_read(void *opaque, Phys addr,
unsigned size)
{
StrongARMRTCState *s = opaque;
@@ -304,7 +304,7 @@ static uint64_t strongarm_rtc_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void strongarm_rtc_write(void *opaque, target_phys_addr_t addr,
+static void strongarm_rtc_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
StrongARMRTCState *s = opaque;
@@ -496,7 +496,7 @@ static void strongarm_gpio_handler_update(StrongARMGPIOInfo
*s)
s->prev_level = level;
}
-static uint64_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset,
+static uint64_t strongarm_gpio_read(void *opaque, Phys offset,
unsigned size)
{
StrongARMGPIOInfo *s = opaque;
@@ -538,7 +538,7 @@ static uint64_t strongarm_gpio_read(void *opaque,
target_phys_addr_t offset,
return 0;
}
-static void strongarm_gpio_write(void *opaque, target_phys_addr_t offset,
+static void strongarm_gpio_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
StrongARMGPIOInfo *s = opaque;
@@ -588,7 +588,7 @@ static void strongarm_gpio_write(void *opaque,
target_phys_addr_t offset,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static DeviceState *strongarm_gpio_init(target_phys_addr_t base,
+static DeviceState *strongarm_gpio_init(Phys base,
DeviceState *pic)
{
DeviceState *dev;
@@ -699,7 +699,7 @@ static void strongarm_ppc_handler_update(StrongARMPPCInfo
*s)
s->prev_level = level;
}
-static uint64_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset,
+static uint64_t strongarm_ppc_read(void *opaque, Phys offset,
unsigned size)
{
StrongARMPPCInfo *s = opaque;
@@ -729,7 +729,7 @@ static uint64_t strongarm_ppc_read(void *opaque,
target_phys_addr_t offset,
return 0;
}
-static void strongarm_ppc_write(void *opaque, target_phys_addr_t offset,
+static void strongarm_ppc_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
StrongARMPPCInfo *s = opaque;
@@ -1056,7 +1056,7 @@ static void strongarm_uart_tx(void *opaque)
strongarm_uart_update_int_status(s);
}
-static uint64_t strongarm_uart_read(void *opaque, target_phys_addr_t addr,
+static uint64_t strongarm_uart_read(void *opaque, Phys addr,
unsigned size)
{
StrongARMUARTState *s = opaque;
@@ -1098,7 +1098,7 @@ static uint64_t strongarm_uart_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void strongarm_uart_write(void *opaque, target_phys_addr_t addr,
+static void strongarm_uart_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
StrongARMUARTState *s = opaque;
@@ -1326,7 +1326,7 @@ static void strongarm_ssp_fifo_update(StrongARMSSPState
*s)
strongarm_ssp_int_update(s);
}
-static uint64_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t strongarm_ssp_read(void *opaque, Phys addr,
unsigned size)
{
StrongARMSSPState *s = opaque;
@@ -1359,7 +1359,7 @@ static uint64_t strongarm_ssp_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void strongarm_ssp_write(void *opaque, target_phys_addr_t addr,
+static void strongarm_ssp_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
StrongARMSSPState *s = opaque;
diff --git a/hw/sun4c_intctl.c b/hw/sun4c_intctl.c
index e15b167..6d031b8 100644
--- a/hw/sun4c_intctl.c
+++ b/hw/sun4c_intctl.c
@@ -61,7 +61,7 @@
static void sun4c_check_interrupts(void *opaque);
-static uint64_t sun4c_intctl_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t sun4c_intctl_mem_read(void *opaque, Phys addr,
unsigned size)
{
Sun4c_INTCTLState *s = opaque;
@@ -73,7 +73,7 @@ static uint64_t sun4c_intctl_mem_read(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void sun4c_intctl_mem_write(void *opaque, target_phys_addr_t addr,
+static void sun4c_intctl_mem_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
Sun4c_INTCTLState *s = opaque;
diff --git a/hw/sun4m.c b/hw/sun4m.c
index 941cc98..01a7727 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -87,16 +87,16 @@
#define ESCC_CLOCK 4915200
struct sun4m_hwdef {
- target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
- target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
- target_phys_addr_t serial_base, fd_base;
- target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
- target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
- target_phys_addr_t bpp_base, dbri_base, sx_base;
+ Phys iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
+ Phys intctl_base, counter_base, nvram_base, ms_kb_base;
+ Phys serial_base, fd_base;
+ Phys afx_base, idreg_base, dma_base, esp_base, le_base;
+ Phys tcx_base, cs_base, apc_base, aux1_base, aux2_base;
+ Phys bpp_base, dbri_base, sx_base;
struct {
- target_phys_addr_t reg_base, vram_base;
+ Phys reg_base, vram_base;
} vsimm[MAX_VSIMMS];
- target_phys_addr_t ecc_base;
+ Phys ecc_base;
uint64_t max_mem;
const char * const default_cpu_model;
uint32_t ecc_version;
@@ -108,13 +108,13 @@ struct sun4m_hwdef {
#define MAX_IOUNITS 5
struct sun4d_hwdef {
- target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
- target_phys_addr_t counter_base, nvram_base, ms_kb_base;
- target_phys_addr_t serial_base;
- target_phys_addr_t espdma_base, esp_base;
- target_phys_addr_t ledma_base, le_base;
- target_phys_addr_t tcx_base;
- target_phys_addr_t sbi_base;
+ Phys iounit_bases[MAX_IOUNITS], slavio_base;
+ Phys counter_base, nvram_base, ms_kb_base;
+ Phys serial_base;
+ Phys espdma_base, esp_base;
+ Phys ledma_base, le_base;
+ Phys tcx_base;
+ Phys sbi_base;
uint64_t max_mem;
const char * const default_cpu_model;
uint32_t iounit_version;
@@ -123,11 +123,11 @@ struct sun4d_hwdef {
};
struct sun4c_hwdef {
- target_phys_addr_t iommu_base, slavio_base;
- target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
- target_phys_addr_t serial_base, fd_base;
- target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
- target_phys_addr_t tcx_base, aux1_base;
+ Phys iommu_base, slavio_base;
+ Phys intctl_base, counter_base, nvram_base, ms_kb_base;
+ Phys serial_base, fd_base;
+ Phys idreg_base, dma_base, esp_base, le_base;
+ Phys tcx_base, aux1_base;
uint64_t max_mem;
const char * const default_cpu_model;
uint32_t iommu_version;
@@ -368,7 +368,7 @@ static unsigned long sun4m_load_kernel(const char
*kernel_filename,
return kernel_size;
}
-static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq
irq)
+static void *iommu_init(Phys addr, uint32_t version, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *s;
@@ -383,7 +383,7 @@ static unsigned long sun4m_load_kernel(const char
*kernel_filename,
return s;
}
-static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
+static void *sparc32_dma_init(Phys daddr, qemu_irq parent_irq,
void *iommu, qemu_irq *dev_irq, int is_ledma)
{
DeviceState *dev;
@@ -401,7 +401,7 @@ static unsigned long sun4m_load_kernel(const char
*kernel_filename,
return s;
}
-static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
+static void lance_init(NICInfo *nd, Phys leaddr,
void *dma_opaque, qemu_irq irq)
{
DeviceState *dev;
@@ -421,8 +421,8 @@ static void lance_init(NICInfo *nd, target_phys_addr_t
leaddr,
qdev_connect_gpio_out(dma_opaque, 0, reset);
}
-static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
- target_phys_addr_t addrg,
+static DeviceState *slavio_intctl_init(Phys addr,
+ Phys addrg,
qemu_irq **parent_irq)
{
DeviceState *dev;
@@ -450,7 +450,7 @@ static void lance_init(NICInfo *nd, target_phys_addr_t
leaddr,
#define SYS_TIMER_OFFSET 0x10000ULL
#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
-static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
+static void slavio_timer_init_all(Phys addr, qemu_irq master_irq,
qemu_irq *cpu_irqs, unsigned int num_cpus)
{
DeviceState *dev;
@@ -465,7 +465,7 @@ static void slavio_timer_init_all(target_phys_addr_t addr,
qemu_irq master_irq,
sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
for (i = 0; i < MAX_CPUS; i++) {
- sysbus_mmio_map(s, i + 1, addr +
(target_phys_addr_t)CPU_TIMER_OFFSET(i));
+ sysbus_mmio_map(s, i + 1, addr + (Phys)CPU_TIMER_OFFSET(i));
sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
}
}
@@ -476,9 +476,9 @@ static void slavio_timer_init_all(target_phys_addr_t addr,
qemu_irq master_irq,
#define MISC_MDM 0x01b00000
#define MISC_SYS 0x01f00000
-static void slavio_misc_init(target_phys_addr_t base,
- target_phys_addr_t aux1_base,
- target_phys_addr_t aux2_base, qemu_irq irq,
+static void slavio_misc_init(Phys base,
+ Phys aux1_base,
+ Phys aux2_base, qemu_irq irq,
qemu_irq fdc_tc)
{
DeviceState *dev;
@@ -515,7 +515,7 @@ static void slavio_misc_init(target_phys_addr_t base,
qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
}
-static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
+static void ecc_init(Phys base, qemu_irq irq, uint32_t version)
{
DeviceState *dev;
SysBusDevice *s;
@@ -531,7 +531,7 @@ static void ecc_init(target_phys_addr_t base, qemu_irq irq,
uint32_t version)
}
}
-static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
+static void apc_init(Phys power_base, qemu_irq cpu_halt)
{
DeviceState *dev;
SysBusDevice *s;
@@ -544,7 +544,7 @@ static void apc_init(target_phys_addr_t power_base,
qemu_irq cpu_halt)
sysbus_connect_irq(s, 0, cpu_halt);
}
-static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
+static void tcx_init(Phys addr, int vram_size, int width,
int height, int depth)
{
DeviceState *dev;
@@ -580,7 +580,7 @@ static void tcx_init(target_phys_addr_t addr, int
vram_size, int width,
/* NCR89C100/MACIO Internal ID register */
static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
-static void idreg_init(target_phys_addr_t addr)
+static void idreg_init(Phys addr)
{
DeviceState *dev;
SysBusDevice *s;
@@ -628,7 +628,7 @@ static void idreg_register_devices(void)
} AFXState;
/* SS-5 TCX AFX register */
-static void afx_init(target_phys_addr_t addr)
+static void afx_init(Phys addr)
{
DeviceState *dev;
SysBusDevice *s;
@@ -671,11 +671,11 @@ static void afx_register_devices(void)
/* Boot PROM (OpenBIOS) */
static uint64_t translate_prom_address(void *opaque, uint64_t addr)
{
- target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
+ Phys *base_addr = (Phys *)opaque;
return addr + *base_addr - PROM_VADDR;
}
-static void prom_init(target_phys_addr_t addr, const char *bios_name)
+static void prom_init(Phys addr, const char *bios_name)
{
DeviceState *dev;
SysBusDevice *s;
@@ -754,7 +754,7 @@ static int ram_init1(SysBusDevice *dev)
return 0;
}
-static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
+static void ram_init(Phys addr, ram_addr_t RAM_size,
uint64_t max_mem)
{
DeviceState *dev;
@@ -1483,7 +1483,7 @@ static void sbook_init(ram_addr_t RAM_size,
},
};
-static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
+static DeviceState *sbi_init(Phys addr, qemu_irq **parent_irq)
{
DeviceState *dev;
SysBusDevice *s;
@@ -1544,7 +1544,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef
*hwdef, ram_addr_t RAM_size,
}
for (i = 0; i < MAX_IOUNITS; i++)
- if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
+ if (hwdef->iounit_bases[i] != (Phys)-1)
iounits[i] = iommu_init(hwdef->iounit_bases[i],
hwdef->iounit_version,
sbi_irq[0]);
@@ -1677,7 +1677,7 @@ static void ss2000_init(ram_addr_t RAM_size,
},
};
-static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
+static DeviceState *sun4c_intctl_init(Phys addr,
qemu_irq *parent_irq)
{
DeviceState *dev;
@@ -1760,7 +1760,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef
*hwdef, ram_addr_t RAM_size,
slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
- if (hwdef->fd_base != (target_phys_addr_t)-1) {
+ if (hwdef->fd_base != (Phys)-1) {
/* there is zero or one floppy drive */
memset(fd, 0, sizeof(fd));
fd[0] = drive_get(IF_FLOPPY, 0, 0);
diff --git a/hw/sun4m.h b/hw/sun4m.h
index 504c3af..de20dfb 100644
--- a/hw/sun4m.h
+++ b/hw/sun4m.h
@@ -6,17 +6,17 @@
/* Devices used by sparc32 system. */
/* iommu.c */
-void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
+void sparc_iommu_memory_rw(void *opaque, Phys addr,
uint8_t *buf, int len, int is_write);
static inline void sparc_iommu_memory_read(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
uint8_t *buf, int len)
{
sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
}
static inline void sparc_iommu_memory_write(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
uint8_t *buf, int len)
{
sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
diff --git a/hw/sun4m_iommu.c b/hw/sun4m_iommu.c
index ef7627c..5d27cd6 100644
--- a/hw/sun4m_iommu.c
+++ b/hw/sun4m_iommu.c
@@ -130,16 +130,16 @@
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t regs[IOMMU_NREGS];
- target_phys_addr_t iostart;
+ Phys iostart;
qemu_irq irq;
uint32_t version;
} IOMMUState;
-static uint64_t iommu_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t iommu_mem_read(void *opaque, Phys addr,
unsigned size)
{
IOMMUState *s = opaque;
- target_phys_addr_t saddr;
+ Phys saddr;
uint32_t ret;
saddr = addr >> 2;
@@ -157,11 +157,11 @@ static uint64_t iommu_mem_read(void *opaque,
target_phys_addr_t addr,
return ret;
}
-static void iommu_mem_write(void *opaque, target_phys_addr_t addr,
+static void iommu_mem_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
IOMMUState *s = opaque;
- target_phys_addr_t saddr;
+ Phys saddr;
saddr = addr >> 2;
trace_sun4m_iommu_mem_writel(saddr, val);
@@ -249,11 +249,11 @@ static void iommu_mem_write(void *opaque,
target_phys_addr_t addr,
},
};
-static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
+static uint32_t iommu_page_get_flags(IOMMUState *s, Phys addr)
{
uint32_t ret;
- target_phys_addr_t iopte;
- target_phys_addr_t pa = addr;
+ Phys iopte;
+ Phys pa = addr;
iopte = s->regs[IOMMU_BASE] << 4;
addr &= ~s->iostart;
@@ -264,17 +264,17 @@ static uint32_t iommu_page_get_flags(IOMMUState *s,
target_phys_addr_t addr)
return ret;
}
-static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
+static Phys iommu_translate_pa(Phys addr,
uint32_t pte)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
trace_sun4m_iommu_translate_pa(addr, pa, pte);
return pa;
}
-static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
+static void iommu_bad_addr(IOMMUState *s, Phys addr,
int is_write)
{
trace_sun4m_iommu_bad_addr(addr);
@@ -286,12 +286,12 @@ static void iommu_bad_addr(IOMMUState *s,
target_phys_addr_t addr,
qemu_irq_raise(s->irq);
}
-void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
+void sparc_iommu_memory_rw(void *opaque, Phys addr,
uint8_t *buf, int len, int is_write)
{
int l;
uint32_t flags;
- target_phys_addr_t page, phys_addr;
+ Phys page, phys_addr;
while (len > 0) {
page = addr & IOMMU_PAGE_MASK;
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 2dc3d04..5e0a6fd 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -586,12 +586,12 @@ static void pci_ebus_register(void)
static uint64_t translate_prom_address(void *opaque, uint64_t addr)
{
- target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
+ Phys *base_addr = (Phys *)opaque;
return addr + *base_addr - PROM_VADDR;
}
/* Boot PROM (OpenBIOS) */
-static void prom_init(target_phys_addr_t addr, const char *bios_name)
+static void prom_init(Phys addr, const char *bios_name)
{
DeviceState *dev;
SysBusDevice *s;
@@ -671,7 +671,7 @@ static int ram_init1(SysBusDevice *dev)
return 0;
}
-static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
+static void ram_init(Phys addr, ram_addr_t RAM_size)
{
DeviceState *dev;
SysBusDevice *s;
diff --git a/hw/sysbus.c b/hw/sysbus.c
index 2e06fe8..800c2e5 100644
--- a/hw/sysbus.c
+++ b/hw/sysbus.c
@@ -40,7 +40,7 @@ void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq
irq)
}
}
-void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr)
+void sysbus_mmio_map(SysBusDevice *dev, int n, Phys addr)
{
assert(n >= 0 && n < dev->num_mmio);
@@ -48,7 +48,7 @@ void sysbus_mmio_map(SysBusDevice *dev, int n,
target_phys_addr_t addr)
/* ??? region already mapped here. */
return;
}
- if (dev->mmio[n].addr != (target_phys_addr_t)-1) {
+ if (dev->mmio[n].addr != (Phys)-1) {
/* Unregister previous mapping. */
memory_region_del_subregion(get_system_memory(), dev->mmio[n].memory);
}
@@ -133,7 +133,7 @@ void sysbus_register_dev(const char *name, size_t size,
sysbus_initfn init)
}
DeviceState *sysbus_create_varargs(const char *name,
- target_phys_addr_t addr, ...)
+ Phys addr, ...)
{
DeviceState *dev;
SysBusDevice *s;
@@ -144,7 +144,7 @@ void sysbus_register_dev(const char *name, size_t size,
sysbus_initfn init)
dev = qdev_create(NULL, name);
s = sysbus_from_qdev(dev);
qdev_init_nofail(dev);
- if (addr != (target_phys_addr_t)-1) {
+ if (addr != (Phys)-1) {
sysbus_mmio_map(s, 0, addr);
}
va_start(va, addr);
@@ -162,7 +162,7 @@ void sysbus_register_dev(const char *name, size_t size,
sysbus_initfn init)
}
DeviceState *sysbus_try_create_varargs(const char *name,
- target_phys_addr_t addr, ...)
+ Phys addr, ...)
{
DeviceState *dev;
SysBusDevice *s;
@@ -176,7 +176,7 @@ void sysbus_register_dev(const char *name, size_t size,
sysbus_initfn init)
}
s = sysbus_from_qdev(dev);
qdev_init_nofail(dev);
- if (addr != (target_phys_addr_t)-1) {
+ if (addr != (Phys)-1) {
sysbus_mmio_map(s, 0, addr);
}
va_start(va, addr);
@@ -196,7 +196,7 @@ void sysbus_register_dev(const char *name, size_t size,
sysbus_initfn init)
static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent)
{
SysBusDevice *s = sysbus_from_qdev(dev);
- target_phys_addr_t size;
+ Phys size;
int i;
monitor_printf(mon, "%*sirq %d\n", indent, "", s->num_irq);
@@ -225,13 +225,13 @@ static void sysbus_dev_print(Monitor *mon, DeviceState
*dev, int indent)
return strdup(path);
}
-void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_memory(SysBusDevice *dev, Phys addr,
MemoryRegion *mem)
{
memory_region_add_subregion(get_system_memory(), addr, mem);
}
-void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_memory_overlap(SysBusDevice *dev, Phys addr,
MemoryRegion *mem, unsigned priority)
{
memory_region_add_subregion_overlap(get_system_memory(), addr, mem,
@@ -243,7 +243,7 @@ void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem)
memory_region_del_subregion(get_system_memory(), mem);
}
-void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_io(SysBusDevice *dev, Phys addr,
MemoryRegion *mem)
{
memory_region_add_subregion(get_system_io(), addr, mem);
diff --git a/hw/sysbus.h b/hw/sysbus.h
index 899756b..da5957c 100644
--- a/hw/sysbus.h
+++ b/hw/sysbus.h
@@ -19,7 +19,7 @@ struct SysBusDevice {
qemu_irq *irqp[QDEV_MAX_IRQ];
int num_mmio;
struct {
- target_phys_addr_t addr;
+ Phys addr;
MemoryRegion *memory;
} mmio[QDEV_MAX_MMIO];
int num_pio;
@@ -48,31 +48,31 @@ void sysbus_init_ioports(SysBusDevice *dev, pio_addr_t
ioport, pio_addr_t size);
void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
-void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr);
-void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_mmio_map(SysBusDevice *dev, int n, Phys addr);
+void sysbus_add_memory(SysBusDevice *dev, Phys addr,
MemoryRegion *mem);
-void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_memory_overlap(SysBusDevice *dev, Phys addr,
MemoryRegion *mem, unsigned priority);
void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem);
-void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
+void sysbus_add_io(SysBusDevice *dev, Phys addr,
MemoryRegion *mem);
void sysbus_del_io(SysBusDevice *dev, MemoryRegion *mem);
MemoryRegion *sysbus_address_space(SysBusDevice *dev);
/* Legacy helper function for creating devices. */
DeviceState *sysbus_create_varargs(const char *name,
- target_phys_addr_t addr, ...);
+ Phys addr, ...);
DeviceState *sysbus_try_create_varargs(const char *name,
- target_phys_addr_t addr, ...);
+ Phys addr, ...);
static inline DeviceState *sysbus_create_simple(const char *name,
- target_phys_addr_t addr,
+ Phys addr,
qemu_irq irq)
{
return sysbus_create_varargs(name, addr, irq, NULL);
}
static inline DeviceState *sysbus_try_create_simple(const char *name,
- target_phys_addr_t addr,
+ Phys addr,
qemu_irq irq)
{
return sysbus_try_create_varargs(name, addr, irq, NULL);
diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c
index b75fa60..6329707 100644
--- a/hw/tc6393xb.c
+++ b/hw/tc6393xb.c
@@ -212,7 +212,7 @@ static void tc6393xb_sub_irq(void *opaque, int line, int
level) {
case SCR_ ##N(1): return s->scr.N[1]; \
case SCR_ ##N(2): return s->scr.N[2]
-static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr)
+static uint32_t tc6393xb_scr_readb(TC6393xbState *s, Phys addr)
{
switch (addr) {
case SCR_REVID:
@@ -273,7 +273,7 @@ static uint32_t tc6393xb_scr_readb(TC6393xbState *s,
target_phys_addr_t addr)
case SCR_ ##N(1): s->scr.N[1] = value; return; \
case SCR_ ##N(2): s->scr.N[2] = value; return
-static void tc6393xb_scr_writeb(TC6393xbState *s, target_phys_addr_t addr,
uint32_t value)
+static void tc6393xb_scr_writeb(TC6393xbState *s, Phys addr, uint32_t value)
{
switch (addr) {
SCR_REG_B(ISR);
@@ -324,7 +324,7 @@ static void tc6393xb_nand_irq(TC6393xbState *s) {
(s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
}
-static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t
addr) {
+static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, Phys addr) {
switch (addr) {
case NAND_CFG_COMMAND:
return s->nand_enable ? 2 : 0;
@@ -337,7 +337,7 @@ static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s,
target_phys_addr_t add
fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t)
addr);
return 0;
}
-static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t
addr, uint32_t value) {
+static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, Phys addr, uint32_t
value) {
switch (addr) {
case NAND_CFG_COMMAND:
s->nand_enable = (value & 0x2);
@@ -354,7 +354,7 @@ static void tc6393xb_nand_cfg_writeb(TC6393xbState *s,
target_phys_addr_t addr,
(uint32_t) addr, value & 0xff);
}
-static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr)
{
+static uint32_t tc6393xb_nand_readb(TC6393xbState *s, Phys addr) {
switch (addr) {
case NAND_DATA + 0:
case NAND_DATA + 1:
@@ -373,7 +373,7 @@ static uint32_t tc6393xb_nand_readb(TC6393xbState *s,
target_phys_addr_t addr) {
fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t)
addr);
return 0;
}
-static void tc6393xb_nand_writeb(TC6393xbState *s, target_phys_addr_t addr,
uint32_t value) {
+static void tc6393xb_nand_writeb(TC6393xbState *s, Phys addr, uint32_t value) {
// fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
// (uint32_t) addr, value & 0xff);
switch (addr) {
@@ -496,7 +496,7 @@ static void tc6393xb_update_display(void *opaque)
}
-static uint64_t tc6393xb_readb(void *opaque, target_phys_addr_t addr,
+static uint64_t tc6393xb_readb(void *opaque, Phys addr,
unsigned size)
{
TC6393xbState *s = opaque;
@@ -519,7 +519,7 @@ static uint64_t tc6393xb_readb(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr,
+static void tc6393xb_writeb(void *opaque, Phys addr,
uint64_t value, unsigned size) {
TC6393xbState *s = opaque;
diff --git a/hw/tcx.c b/hw/tcx.c
index 75a28f2..a85ddcd 100644
--- a/hw/tcx.c
+++ b/hw/tcx.c
@@ -36,7 +36,7 @@
typedef struct TCXState {
SysBusDevice busdev;
- target_phys_addr_t addr;
+ Phys addr;
DisplayState *ds;
uint8_t *vram;
uint32_t *vram24, *cplane;
@@ -439,13 +439,13 @@ static void tcx_reset(DeviceState *d)
s->dac_state = 0;
}
-static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t tcx_dac_readl(void *opaque, Phys addr,
unsigned size)
{
return 0;
}
-static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val,
+static void tcx_dac_writel(void *opaque, Phys addr, uint64_t val,
unsigned size)
{
TCXState *s = opaque;
@@ -492,13 +492,13 @@ static void tcx_dac_writel(void *opaque,
target_phys_addr_t addr, uint64_t val,
},
};
-static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr,
+static uint64_t dummy_readl(void *opaque, Phys addr,
unsigned size)
{
return 0;
}
-static void dummy_writel(void *opaque, target_phys_addr_t addr,
+static void dummy_writel(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
}
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index 276300a..aa7ac33 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -281,7 +281,7 @@ static void tusb_gpio_intr_update(TUSBState *s)
extern CPUReadMemoryFunc * const musb_read[];
extern CPUWriteMemoryFunc * const musb_write[];
-static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t tusb_async_readb(void *opaque, Phys addr)
{
TUSBState *s = (TUSBState *) opaque;
@@ -298,7 +298,7 @@ static uint32_t tusb_async_readb(void *opaque,
target_phys_addr_t addr)
return 0;
}
-static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr)
+static uint32_t tusb_async_readh(void *opaque, Phys addr)
{
TUSBState *s = (TUSBState *) opaque;
@@ -315,7 +315,7 @@ static uint32_t tusb_async_readh(void *opaque,
target_phys_addr_t addr)
return 0;
}
-static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t tusb_async_readw(void *opaque, Phys addr)
{
TUSBState *s = (TUSBState *) opaque;
int offset = addr & 0xfff;
@@ -438,7 +438,7 @@ static uint32_t tusb_async_readw(void *opaque,
target_phys_addr_t addr)
return 0;
}
-static void tusb_async_writeb(void *opaque, target_phys_addr_t addr,
+static void tusb_async_writeb(void *opaque, Phys addr,
uint32_t value)
{
TUSBState *s = (TUSBState *) opaque;
@@ -459,7 +459,7 @@ static void tusb_async_writeb(void *opaque,
target_phys_addr_t addr,
}
}
-static void tusb_async_writeh(void *opaque, target_phys_addr_t addr,
+static void tusb_async_writeh(void *opaque, Phys addr,
uint32_t value)
{
TUSBState *s = (TUSBState *) opaque;
@@ -480,7 +480,7 @@ static void tusb_async_writeh(void *opaque,
target_phys_addr_t addr,
}
}
-static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
+static void tusb_async_writew(void *opaque, Phys addr,
uint32_t value)
{
TUSBState *s = (TUSBState *) opaque;
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index 14d9914..1470561 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -101,7 +101,7 @@ static uint32_t unin_get_config_reg(uint32_t reg, uint32_t
addr)
return retval;
}
-static void unin_data_write(void *opaque, target_phys_addr_t addr,
+static void unin_data_write(void *opaque, Phys addr,
uint64_t val, unsigned len)
{
UNINState *s = opaque;
@@ -112,7 +112,7 @@ static void unin_data_write(void *opaque,
target_phys_addr_t addr,
val, len);
}
-static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
+static uint64_t unin_data_read(void *opaque, Phys addr,
unsigned len)
{
UNINState *s = opaque;
diff --git a/hw/usb-ehci.c b/hw/usb-ehci.c
index 7c926c0..829eb91 100644
--- a/hw/usb-ehci.c
+++ b/hw/usb-ehci.c
@@ -486,7 +486,7 @@ struct EHCIState {
return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
}
-static const char *addr2str(target_phys_addr_t addr)
+static const char *addr2str(Phys addr)
{
return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
}
@@ -605,7 +605,7 @@ static int ehci_get_fetch_addr(EHCIState *s, int async)
return async ? s->a_fetch_addr : s->p_fetch_addr;
}
-static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
+static void ehci_trace_qh(EHCIQueue *q, Phys addr, EHCIqh *qh)
{
/* need three here due to argument count limits */
trace_usb_ehci_qh_ptrs(q, addr, qh->next,
@@ -623,7 +623,7 @@ static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t
addr, EHCIqh *qh)
(bool)(qh->epchar & QH_EPCHAR_I));
}
-static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
+static void ehci_trace_qtd(EHCIQueue *q, Phys addr, EHCIqtd *qtd)
{
/* need three here due to argument count limits */
trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
@@ -640,7 +640,7 @@ static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t
addr, EHCIqtd *qtd)
(bool)(qtd->token & QTD_TOKEN_XACTERR));
}
-static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
+static void ehci_trace_itd(EHCIState *s, Phys addr, EHCIitd *itd)
{
trace_usb_ehci_itd(addr, itd->next,
get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
@@ -649,7 +649,7 @@ static void ehci_trace_itd(EHCIState *s, target_phys_addr_t
addr, EHCIitd *itd)
get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
}
-static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
+static void ehci_trace_sitd(EHCIState *s, Phys addr,
EHCIsitd *sitd)
{
trace_usb_ehci_sitd(addr, sitd->next,
@@ -888,7 +888,7 @@ static void ehci_reset(void *opaque)
ehci_queues_rip_all(s);
}
-static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
+static uint32_t ehci_mem_readb(void *ptr, Phys addr)
{
EHCIState *s = ptr;
uint32_t val;
@@ -898,7 +898,7 @@ static uint32_t ehci_mem_readb(void *ptr,
target_phys_addr_t addr)
return val;
}
-static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
+static uint32_t ehci_mem_readw(void *ptr, Phys addr)
{
EHCIState *s = ptr;
uint32_t val;
@@ -908,7 +908,7 @@ static uint32_t ehci_mem_readw(void *ptr,
target_phys_addr_t addr)
return val;
}
-static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
+static uint32_t ehci_mem_readl(void *ptr, Phys addr)
{
EHCIState *s = ptr;
uint32_t val;
@@ -920,13 +920,13 @@ static uint32_t ehci_mem_readl(void *ptr,
target_phys_addr_t addr)
return val;
}
-static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
+static void ehci_mem_writeb(void *ptr, Phys addr, uint32_t val)
{
fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
exit(1);
}
-static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
+static void ehci_mem_writew(void *ptr, Phys addr, uint32_t val)
{
fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
exit(1);
@@ -998,7 +998,7 @@ static void handle_port_status_write(EHCIState *s, int
port, uint32_t val)
*portsc |= val;
}
-static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
+static void ehci_mem_writel(void *ptr, Phys addr, uint32_t val)
{
EHCIState *s = ptr;
uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
diff --git a/hw/usb-libhw.c b/hw/usb-libhw.c
index 162b42b..ec0955a 100644
--- a/hw/usb-libhw.c
+++ b/hw/usb-libhw.c
@@ -27,7 +27,7 @@
int usb_packet_map(USBPacket *p, QEMUSGList *sgl)
{
int is_write = (p->pid == USB_TOKEN_IN);
- target_phys_addr_t len;
+ Phys len;
void *mem;
int i;
diff --git a/hw/usb-musb.c b/hw/usb-musb.c
index 01e2e7c..6e66ef8 100644
--- a/hw/usb-musb.c
+++ b/hw/usb-musb.c
@@ -1234,7 +1234,7 @@ static void musb_ep_writeh(void *opaque, int ep, int
addr, uint16_t value)
}
/* Generic control */
-static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t musb_readb(void *opaque, Phys addr)
{
MUSBState *s = (MUSBState *) opaque;
int ep, i;
@@ -1296,7 +1296,7 @@ static uint32_t musb_readb(void *opaque,
target_phys_addr_t addr)
};
}
-static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void musb_writeb(void *opaque, Phys addr, uint32_t value)
{
MUSBState *s = (MUSBState *) opaque;
int ep;
@@ -1383,7 +1383,7 @@ static void musb_writeb(void *opaque, target_phys_addr_t
addr, uint32_t value)
};
}
-static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
+static uint32_t musb_readh(void *opaque, Phys addr)
{
MUSBState *s = (MUSBState *) opaque;
int ep, i;
@@ -1437,7 +1437,7 @@ static uint32_t musb_readh(void *opaque,
target_phys_addr_t addr)
};
}
-static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void musb_writeh(void *opaque, Phys addr, uint32_t value)
{
MUSBState *s = (MUSBState *) opaque;
int ep;
@@ -1493,7 +1493,7 @@ static void musb_writeh(void *opaque, target_phys_addr_t
addr, uint32_t value)
};
}
-static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t musb_readw(void *opaque, Phys addr)
{
MUSBState *s = (MUSBState *) opaque;
int ep;
@@ -1511,7 +1511,7 @@ static uint32_t musb_readw(void *opaque,
target_phys_addr_t addr)
};
}
-static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
+static void musb_writew(void *opaque, Phys addr, uint32_t value)
{
MUSBState *s = (MUSBState *) opaque;
int ep;
diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c
index e68be70..9b0cba7 100644
--- a/hw/usb-ohci.c
+++ b/hw/usb-ohci.c
@@ -105,7 +105,7 @@
uint32_t htest;
/* SM501 local memory offset */
- target_phys_addr_t localmem_base;
+ Phys localmem_base;
/* Active packets. */
uint32_t old_ctl;
@@ -1456,7 +1456,7 @@ static void ohci_port_set_status(OHCIState *ohci, int
portnum, uint32_t val)
}
static uint64_t ohci_mem_read(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
unsigned size)
{
OHCIState *ohci = opaque;
@@ -1579,7 +1579,7 @@ static uint64_t ohci_mem_read(void *opaque,
}
static void ohci_mem_write(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
uint64_t val,
unsigned size)
{
@@ -1819,7 +1819,7 @@ void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
SysBusDevice busdev;
OHCIState ohci;
uint32_t num_ports;
- target_phys_addr_t dma_offset;
+ Phys dma_offset;
} OHCISysBusState;
static int ohci_init_pxa(SysBusDevice *dev)
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index a285f7f..4da3872 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -21,18 +21,18 @@
MemoryRegion isa;
} PCIVPBState;
-static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
+static inline uint32_t vpb_pci_config_addr(Phys addr)
{
return addr & 0xffffff;
}
-static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr,
+static void pci_vpb_config_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
}
-static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
+static uint64_t pci_vpb_config_read(void *opaque, Phys addr,
unsigned size)
{
uint32_t val;
diff --git a/hw/versatilepb.c b/hw/versatilepb.c
index 0312b75..5f516ee 100644
--- a/hw/versatilepb.c
+++ b/hw/versatilepb.c
@@ -77,7 +77,7 @@ static void vpb_sic_set_irq(void *opaque, int irq, int level)
vpb_sic_update(s);
}
-static uint64_t vpb_sic_read(void *opaque, target_phys_addr_t offset,
+static uint64_t vpb_sic_read(void *opaque, Phys offset,
unsigned size)
{
vpb_sic_state *s = (vpb_sic_state *)opaque;
@@ -99,7 +99,7 @@ static uint64_t vpb_sic_read(void *opaque, target_phys_addr_t
offset,
}
}
-static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
+static void vpb_sic_write(void *opaque, Phys offset,
uint64_t value, unsigned size)
{
vpb_sic_state *s = (vpb_sic_state *)opaque;
diff --git a/hw/vga-isa-mm.c b/hw/vga-isa-mm.c
index f8984c6..1908e6d 100644
--- a/hw/vga-isa-mm.c
+++ b/hw/vga-isa-mm.c
@@ -34,7 +34,7 @@
} ISAVGAMMState;
/* Memory mapped interface */
-static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t vga_mm_readb (void *opaque, Phys addr)
{
ISAVGAMMState *s = opaque;
@@ -42,14 +42,14 @@ static uint32_t vga_mm_readb (void *opaque,
target_phys_addr_t addr)
}
static void vga_mm_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
ISAVGAMMState *s = opaque;
vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xff);
}
-static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t vga_mm_readw (void *opaque, Phys addr)
{
ISAVGAMMState *s = opaque;
@@ -57,14 +57,14 @@ static uint32_t vga_mm_readw (void *opaque,
target_phys_addr_t addr)
}
static void vga_mm_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
ISAVGAMMState *s = opaque;
vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xffff);
}
-static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t vga_mm_readl (void *opaque, Phys addr)
{
ISAVGAMMState *s = opaque;
@@ -72,7 +72,7 @@ static uint32_t vga_mm_readl (void *opaque,
target_phys_addr_t addr)
}
static void vga_mm_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ Phys addr, uint32_t value)
{
ISAVGAMMState *s = opaque;
@@ -95,8 +95,8 @@ static void vga_mm_writel (void *opaque,
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift,
+static void vga_mm_init(ISAVGAMMState *s, Phys vram_base,
+ Phys ctrl_base, int it_shift,
MemoryRegion *address_space)
{
MemoryRegion *s_ioport_ctrl, *vga_io_memory;
@@ -120,8 +120,8 @@ static void vga_mm_init(ISAVGAMMState *s,
target_phys_addr_t vram_base,
memory_region_set_coalescing(vga_io_memory);
}
-int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift,
+int isa_vga_mm_init(Phys vram_base,
+ Phys ctrl_base, int it_shift,
MemoryRegion *address_space)
{
ISAVGAMMState *s;
diff --git a/hw/vga.c b/hw/vga.c
index 4878fbc..c9823dd 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -156,7 +156,7 @@
static void vga_update_memory_access(VGACommonState *s)
{
MemoryRegion *region, *old_region = s->chain4_alias;
- target_phys_addr_t base, offset, size;
+ Phys base, offset, size;
s->chain4_alias = NULL;
@@ -756,7 +756,7 @@ static void vbe_ioport_write_data(void *opaque, uint32_t
addr, uint32_t val)
#endif
/* called for accesses between 0xa0000 and 0xc0000 */
-uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr)
+uint32_t vga_mem_readb(VGACommonState *s, Phys addr)
{
int memory_map_mode, plane;
uint32_t ret;
@@ -812,7 +812,7 @@ uint32_t vga_mem_readb(VGACommonState *s,
target_phys_addr_t addr)
}
/* called for accesses between 0xa0000 and 0xc0000 */
-void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val)
+void vga_mem_writeb(VGACommonState *s, Phys addr, uint32_t val)
{
int memory_map_mode, plane, write_mode, b, func_select, mask;
uint32_t write_mask, bit_mask, set_mask;
@@ -2113,7 +2113,7 @@ static void vga_update_text(void *opaque, console_ch_t
*chardata)
dpy_update(s->ds, 0, 0, s->last_width, height);
}
-static uint64_t vga_mem_read(void *opaque, target_phys_addr_t addr,
+static uint64_t vga_mem_read(void *opaque, Phys addr,
unsigned size)
{
VGACommonState *s = opaque;
@@ -2121,7 +2121,7 @@ static uint64_t vga_mem_read(void *opaque,
target_phys_addr_t addr,
return vga_mem_readb(s, addr);
}
-static void vga_mem_write(void *opaque, target_phys_addr_t addr,
+static void vga_mem_write(void *opaque, Phys addr,
uint64_t data, unsigned size)
{
VGACommonState *s = opaque;
diff --git a/hw/vga_int.h b/hw/vga_int.h
index c1e700f..c4524ca 100644
--- a/hw/vga_int.h
+++ b/hw/vga_int.h
@@ -200,8 +200,8 @@ void vga_dirty_log_stop(VGACommonState *s);
extern const VMStateDescription vmstate_vga_common;
uint32_t vga_ioport_read(void *opaque, uint32_t addr);
void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
-uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr);
-void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val);
+uint32_t vga_mem_readb(VGACommonState *s, Phys addr);
+void vga_mem_writeb(VGACommonState *s, Phys addr, uint32_t val);
void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
int ppm_save(const char *filename, struct DisplaySurface *ds);
diff --git a/hw/vhost.c b/hw/vhost.c
index cd56e75..febe59a 100644
--- a/hw/vhost.c
+++ b/hw/vhost.c
@@ -60,8 +60,8 @@ static void vhost_dev_sync_region(struct vhost_dev *dev,
static int vhost_sync_dirty_bitmap(struct vhost_dev *dev,
MemoryRegionSection *section,
- target_phys_addr_t start_addr,
- target_phys_addr_t end_addr)
+ Phys start_addr,
+ Phys end_addr)
{
int i;
@@ -88,8 +88,8 @@ static void vhost_log_sync(MemoryListener *listener,
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
memory_listener);
- target_phys_addr_t start_addr = section->offset_within_address_space;
- target_phys_addr_t end_addr = start_addr + section->size;
+ Phys start_addr = section->offset_within_address_space;
+ Phys end_addr = start_addr + section->size;
vhost_sync_dirty_bitmap(dev, section, start_addr, end_addr);
}
@@ -274,7 +274,7 @@ static inline void vhost_dev_log_resize(struct vhost_dev*
dev, uint64_t size)
assert(r >= 0);
for (i = 0; i < dev->n_mem_sections; ++i) {
vhost_sync_dirty_bitmap(dev, &dev->mem_sections[i],
- 0, (target_phys_addr_t)~0x0ull);
+ 0, (Phys)~0x0ull);
}
if (dev->log) {
g_free(dev->log);
@@ -290,7 +290,7 @@ static int vhost_verify_ring_mappings(struct vhost_dev *dev,
int i;
for (i = 0; i < dev->nvqs; ++i) {
struct vhost_virtqueue *vq = dev->vqs + i;
- target_phys_addr_t l;
+ Phys l;
void *p;
if (!ranges_overlap(start_addr, size, vq->ring_phys, vq->ring_size)) {
@@ -356,7 +356,7 @@ static void vhost_set_memory(MemoryListener *listener,
{
struct vhost_dev *dev = container_of(listener, struct vhost_dev,
memory_listener);
- target_phys_addr_t start_addr = section->offset_within_address_space;
+ Phys start_addr = section->offset_within_address_space;
ram_addr_t size = section->size;
bool log_dirty = memory_region_is_logging(section->mr);
int s = offsetof(struct vhost_memory, regions) +
@@ -589,7 +589,7 @@ static int vhost_virtqueue_init(struct vhost_dev *dev,
struct vhost_virtqueue *vq,
unsigned idx)
{
- target_phys_addr_t s, l, a;
+ Phys s, l, a;
int r;
struct vhost_vring_file file = {
.index = idx,
@@ -901,7 +901,7 @@ void vhost_dev_stop(struct vhost_dev *hdev, VirtIODevice
*vdev)
}
for (i = 0; i < hdev->n_mem_sections; ++i) {
vhost_sync_dirty_bitmap(hdev, &hdev->mem_sections[i],
- 0, (target_phys_addr_t)~0x0ull);
+ 0, (Phys)~0x0ull);
}
r = vdev->binding->set_guest_notifiers(vdev->binding_opaque, false);
if (r < 0) {
diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c
index bd16b97..a77a6b2 100644
--- a/hw/virtex_ml507.c
+++ b/hw/virtex_ml507.c
@@ -59,7 +59,7 @@
/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
static void mmubooke_create_initial_mapping(CPUState *env,
target_ulong va,
- target_phys_addr_t pa)
+ Phys pa)
{
ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
@@ -132,10 +132,10 @@ static void main_cpu_reset(void *opaque)
}
#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
-static int xilinx_load_device_tree(target_phys_addr_t addr,
+static int xilinx_load_device_tree(Phys addr,
uint32_t ramsize,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size,
+ Phys initrd_base,
+ Phys initrd_size,
const char *kernel_cmdline)
{
char *path;
@@ -190,7 +190,7 @@ static void virtex_init(ram_addr_t ram_size,
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev;
CPUState *env;
- target_phys_addr_t ram_base = 0;
+ Phys ram_base = 0;
DriveInfo *dinfo;
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
@@ -229,7 +229,7 @@ static void virtex_init(ram_addr_t ram_size,
if (kernel_filename) {
uint64_t entry, low, high;
- target_phys_addr_t boot_offset;
+ Phys boot_offset;
/* Boots a kernel elf binary. */
kernel_size = load_elf(kernel_filename, NULL, NULL,
diff --git a/hw/virtio-pci.c b/hw/virtio-pci.c
index 77b75bc..08cb445 100644
--- a/hw/virtio-pci.c
+++ b/hw/virtio-pci.c
@@ -279,7 +279,7 @@ static void virtio_ioport_write(void *opaque, uint32_t
addr, uint32_t val)
{
VirtIOPCIProxy *proxy = opaque;
VirtIODevice *vdev = proxy->vdev;
- target_phys_addr_t pa;
+ Phys pa;
switch (addr) {
case VIRTIO_PCI_GUEST_FEATURES:
@@ -290,7 +290,7 @@ static void virtio_ioport_write(void *opaque, uint32_t
addr, uint32_t val)
virtio_set_features(vdev, val);
break;
case VIRTIO_PCI_QUEUE_PFN:
- pa = (target_phys_addr_t)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
+ pa = (Phys)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
if (pa == 0) {
virtio_pci_stop_ioeventfd(proxy);
virtio_reset(proxy->vdev);
diff --git a/hw/virtio.c b/hw/virtio.c
index 81ecc40..8dfa507 100644
--- a/hw/virtio.c
+++ b/hw/virtio.c
@@ -53,15 +53,15 @@
typedef struct VRing
{
unsigned int num;
- target_phys_addr_t desc;
- target_phys_addr_t avail;
- target_phys_addr_t used;
+ Phys desc;
+ Phys avail;
+ Phys used;
} VRing;
struct VirtQueue
{
VRing vring;
- target_phys_addr_t pa;
+ Phys pa;
uint16_t last_avail_idx;
/* Last used index value we have signalled on */
uint16_t signalled_used;
@@ -84,7 +84,7 @@ struct VirtQueue
/* virt queue functions */
static void virtqueue_init(VirtQueue *vq)
{
- target_phys_addr_t pa = vq->pa;
+ Phys pa = vq->pa;
vq->vring.desc = pa;
vq->vring.avail = pa + vq->vring.num * sizeof(VRingDesc);
@@ -93,51 +93,51 @@ static void virtqueue_init(VirtQueue *vq)
VIRTIO_PCI_VRING_ALIGN);
}
-static inline uint64_t vring_desc_addr(target_phys_addr_t desc_pa, int i)
+static inline uint64_t vring_desc_addr(Phys desc_pa, int i)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, addr);
return ldq_phys(pa);
}
-static inline uint32_t vring_desc_len(target_phys_addr_t desc_pa, int i)
+static inline uint32_t vring_desc_len(Phys desc_pa, int i)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, len);
return ldl_phys(pa);
}
-static inline uint16_t vring_desc_flags(target_phys_addr_t desc_pa, int i)
+static inline uint16_t vring_desc_flags(Phys desc_pa, int i)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, flags);
return lduw_phys(pa);
}
-static inline uint16_t vring_desc_next(target_phys_addr_t desc_pa, int i)
+static inline uint16_t vring_desc_next(Phys desc_pa, int i)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = desc_pa + sizeof(VRingDesc) * i + offsetof(VRingDesc, next);
return lduw_phys(pa);
}
static inline uint16_t vring_avail_flags(VirtQueue *vq)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = vq->vring.avail + offsetof(VRingAvail, flags);
return lduw_phys(pa);
}
static inline uint16_t vring_avail_idx(VirtQueue *vq)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = vq->vring.avail + offsetof(VRingAvail, idx);
return lduw_phys(pa);
}
static inline uint16_t vring_avail_ring(VirtQueue *vq, int i)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = vq->vring.avail + offsetof(VRingAvail, ring[i]);
return lduw_phys(pa);
}
@@ -149,49 +149,49 @@ static inline uint16_t vring_used_event(VirtQueue *vq)
static inline void vring_used_ring_id(VirtQueue *vq, int i, uint32_t val)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = vq->vring.used + offsetof(VRingUsed, ring[i].id);
stl_phys(pa, val);
}
static inline void vring_used_ring_len(VirtQueue *vq, int i, uint32_t val)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = vq->vring.used + offsetof(VRingUsed, ring[i].len);
stl_phys(pa, val);
}
static uint16_t vring_used_idx(VirtQueue *vq)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = vq->vring.used + offsetof(VRingUsed, idx);
return lduw_phys(pa);
}
static inline void vring_used_idx_set(VirtQueue *vq, uint16_t val)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = vq->vring.used + offsetof(VRingUsed, idx);
stw_phys(pa, val);
}
static inline void vring_used_flags_set_bit(VirtQueue *vq, int mask)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
stw_phys(pa, lduw_phys(pa) | mask);
}
static inline void vring_used_flags_unset_bit(VirtQueue *vq, int mask)
{
- target_phys_addr_t pa;
+ Phys pa;
pa = vq->vring.used + offsetof(VRingUsed, flags);
stw_phys(pa, lduw_phys(pa) & ~mask);
}
static inline void vring_avail_event(VirtQueue *vq, uint16_t val)
{
- target_phys_addr_t pa;
+ Phys pa;
if (!vq->notification) {
return;
}
@@ -304,7 +304,7 @@ static unsigned int virtqueue_get_head(VirtQueue *vq,
unsigned int idx)
return head;
}
-static unsigned virtqueue_next_desc(target_phys_addr_t desc_pa,
+static unsigned virtqueue_next_desc(Phys desc_pa,
unsigned int i, unsigned int max)
{
unsigned int next;
@@ -336,7 +336,7 @@ int virtqueue_avail_bytes(VirtQueue *vq, int in_bytes, int
out_bytes)
total_bufs = in_total = out_total = 0;
while (virtqueue_num_heads(vq, idx)) {
unsigned int max, num_bufs, indirect = 0;
- target_phys_addr_t desc_pa;
+ Phys desc_pa;
int i;
max = vq->vring.num;
@@ -390,11 +390,11 @@ int virtqueue_avail_bytes(VirtQueue *vq, int in_bytes,
int out_bytes)
return 0;
}
-void virtqueue_map_sg(struct iovec *sg, target_phys_addr_t *addr,
+void virtqueue_map_sg(struct iovec *sg, Phys *addr,
size_t num_sg, int is_write)
{
unsigned int i;
- target_phys_addr_t len;
+ Phys len;
for (i = 0; i < num_sg; i++) {
len = sg[i].iov_len;
@@ -409,7 +409,7 @@ void virtqueue_map_sg(struct iovec *sg, target_phys_addr_t
*addr,
int virtqueue_pop(VirtQueue *vq, VirtQueueElement *elem)
{
unsigned int i, head, max;
- target_phys_addr_t desc_pa = vq->vring.desc;
+ Phys desc_pa = vq->vring.desc;
if (!virtqueue_num_heads(vq, vq->last_avail_idx))
return 0;
@@ -608,13 +608,13 @@ void virtio_config_writel(VirtIODevice *vdev, uint32_t
addr, uint32_t data)
vdev->set_config(vdev, vdev->config);
}
-void virtio_queue_set_addr(VirtIODevice *vdev, int n, target_phys_addr_t addr)
+void virtio_queue_set_addr(VirtIODevice *vdev, int n, Phys addr)
{
vdev->vq[n].pa = addr;
virtqueue_init(&vdev->vq[n]);
}
-target_phys_addr_t virtio_queue_get_addr(VirtIODevice *vdev, int n)
+Phys virtio_queue_get_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].pa;
}
@@ -909,44 +909,44 @@ void virtio_bind_device(VirtIODevice *vdev, const
VirtIOBindings *binding,
vdev->binding_opaque = opaque;
}
-target_phys_addr_t virtio_queue_get_desc_addr(VirtIODevice *vdev, int n)
+Phys virtio_queue_get_desc_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.desc;
}
-target_phys_addr_t virtio_queue_get_avail_addr(VirtIODevice *vdev, int n)
+Phys virtio_queue_get_avail_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.avail;
}
-target_phys_addr_t virtio_queue_get_used_addr(VirtIODevice *vdev, int n)
+Phys virtio_queue_get_used_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.used;
}
-target_phys_addr_t virtio_queue_get_ring_addr(VirtIODevice *vdev, int n)
+Phys virtio_queue_get_ring_addr(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.desc;
}
-target_phys_addr_t virtio_queue_get_desc_size(VirtIODevice *vdev, int n)
+Phys virtio_queue_get_desc_size(VirtIODevice *vdev, int n)
{
return sizeof(VRingDesc) * vdev->vq[n].vring.num;
}
-target_phys_addr_t virtio_queue_get_avail_size(VirtIODevice *vdev, int n)
+Phys virtio_queue_get_avail_size(VirtIODevice *vdev, int n)
{
return offsetof(VRingAvail, ring) +
sizeof(uint64_t) * vdev->vq[n].vring.num;
}
-target_phys_addr_t virtio_queue_get_used_size(VirtIODevice *vdev, int n)
+Phys virtio_queue_get_used_size(VirtIODevice *vdev, int n)
{
return offsetof(VRingUsed, ring) +
sizeof(VRingUsedElem) * vdev->vq[n].vring.num;
}
-target_phys_addr_t virtio_queue_get_ring_size(VirtIODevice *vdev, int n)
+Phys virtio_queue_get_ring_size(VirtIODevice *vdev, int n)
{
return vdev->vq[n].vring.used - vdev->vq[n].vring.desc +
virtio_queue_get_used_size(vdev, n);
diff --git a/hw/virtio.h b/hw/virtio.h
index 25f5564..5dea5ef 100644
--- a/hw/virtio.h
+++ b/hw/virtio.h
@@ -70,7 +70,7 @@
struct VirtQueue;
-static inline target_phys_addr_t vring_align(target_phys_addr_t addr,
+static inline Phys vring_align(Phys addr,
unsigned long align)
{
return (addr + align - 1) & ~(align - 1);
@@ -85,8 +85,8 @@ typedef struct VirtQueueElement
unsigned int index;
unsigned int out_num;
unsigned int in_num;
- target_phys_addr_t in_addr[VIRTQUEUE_MAX_SIZE];
- target_phys_addr_t out_addr[VIRTQUEUE_MAX_SIZE];
+ Phys in_addr[VIRTQUEUE_MAX_SIZE];
+ Phys out_addr[VIRTQUEUE_MAX_SIZE];
struct iovec in_sg[VIRTQUEUE_MAX_SIZE];
struct iovec out_sg[VIRTQUEUE_MAX_SIZE];
} VirtQueueElement;
@@ -145,7 +145,7 @@ void virtqueue_flush(VirtQueue *vq, unsigned int count);
void virtqueue_fill(VirtQueue *vq, const VirtQueueElement *elem,
unsigned int len, unsigned int idx);
-void virtqueue_map_sg(struct iovec *sg, target_phys_addr_t *addr,
+void virtqueue_map_sg(struct iovec *sg, Phys *addr,
size_t num_sg, int is_write);
int virtqueue_pop(VirtQueue *vq, VirtQueueElement *elem);
int virtqueue_avail_bytes(VirtQueue *vq, int in_bytes, int out_bytes);
@@ -176,8 +176,8 @@ uint32_t virtio_config_readl(VirtIODevice *vdev, uint32_t
addr);
void virtio_config_writeb(VirtIODevice *vdev, uint32_t addr, uint32_t data);
void virtio_config_writew(VirtIODevice *vdev, uint32_t addr, uint32_t data);
void virtio_config_writel(VirtIODevice *vdev, uint32_t addr, uint32_t data);
-void virtio_queue_set_addr(VirtIODevice *vdev, int n, target_phys_addr_t addr);
-target_phys_addr_t virtio_queue_get_addr(VirtIODevice *vdev, int n);
+void virtio_queue_set_addr(VirtIODevice *vdev, int n, Phys addr);
+Phys virtio_queue_get_addr(VirtIODevice *vdev, int n);
int virtio_queue_get_num(VirtIODevice *vdev, int n);
void virtio_queue_notify(VirtIODevice *vdev, int n);
uint16_t virtio_queue_vector(VirtIODevice *vdev, int n);
@@ -215,14 +215,14 @@ void virtio_balloon_exit(VirtIODevice *vdev);
DEFINE_PROP_BIT("event_idx", _state, _field, \
VIRTIO_RING_F_EVENT_IDX, true)
-target_phys_addr_t virtio_queue_get_desc_addr(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_avail_addr(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_used_addr(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_ring_addr(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_desc_size(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_avail_size(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_used_size(VirtIODevice *vdev, int n);
-target_phys_addr_t virtio_queue_get_ring_size(VirtIODevice *vdev, int n);
+Phys virtio_queue_get_desc_addr(VirtIODevice *vdev, int n);
+Phys virtio_queue_get_avail_addr(VirtIODevice *vdev, int n);
+Phys virtio_queue_get_used_addr(VirtIODevice *vdev, int n);
+Phys virtio_queue_get_ring_addr(VirtIODevice *vdev, int n);
+Phys virtio_queue_get_desc_size(VirtIODevice *vdev, int n);
+Phys virtio_queue_get_avail_size(VirtIODevice *vdev, int n);
+Phys virtio_queue_get_used_size(VirtIODevice *vdev, int n);
+Phys virtio_queue_get_ring_size(VirtIODevice *vdev, int n);
uint16_t virtio_queue_get_last_avail_idx(VirtIODevice *vdev, int n);
void virtio_queue_set_last_avail_idx(VirtIODevice *vdev, int n, uint16_t idx);
VirtQueue *virtio_get_queue(VirtIODevice *vdev, int n);
diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index b1885c3..efcffb7 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -1130,7 +1130,7 @@ static void vmsvga_init(struct vmsvga_state_s *s, int
vga_ram_size,
}
}
-static uint64_t vmsvga_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t vmsvga_io_read(void *opaque, Phys addr,
unsigned size)
{
struct vmsvga_state_s *s = opaque;
@@ -1143,7 +1143,7 @@ static uint64_t vmsvga_io_read(void *opaque,
target_phys_addr_t addr,
}
}
-static void vmsvga_io_write(void *opaque, target_phys_addr_t addr,
+static void vmsvga_io_write(void *opaque, Phys addr,
uint64_t data, unsigned size)
{
struct vmsvga_state_s *s = opaque;
diff --git a/hw/wdt_i6300esb.c b/hw/wdt_i6300esb.c
index 20d8673..e66f597 100644
--- a/hw/wdt_i6300esb.c
+++ b/hw/wdt_i6300esb.c
@@ -257,14 +257,14 @@ static uint32_t i6300esb_config_read(PCIDevice *dev,
uint32_t addr, int len)
}
}
-static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr)
+static uint32_t i6300esb_mem_readb(void *vp, Phys addr)
{
i6300esb_debug ("addr = %x\n", (int) addr);
return 0;
}
-static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr)
+static uint32_t i6300esb_mem_readw(void *vp, Phys addr)
{
uint32_t data = 0;
I6300State *d = vp;
@@ -282,14 +282,14 @@ static uint32_t i6300esb_mem_readw(void *vp,
target_phys_addr_t addr)
return data;
}
-static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr)
+static uint32_t i6300esb_mem_readl(void *vp, Phys addr)
{
i6300esb_debug("addr = %x\n", (int) addr);
return 0;
}
-static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t
val)
+static void i6300esb_mem_writeb(void *vp, Phys addr, uint32_t val)
{
I6300State *d = vp;
@@ -301,7 +301,7 @@ static void i6300esb_mem_writeb(void *vp,
target_phys_addr_t addr, uint32_t val)
d->unlock_state = 2;
}
-static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t
val)
+static void i6300esb_mem_writew(void *vp, Phys addr, uint32_t val)
{
I6300State *d = vp;
@@ -334,7 +334,7 @@ static void i6300esb_mem_writew(void *vp,
target_phys_addr_t addr, uint32_t val)
}
}
-static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t
val)
+static void i6300esb_mem_writel(void *vp, Phys addr, uint32_t val)
{
I6300State *d = vp;
diff --git a/hw/xen_platform.c b/hw/xen_platform.c
index e62eaef..48456e3 100644
--- a/hw/xen_platform.c
+++ b/hw/xen_platform.c
@@ -288,7 +288,7 @@ static void platform_ioport_bar_setup(PCIXenPlatformState
*d)
memory_region_init_io(&d->bar, &xen_pci_io_ops, d, "xen-pci", 0x100);
}
-static uint64_t platform_mmio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t platform_mmio_read(void *opaque, Phys addr,
unsigned size)
{
DPRINTF("Warning: attempted read from physical address "
@@ -297,7 +297,7 @@ static uint64_t platform_mmio_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void platform_mmio_write(void *opaque, target_phys_addr_t addr,
+static void platform_mmio_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
diff --git a/hw/xilinx.h b/hw/xilinx.h
index 35f35bd..26fddf2 100644
--- a/hw/xilinx.h
+++ b/hw/xilinx.h
@@ -2,7 +2,7 @@
#include "net.h"
static inline DeviceState *
-xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int kind_of_intr)
+xilinx_intc_create(Phys base, qemu_irq irq, int kind_of_intr)
{
DeviceState *dev;
@@ -16,7 +16,7 @@ xilinx_intc_create(target_phys_addr_t base, qemu_irq irq, int
kind_of_intr)
/* OPB Timer/Counter. */
static inline DeviceState *
-xilinx_timer_create(target_phys_addr_t base, qemu_irq irq, int nr, int freq)
+xilinx_timer_create(Phys base, qemu_irq irq, int nr, int freq)
{
DeviceState *dev;
@@ -31,7 +31,7 @@ xilinx_timer_create(target_phys_addr_t base, qemu_irq irq,
int nr, int freq)
/* XPS Ethernet Lite MAC. */
static inline DeviceState *
-xilinx_ethlite_create(NICInfo *nd, target_phys_addr_t base, qemu_irq irq,
+xilinx_ethlite_create(NICInfo *nd, Phys base, qemu_irq irq,
int txpingpong, int rxpingpong)
{
DeviceState *dev;
@@ -50,7 +50,7 @@ xilinx_ethlite_create(NICInfo *nd, target_phys_addr_t base,
qemu_irq irq,
static inline DeviceState *
xilinx_axiethernet_create(void *dmach,
- NICInfo *nd, target_phys_addr_t base, qemu_irq irq,
+ NICInfo *nd, Phys base, qemu_irq irq,
int txmem, int rxmem)
{
DeviceState *dev;
@@ -70,7 +70,7 @@ xilinx_axiethernet_create(void *dmach,
static inline DeviceState *
xilinx_axiethernetdma_create(void *dmach,
- target_phys_addr_t base, qemu_irq irq,
+ Phys base, qemu_irq irq,
qemu_irq irq2, int freqhz)
{
DeviceState *dev = NULL;
diff --git a/hw/xilinx_axidma.c b/hw/xilinx_axidma.c
index 596ec0e..499eb13 100644
--- a/hw/xilinx_axidma.c
+++ b/hw/xilinx_axidma.c
@@ -139,7 +139,7 @@ static void stream_reset(struct AXIStream *s)
}
/* Map an offset addr into a channel index. */
-static inline int streamid_from_addr(target_phys_addr_t addr)
+static inline int streamid_from_addr(Phys addr)
{
int sid;
@@ -158,7 +158,7 @@ static void stream_desc_show(struct SDesc *d)
}
#endif
-static void stream_desc_load(struct AXIStream *s, target_phys_addr_t addr)
+static void stream_desc_load(struct AXIStream *s, Phys addr)
{
struct SDesc *d = &s->desc;
int i;
@@ -175,7 +175,7 @@ static void stream_desc_load(struct AXIStream *s,
target_phys_addr_t addr)
}
}
-static void stream_desc_store(struct AXIStream *s, target_phys_addr_t addr)
+static void stream_desc_store(struct AXIStream *s, Phys addr)
{
struct SDesc *d = &s->desc;
int i;
@@ -363,7 +363,7 @@ void axidma_push(void *opaque, unsigned char *buf, size_t
len, uint32_t *app)
stream_update_irq(s);
}
-static uint64_t axidma_read(void *opaque, target_phys_addr_t addr,
+static uint64_t axidma_read(void *opaque, Phys addr,
unsigned size)
{
struct XilinxAXIDMA *d = opaque;
@@ -398,7 +398,7 @@ static uint64_t axidma_read(void *opaque,
target_phys_addr_t addr,
}
-static void axidma_write(void *opaque, target_phys_addr_t addr,
+static void axidma_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct XilinxAXIDMA *d = opaque;
diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
index a2eb3e6..67794e7 100644
--- a/hw/xilinx_axienet.c
+++ b/hw/xilinx_axienet.c
@@ -412,7 +412,7 @@ static void enet_update_irq(struct XilinxAXIEnet *s)
qemu_set_irq(s->irq, !!s->regs[R_IP]);
}
-static uint64_t enet_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t enet_read(void *opaque, Phys addr, unsigned size)
{
struct XilinxAXIEnet *s = opaque;
uint32_t r = 0;
@@ -503,7 +503,7 @@ static uint64_t enet_read(void *opaque, target_phys_addr_t
addr, unsigned size)
return r;
}
-static void enet_write(void *opaque, target_phys_addr_t addr,
+static void enet_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
struct XilinxAXIEnet *s = opaque;
diff --git a/hw/xilinx_ethlite.c b/hw/xilinx_ethlite.c
index 6777254..ef3cda1 100644
--- a/hw/xilinx_ethlite.c
+++ b/hw/xilinx_ethlite.c
@@ -72,7 +72,7 @@ static inline void eth_pulse_irq(struct xlx_ethlite *s)
}
static uint64_t
-eth_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+eth_read(void *opaque, Phys addr, unsigned int size)
{
struct xlx_ethlite *s = opaque;
uint32_t r = 0;
@@ -100,7 +100,7 @@ static inline void eth_pulse_irq(struct xlx_ethlite *s)
}
static void
-eth_write(void *opaque, target_phys_addr_t addr,
+eth_write(void *opaque, Phys addr,
uint64_t val64, unsigned int size)
{
struct xlx_ethlite *s = opaque;
diff --git a/hw/xilinx_intc.c b/hw/xilinx_intc.c
index c567885..3a218ea 100644
--- a/hw/xilinx_intc.c
+++ b/hw/xilinx_intc.c
@@ -74,7 +74,7 @@ static void update_irq(struct xlx_pic *p)
}
static uint64_t
-pic_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+pic_read(void *opaque, Phys addr, unsigned int size)
{
struct xlx_pic *p = opaque;
uint32_t r = 0;
@@ -93,7 +93,7 @@ static void update_irq(struct xlx_pic *p)
}
static void
-pic_write(void *opaque, target_phys_addr_t addr,
+pic_write(void *opaque, Phys addr,
uint64_t val64, unsigned int size)
{
struct xlx_pic *p = opaque;
diff --git a/hw/xilinx_timer.c b/hw/xilinx_timer.c
index 0b2f32a..1ead4b4 100644
--- a/hw/xilinx_timer.c
+++ b/hw/xilinx_timer.c
@@ -66,7 +66,7 @@ struct timerblock
struct xlx_timer *timers;
};
-static inline unsigned int timer_from_addr(target_phys_addr_t addr)
+static inline unsigned int timer_from_addr(Phys addr)
{
/* Timers get a 4x32bit control reg area each. */
return addr >> 2;
@@ -87,7 +87,7 @@ static void timer_update_irq(struct timerblock *t)
}
static uint64_t
-timer_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+timer_read(void *opaque, Phys addr, unsigned int size)
{
struct timerblock *t = opaque;
struct xlx_timer *xt;
@@ -136,7 +136,7 @@ static void timer_enable(struct xlx_timer *xt)
}
static void
-timer_write(void *opaque, target_phys_addr_t addr,
+timer_write(void *opaque, Phys addr,
uint64_t val64, unsigned int size)
{
struct timerblock *t = opaque;
diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c
index 6533df9..9c080d1 100644
--- a/hw/xilinx_uartlite.c
+++ b/hw/xilinx_uartlite.c
@@ -84,7 +84,7 @@ static void uart_update_status(struct xlx_uartlite *s)
}
static uint64_t
-uart_read(void *opaque, target_phys_addr_t addr, unsigned int size)
+uart_read(void *opaque, Phys addr, unsigned int size)
{
struct xlx_uartlite *s = opaque;
uint32_t r = 0;
@@ -109,7 +109,7 @@ static void uart_update_status(struct xlx_uartlite *s)
}
static void
-uart_write(void *opaque, target_phys_addr_t addr,
+uart_write(void *opaque, Phys addr,
uint64_t val64, unsigned int size)
{
struct xlx_uartlite *s = opaque;
diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c
index 26112c3..fe3d74d 100644
--- a/hw/xtensa_lx60.c
+++ b/hw/xtensa_lx60.c
@@ -56,7 +56,7 @@ static void lx60_fpga_reset(void *opaque)
s->switches = 0;
}
-static uint64_t lx60_fpga_read(void *opaque, target_phys_addr_t addr,
+static uint64_t lx60_fpga_read(void *opaque, Phys addr,
unsigned size)
{
Lx60FpgaState *s = opaque;
@@ -77,7 +77,7 @@ static uint64_t lx60_fpga_read(void *opaque,
target_phys_addr_t addr,
return 0;
}
-static void lx60_fpga_write(void *opaque, target_phys_addr_t addr,
+static void lx60_fpga_write(void *opaque, Phys addr,
uint64_t val, unsigned size)
{
Lx60FpgaState *s = opaque;
@@ -102,7 +102,7 @@ static void lx60_fpga_write(void *opaque,
target_phys_addr_t addr,
};
static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space,
- target_phys_addr_t base)
+ Phys base)
{
Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState));
@@ -115,9 +115,9 @@ static void lx60_fpga_write(void *opaque,
target_phys_addr_t addr,
}
static void lx60_net_init(MemoryRegion *address_space,
- target_phys_addr_t base,
- target_phys_addr_t descriptors,
- target_phys_addr_t buffers,
+ Phys base,
+ Phys descriptors,
+ Phys buffers,
qemu_irq irq, NICInfo *nd)
{
DeviceState *dev;
diff --git a/hw/zaurus.c b/hw/zaurus.c
index c4bcd29..f25da61 100644
--- a/hw/zaurus.c
+++ b/hw/zaurus.c
@@ -68,7 +68,7 @@ static inline void scoop_gpio_handler_update(ScoopInfo *s) {
s->prev_level = level;
}
-static uint64_t scoop_read(void *opaque, target_phys_addr_t addr,
+static uint64_t scoop_read(void *opaque, Phys addr,
unsigned size)
{
ScoopInfo *s = (ScoopInfo *) opaque;
@@ -102,7 +102,7 @@ static uint64_t scoop_read(void *opaque, target_phys_addr_t
addr,
return 0;
}
-static void scoop_write(void *opaque, target_phys_addr_t addr,
+static void scoop_write(void *opaque, Phys addr,
uint64_t value, unsigned size)
{
ScoopInfo *s = (ScoopInfo *) opaque;
@@ -273,7 +273,7 @@ static void scoop_register(void)
.phadadj = 0x01,
};
-void sl_bootparam_write(target_phys_addr_t ptr)
+void sl_bootparam_write(Phys ptr)
{
cpu_physical_memory_write(ptr, (void *)&zaurus_bootparam,
sizeof(struct sl_param_info));
diff --git a/kvm-all.c b/kvm-all.c
index 3174f42..d7d9399 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -49,7 +49,7 @@
typedef struct KVMSlot
{
- target_phys_addr_t start_addr;
+ Phys start_addr;
ram_addr_t memory_size;
void *ram;
int slot;
@@ -103,8 +103,8 @@ struct KVMState
}
static KVMSlot *kvm_lookup_matching_slot(KVMState *s,
- target_phys_addr_t start_addr,
- target_phys_addr_t end_addr)
+ Phys start_addr,
+ Phys end_addr)
{
int i;
@@ -124,8 +124,8 @@ struct KVMState
* Find overlapping slot with lowest start address
*/
static KVMSlot *kvm_lookup_overlapping_slot(KVMState *s,
- target_phys_addr_t start_addr,
- target_phys_addr_t end_addr)
+ Phys start_addr,
+ Phys end_addr)
{
KVMSlot *found = NULL;
int i;
@@ -148,7 +148,7 @@ struct KVMState
}
int kvm_physical_memory_addr_from_host(KVMState *s, void *ram,
- target_phys_addr_t *phys_addr)
+ Phys *phys_addr)
{
int i;
@@ -275,7 +275,7 @@ static int kvm_slot_dirty_pages_log_change(KVMSlot *mem,
bool log_dirty)
return kvm_set_user_memory_region(s, mem);
}
-static int kvm_dirty_pages_log_change(target_phys_addr_t phys_addr,
+static int kvm_dirty_pages_log_change(Phys phys_addr,
ram_addr_t size, bool log_dirty)
{
KVMState *s = kvm_state;
@@ -284,7 +284,7 @@ static int kvm_dirty_pages_log_change(target_phys_addr_t
phys_addr,
if (mem == NULL) {
fprintf(stderr, "BUG: %s: invalid parameters " TARGET_FMT_plx "-"
TARGET_FMT_plx "\n", __func__, phys_addr,
- (target_phys_addr_t)(phys_addr + size - 1));
+ (Phys)(phys_addr + size - 1));
return -EINVAL;
}
return kvm_slot_dirty_pages_log_change(mem, log_dirty);
@@ -384,8 +384,8 @@ static int
kvm_physical_sync_dirty_bitmap(MemoryRegionSection *section)
KVMDirtyLog d;
KVMSlot *mem;
int ret = 0;
- target_phys_addr_t start_addr = section->offset_within_address_space;
- target_phys_addr_t end_addr = start_addr + section->size;
+ Phys start_addr = section->offset_within_address_space;
+ Phys end_addr = start_addr + section->size;
d.dirty_bitmap = NULL;
while (start_addr < end_addr) {
@@ -432,7 +432,7 @@ static int
kvm_physical_sync_dirty_bitmap(MemoryRegionSection *section)
return ret;
}
-int kvm_coalesce_mmio_region(target_phys_addr_t start, ram_addr_t size)
+int kvm_coalesce_mmio_region(Phys start, ram_addr_t size)
{
int ret = -ENOSYS;
KVMState *s = kvm_state;
@@ -449,7 +449,7 @@ int kvm_coalesce_mmio_region(target_phys_addr_t start,
ram_addr_t size)
return ret;
}
-int kvm_uncoalesce_mmio_region(target_phys_addr_t start, ram_addr_t size)
+int kvm_uncoalesce_mmio_region(Phys start, ram_addr_t size)
{
int ret = -ENOSYS;
KVMState *s = kvm_state;
@@ -534,7 +534,7 @@ static void kvm_set_phys_mem(MemoryRegionSection *section,
bool add)
int err;
MemoryRegion *mr = section->mr;
bool log_dirty = memory_region_is_logging(mr);
- target_phys_addr_t start_addr = section->offset_within_address_space;
+ Phys start_addr = section->offset_within_address_space;
ram_addr_t size = section->size;
void *ram = NULL;
diff --git a/kvm-stub.c b/kvm-stub.c
index 06064b9..cab465d 100644
--- a/kvm-stub.c
+++ b/kvm-stub.c
@@ -32,12 +32,12 @@ int kvm_init_vcpu(CPUState *env)
return -ENOSYS;
}
-int kvm_coalesce_mmio_region(target_phys_addr_t start, ram_addr_t size)
+int kvm_coalesce_mmio_region(Phys start, ram_addr_t size)
{
return -ENOSYS;
}
-int kvm_uncoalesce_mmio_region(target_phys_addr_t start, ram_addr_t size)
+int kvm_uncoalesce_mmio_region(Phys start, ram_addr_t size)
{
return -ENOSYS;
}
diff --git a/kvm.h b/kvm.h
index c1de81a..f4fe04e 100644
--- a/kvm.h
+++ b/kvm.h
@@ -60,8 +60,8 @@ int kvm_cpu_exec(CPUState *env);
#if !defined(CONFIG_USER_ONLY)
void kvm_setup_guest_memory(void *start, size_t size);
-int kvm_coalesce_mmio_region(target_phys_addr_t start, ram_addr_t size);
-int kvm_uncoalesce_mmio_region(target_phys_addr_t start, ram_addr_t size);
+int kvm_coalesce_mmio_region(Phys start, ram_addr_t size);
+int kvm_uncoalesce_mmio_region(Phys start, ram_addr_t size);
void kvm_flush_coalesced_mmio_buffer(void);
#endif
@@ -189,7 +189,7 @@ static inline void cpu_synchronize_post_init(CPUState *env)
#if !defined(CONFIG_USER_ONLY)
int kvm_physical_memory_addr_from_host(KVMState *s, void *ram_addr,
- target_phys_addr_t *phys_addr);
+ Phys *phys_addr);
#endif
#endif
diff --git a/memory.c b/memory.c
index 394cbab..5e10156 100644
--- a/memory.c
+++ b/memory.c
@@ -135,7 +135,7 @@ static bool
memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
/* Range of memory in the global map. Addresses are absolute. */
struct FlatRange {
MemoryRegion *mr;
- target_phys_addr_t offset_in_region;
+ Phys offset_in_region;
AddrRange addr;
uint8_t dirty_log_mask;
bool readable;
@@ -245,7 +245,7 @@ static void flatview_simplify(FlatView *view)
}
static void memory_region_read_accessor(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
uint64_t *value,
unsigned size,
unsigned shift,
@@ -259,7 +259,7 @@ static void memory_region_read_accessor(void *opaque,
}
static void memory_region_write_accessor(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
uint64_t *value,
unsigned size,
unsigned shift,
@@ -272,13 +272,13 @@ static void memory_region_write_accessor(void *opaque,
mr->ops->write(mr->opaque, addr, tmp, size);
}
-static void access_with_adjusted_size(target_phys_addr_t addr,
+static void access_with_adjusted_size(Phys addr,
uint64_t *value,
unsigned size,
unsigned access_size_min,
unsigned access_size_max,
void (*access)(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
uint64_t *value,
unsigned size,
unsigned shift,
@@ -519,7 +519,7 @@ static void render_memory_region(FlatView *view,
{
MemoryRegion *subregion;
unsigned i;
- target_phys_addr_t offset_in_region;
+ Phys offset_in_region;
Int128 remain;
Int128 now;
FlatRange fr;
@@ -883,7 +883,7 @@ void memory_region_init(MemoryRegion *mr,
}
static bool memory_region_access_valid(MemoryRegion *mr,
- target_phys_addr_t addr,
+ Phys addr,
unsigned size,
bool is_write)
{
@@ -909,7 +909,7 @@ static bool memory_region_access_valid(MemoryRegion *mr,
}
static uint64_t memory_region_dispatch_read1(MemoryRegion *mr,
- target_phys_addr_t addr,
+ Phys addr,
unsigned size)
{
uint64_t data = 0;
@@ -949,7 +949,7 @@ static void adjust_endianness(MemoryRegion *mr, uint64_t
*data, unsigned size)
}
static uint64_t memory_region_dispatch_read(MemoryRegion *mr,
- target_phys_addr_t addr,
+ Phys addr,
unsigned size)
{
uint64_t ret;
@@ -960,7 +960,7 @@ static uint64_t memory_region_dispatch_read(MemoryRegion
*mr,
}
static void memory_region_dispatch_write(MemoryRegion *mr,
- target_phys_addr_t addr,
+ Phys addr,
uint64_t data,
unsigned size)
{
@@ -1022,7 +1022,7 @@ void memory_region_init_ram_ptr(MemoryRegion *mr,
void memory_region_init_alias(MemoryRegion *mr,
const char *name,
MemoryRegion *orig,
- target_phys_addr_t offset,
+ Phys offset,
uint64_t size)
{
memory_region_init(mr, name, size);
@@ -1083,7 +1083,7 @@ bool memory_region_is_rom(MemoryRegion *mr)
return mr->ram && mr->readonly;
}
-void memory_region_set_offset(MemoryRegion *mr, target_phys_addr_t offset)
+void memory_region_set_offset(MemoryRegion *mr, Phys offset)
{
mr->offset = offset;
}
@@ -1096,14 +1096,14 @@ void memory_region_set_log(MemoryRegion *mr, bool log,
unsigned client)
memory_region_update_topology(mr);
}
-bool memory_region_get_dirty(MemoryRegion *mr, target_phys_addr_t addr,
+bool memory_region_get_dirty(MemoryRegion *mr, Phys addr,
unsigned client)
{
assert(mr->terminates);
return cpu_physical_memory_get_dirty(mr->ram_addr + addr, 1 << client);
}
-void memory_region_set_dirty(MemoryRegion *mr, target_phys_addr_t addr)
+void memory_region_set_dirty(MemoryRegion *mr, Phys addr)
{
assert(mr->terminates);
return cpu_physical_memory_set_dirty(mr->ram_addr + addr);
@@ -1136,8 +1136,8 @@ void memory_region_rom_device_set_readable(MemoryRegion
*mr, bool readable)
}
}
-void memory_region_reset_dirty(MemoryRegion *mr, target_phys_addr_t addr,
- target_phys_addr_t size, unsigned client)
+void memory_region_reset_dirty(MemoryRegion *mr, Phys addr,
+ Phys size, unsigned client)
{
assert(mr->terminates);
cpu_physical_memory_reset_dirty(mr->ram_addr + addr,
@@ -1188,7 +1188,7 @@ void memory_region_set_coalescing(MemoryRegion *mr)
}
void memory_region_add_coalescing(MemoryRegion *mr,
- target_phys_addr_t offset,
+ Phys offset,
uint64_t size)
{
CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
@@ -1211,7 +1211,7 @@ void memory_region_clear_coalescing(MemoryRegion *mr)
}
void memory_region_add_eventfd(MemoryRegion *mr,
- target_phys_addr_t addr,
+ Phys addr,
unsigned size,
bool match_data,
uint64_t data,
@@ -1241,7 +1241,7 @@ void memory_region_add_eventfd(MemoryRegion *mr,
}
void memory_region_del_eventfd(MemoryRegion *mr,
- target_phys_addr_t addr,
+ Phys addr,
unsigned size,
bool match_data,
uint64_t data,
@@ -1271,7 +1271,7 @@ void memory_region_del_eventfd(MemoryRegion *mr,
}
static void memory_region_add_subregion_common(MemoryRegion *mr,
- target_phys_addr_t offset,
+ Phys offset,
MemoryRegion *subregion)
{
MemoryRegion *other;
@@ -1313,7 +1313,7 @@ static void
memory_region_add_subregion_common(MemoryRegion *mr,
void memory_region_add_subregion(MemoryRegion *mr,
- target_phys_addr_t offset,
+ Phys offset,
MemoryRegion *subregion)
{
subregion->may_overlap = false;
@@ -1322,7 +1322,7 @@ void memory_region_add_subregion(MemoryRegion *mr,
}
void memory_region_add_subregion_overlap(MemoryRegion *mr,
- target_phys_addr_t offset,
+ Phys offset,
MemoryRegion *subregion,
unsigned priority)
{
@@ -1349,7 +1349,7 @@ void memory_region_set_enabled(MemoryRegion *mr, bool
enabled)
memory_region_update_topology(NULL);
}
-void memory_region_set_address(MemoryRegion *mr, target_phys_addr_t addr)
+void memory_region_set_address(MemoryRegion *mr, Phys addr)
{
MemoryRegion *parent = mr->parent;
unsigned priority = mr->priority;
@@ -1370,9 +1370,9 @@ void memory_region_set_address(MemoryRegion *mr,
target_phys_addr_t addr)
memory_region_transaction_commit();
}
-void memory_region_set_alias_offset(MemoryRegion *mr, target_phys_addr_t
offset)
+void memory_region_set_alias_offset(MemoryRegion *mr, Phys offset)
{
- target_phys_addr_t old_offset = mr->alias_offset;
+ Phys old_offset = mr->alias_offset;
assert(mr->alias);
mr->alias_offset = offset;
@@ -1409,7 +1409,7 @@ static int cmp_flatrange_addr(const void *addr_, const
void *fr_)
}
MemoryRegionSection memory_region_find(MemoryRegion *address_space,
- target_phys_addr_t addr, uint64_t size)
+ Phys addr, uint64_t size)
{
AddressSpace *as = memory_region_to_address_space(address_space);
AddrRange range = addrrange_make(int128_make64(addr),
@@ -1512,12 +1512,12 @@ void set_system_io_map(MemoryRegion *mr)
memory_region_update_topology(NULL);
}
-uint64_t io_mem_read(int io_index, target_phys_addr_t addr, unsigned size)
+uint64_t io_mem_read(int io_index, Phys addr, unsigned size)
{
return memory_region_dispatch_read(io_mem_region[io_index], addr, size);
}
-void io_mem_write(int io_index, target_phys_addr_t addr,
+void io_mem_write(int io_index, Phys addr,
uint64_t val, unsigned size)
{
memory_region_dispatch_write(io_mem_region[io_index], addr, val, size);
@@ -1535,7 +1535,7 @@ struct MemoryRegionList {
static void mtree_print_mr(fprintf_function mon_printf, void *f,
const MemoryRegion *mr, unsigned int level,
- target_phys_addr_t base,
+ Phys base,
MemoryRegionListHead *alias_print_queue)
{
MemoryRegionList *new_ml, *ml, *next_ml;
@@ -1572,18 +1572,18 @@ static void mtree_print_mr(fprintf_function mon_printf,
void *f,
TARGET_FMT_plx "-" TARGET_FMT_plx "\n",
base + mr->addr,
base + mr->addr
- + (target_phys_addr_t)int128_get64(mr->size) - 1,
+ + (Phys)int128_get64(mr->size) - 1,
mr->priority,
mr->name,
mr->alias->name,
mr->alias_offset,
mr->alias_offset
- + (target_phys_addr_t)int128_get64(mr->size) - 1);
+ + (Phys)int128_get64(mr->size) - 1);
} else {
mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d): %s\n",
base + mr->addr,
base + mr->addr
- + (target_phys_addr_t)int128_get64(mr->size) - 1,
+ + (Phys)int128_get64(mr->size) - 1,
mr->priority,
mr->name);
}
diff --git a/memory.h b/memory.h
index 70f57fb..45c123f 100644
--- a/memory.h
+++ b/memory.h
@@ -50,12 +50,12 @@ struct MemoryRegionOps {
/* Read from the memory region. @addr is relative to @mr; @size is
* in bytes. */
uint64_t (*read)(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
unsigned size);
/* Write to the memory region. @addr is relative to @mr; @size is
* in bytes. */
void (*write)(void *opaque,
- target_phys_addr_t addr,
+ Phys addr,
uint64_t data,
unsigned size);
@@ -76,7 +76,7 @@ struct MemoryRegionOps {
* by the device (and results in machine dependent behaviour such
* as a machine check exception).
*/
- bool (*accepts)(void *opaque, target_phys_addr_t addr,
+ bool (*accepts)(void *opaque, Phys addr,
unsigned size, bool is_write);
} valid;
/* Internal implementation constraints: */
@@ -114,8 +114,8 @@ struct MemoryRegion {
void *opaque;
MemoryRegion *parent;
Int128 size;
- target_phys_addr_t addr;
- target_phys_addr_t offset;
+ Phys addr;
+ Phys offset;
void (*destructor)(MemoryRegion *mr);
ram_addr_t ram_addr;
IORange iorange;
@@ -127,7 +127,7 @@ struct MemoryRegion {
bool enabled;
bool rom_device;
MemoryRegion *alias;
- target_phys_addr_t alias_offset;
+ Phys alias_offset;
unsigned priority;
bool may_overlap;
QTAILQ_HEAD(subregions, MemoryRegion) subregions;
@@ -164,9 +164,9 @@ typedef struct MemoryRegionSection MemoryRegionSection;
struct MemoryRegionSection {
MemoryRegion *mr;
MemoryRegion *address_space;
- target_phys_addr_t offset_within_region;
+ Phys offset_within_region;
uint64_t size;
- target_phys_addr_t offset_within_address_space;
+ Phys offset_within_address_space;
};
typedef struct MemoryListener MemoryListener;
@@ -261,7 +261,7 @@ void memory_region_init_ram_ptr(MemoryRegion *mr,
void memory_region_init_alias(MemoryRegion *mr,
const char *name,
MemoryRegion *orig,
- target_phys_addr_t offset,
+ Phys offset,
uint64_t size);
/**
@@ -348,7 +348,7 @@ void *memory_region_get_ram_ptr(MemoryRegion *mr);
*
* This function is deprecated and should not be used in new code.
*/
-void memory_region_set_offset(MemoryRegion *mr, target_phys_addr_t offset);
+void memory_region_set_offset(MemoryRegion *mr, Phys offset);
/**
* memory_region_set_log: Turn dirty logging on or off for a region.
@@ -376,7 +376,7 @@ void memory_region_set_log(MemoryRegion *mr, bool log,
unsigned client);
* @client: the user of the logging information; %DIRTY_MEMORY_MIGRATION or
* %DIRTY_MEMORY_VGA.
*/
-bool memory_region_get_dirty(MemoryRegion *mr, target_phys_addr_t addr,
+bool memory_region_get_dirty(MemoryRegion *mr, Phys addr,
unsigned client);
/**
@@ -387,7 +387,7 @@ bool memory_region_get_dirty(MemoryRegion *mr,
target_phys_addr_t addr,
* @mr: the memory region being queried.
* @addr: the address (relative to the start of the region) being dirtied.
*/
-void memory_region_set_dirty(MemoryRegion *mr, target_phys_addr_t addr);
+void memory_region_set_dirty(MemoryRegion *mr, Phys addr);
/**
* memory_region_sync_dirty_bitmap: Synchronize a region's dirty bitmap with
@@ -412,8 +412,8 @@ void memory_region_sync_dirty_bitmap(MemoryRegion *mr);
* @client: the user of the logging information; %DIRTY_MEMORY_MIGRATION or
* %DIRTY_MEMORY_VGA.
*/
-void memory_region_reset_dirty(MemoryRegion *mr, target_phys_addr_t addr,
- target_phys_addr_t size, unsigned client);
+void memory_region_reset_dirty(MemoryRegion *mr, Phys addr,
+ Phys size, unsigned client);
/**
* memory_region_set_readonly: Turn a memory region read-only (or read-write)
@@ -463,7 +463,7 @@ void memory_region_set_coalescing(MemoryRegion *mr);
* @size: the size of the subrange to be coalesced.
*/
void memory_region_add_coalescing(MemoryRegion *mr,
- target_phys_addr_t offset,
+ Phys offset,
uint64_t size);
/**
@@ -494,7 +494,7 @@ void memory_region_clear_coalescing(MemoryRegion *mr);
* @fd: the eventfd to be triggered when @addr, @size, and @data all match.
**/
void memory_region_add_eventfd(MemoryRegion *mr,
- target_phys_addr_t addr,
+ Phys addr,
unsigned size,
bool match_data,
uint64_t data,
@@ -514,7 +514,7 @@ void memory_region_add_eventfd(MemoryRegion *mr,
* @fd: the eventfd to be triggered when @addr, @size, and @data all match.
*/
void memory_region_del_eventfd(MemoryRegion *mr,
- target_phys_addr_t addr,
+ Phys addr,
unsigned size,
bool match_data,
uint64_t data,
@@ -534,7 +534,7 @@ void memory_region_del_eventfd(MemoryRegion *mr,
* @subregion: the subregion to be added.
*/
void memory_region_add_subregion(MemoryRegion *mr,
- target_phys_addr_t offset,
+ Phys offset,
MemoryRegion *subregion);
/**
* memory_region_add_subregion: Add a subregion to a container, with overlap.
@@ -553,7 +553,7 @@ void memory_region_add_subregion(MemoryRegion *mr,
* @priority: used for resolving overlaps; highest priority wins.
*/
void memory_region_add_subregion_overlap(MemoryRegion *mr,
- target_phys_addr_t offset,
+ Phys offset,
MemoryRegion *subregion,
unsigned priority);
@@ -601,7 +601,7 @@ void memory_region_set_enabled(MemoryRegion *mr, bool
enabled);
* @mr: the region to be updated
* @addr: new address, relative to parent region
*/
-void memory_region_set_address(MemoryRegion *mr, target_phys_addr_t addr);
+void memory_region_set_address(MemoryRegion *mr, Phys addr);
/*
* memory_region_set_alias_offset: dynamically update a memory alias's offset
@@ -613,7 +613,7 @@ void memory_region_set_address(MemoryRegion *mr,
target_phys_addr_t addr);
* @offset: the new offset into the target memory region
*/
void memory_region_set_alias_offset(MemoryRegion *mr,
- target_phys_addr_t offset);
+ Phys offset);
/**
* memory_region_find: locate a MemoryRegion in an address space
@@ -634,7 +634,7 @@ void memory_region_set_alias_offset(MemoryRegion *mr,
* @size: size of the area to be searched
*/
MemoryRegionSection memory_region_find(MemoryRegion *address_space,
- target_phys_addr_t addr, uint64_t size);
+ Phys addr, uint64_t size);
/**
diff --git a/monitor.c b/monitor.c
index 7334401..5d07371 100644
--- a/monitor.c
+++ b/monitor.c
@@ -1130,7 +1130,7 @@ static void monitor_printc(Monitor *mon, int c)
}
static void memory_dump(Monitor *mon, int count, int format, int wsize,
- target_phys_addr_t addr, int is_physical)
+ Phys addr, int is_physical)
{
CPUState *env;
int l, line_size, i, max_digits, len;
@@ -1264,7 +1264,7 @@ static void do_physical_memory_dump(Monitor *mon, const
QDict *qdict)
int count = qdict_get_int(qdict, "count");
int format = qdict_get_int(qdict, "format");
int size = qdict_get_int(qdict, "size");
- target_phys_addr_t addr = qdict_get_int(qdict, "addr");
+ Phys addr = qdict_get_int(qdict, "addr");
memory_dump(mon, count, format, size, addr, 1);
}
@@ -1272,7 +1272,7 @@ static void do_physical_memory_dump(Monitor *mon, const
QDict *qdict)
static void do_print(Monitor *mon, const QDict *qdict)
{
int format = qdict_get_int(qdict, "format");
- target_phys_addr_t val = qdict_get_int(qdict, "val");
+ Phys val = qdict_get_int(qdict, "val");
#if TARGET_PHYS_ADDR_BITS == 32
switch(format) {
@@ -1668,9 +1668,9 @@ static void do_boot_set(Monitor *mon, const QDict *qdict)
}
#if defined(TARGET_I386)
-static void print_pte(Monitor *mon, target_phys_addr_t addr,
- target_phys_addr_t pte,
- target_phys_addr_t mask)
+static void print_pte(Monitor *mon, Phys addr,
+ Phys pte,
+ Phys mask)
{
#ifdef TARGET_X86_64
if (addr & (1ULL << 47)) {
@@ -1739,7 +1739,7 @@ static void tlb_info_pae32(Monitor *mon, CPUState *env)
if (pde & PG_PSE_MASK) {
/* 2M pages with PAE, CR4.PSE is ignored */
print_pte(mon, (l1 << 30 ) + (l2 << 21), pde,
- ~((target_phys_addr_t)(1 << 20) - 1));
+ ~((Phys)(1 << 20) - 1));
} else {
pt_addr = pde & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
@@ -1749,7 +1749,7 @@ static void tlb_info_pae32(Monitor *mon, CPUState *env)
print_pte(mon, (l1 << 30 ) + (l2 << 21)
+ (l3 << 12),
pte & ~PG_PSE_MASK,
- ~(target_phys_addr_t)0xfff);
+ ~(Phys)0xfff);
}
}
}
@@ -1841,9 +1841,9 @@ static void tlb_info(Monitor *mon)
}
}
-static void mem_print(Monitor *mon, target_phys_addr_t *pstart,
+static void mem_print(Monitor *mon, Phys *pstart,
int *plast_prot,
- target_phys_addr_t end, int prot)
+ Phys end, int prot)
{
int prot1;
prot1 = *plast_prot;
@@ -1869,7 +1869,7 @@ static void mem_info_32(Monitor *mon, CPUState *env)
unsigned int l1, l2;
int prot, last_prot;
uint32_t pgd, pde, pte;
- target_phys_addr_t start, end;
+ Phys start, end;
pgd = env->cr[3] & ~0xfff;
last_prot = 0;
@@ -1902,7 +1902,7 @@ static void mem_info_32(Monitor *mon, CPUState *env)
}
}
/* Flush last range */
- mem_print(mon, &start, &last_prot, (target_phys_addr_t)1 << 32, 0);
+ mem_print(mon, &start, &last_prot, (Phys)1 << 32, 0);
}
static void mem_info_pae32(Monitor *mon, CPUState *env)
@@ -1911,7 +1911,7 @@ static void mem_info_pae32(Monitor *mon, CPUState *env)
int prot, last_prot;
uint64_t pdpe, pde, pte;
uint64_t pdp_addr, pd_addr, pt_addr;
- target_phys_addr_t start, end;
+ Phys start, end;
pdp_addr = env->cr[3] & ~0x1f;
last_prot = 0;
@@ -1957,7 +1957,7 @@ static void mem_info_pae32(Monitor *mon, CPUState *env)
}
}
/* Flush last range */
- mem_print(mon, &start, &last_prot, (target_phys_addr_t)1 << 32, 0);
+ mem_print(mon, &start, &last_prot, (Phys)1 << 32, 0);
}
@@ -2036,7 +2036,7 @@ static void mem_info_64(Monitor *mon, CPUState *env)
}
}
/* Flush last range */
- mem_print(mon, &start, &last_prot, (target_phys_addr_t)1 << 48, 0);
+ mem_print(mon, &start, &last_prot, (Phys)1 << 48, 0);
}
#endif
diff --git a/softmmu_template.h b/softmmu_template.h
index 97020f8..9dc1367 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -57,7 +57,7 @@
static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
int mmu_idx,
void *retaddr);
-static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
+static inline DATA_TYPE glue(io_read, SUFFIX)(Phys physaddr,
target_ulong addr,
void *retaddr)
{
@@ -95,7 +95,7 @@ DATA_TYPE REGPARM glue(glue(__ld, SUFFIX),
MMUSUFFIX)(target_ulong addr,
DATA_TYPE res;
int index;
target_ulong tlb_addr;
- target_phys_addr_t ioaddr;
+ Phys ioaddr;
unsigned long addend;
void *retaddr;
@@ -152,7 +152,7 @@ static DATA_TYPE glue(glue(slow_ld, SUFFIX),
MMUSUFFIX)(target_ulong addr,
{
DATA_TYPE res, res1, res2;
int index, shift;
- target_phys_addr_t ioaddr;
+ Phys ioaddr;
unsigned long addend;
target_ulong tlb_addr, addr1, addr2;
@@ -202,7 +202,7 @@ static void glue(glue(slow_st, SUFFIX),
MMUSUFFIX)(target_ulong addr,
int mmu_idx,
void *retaddr);
-static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
+static inline void glue(io_write, SUFFIX)(Phys physaddr,
DATA_TYPE val,
target_ulong addr,
void *retaddr)
@@ -236,7 +236,7 @@ void REGPARM glue(glue(__st, SUFFIX),
MMUSUFFIX)(target_ulong addr,
DATA_TYPE val,
int mmu_idx)
{
- target_phys_addr_t ioaddr;
+ Phys ioaddr;
unsigned long addend;
target_ulong tlb_addr;
void *retaddr;
@@ -290,7 +290,7 @@ static void glue(glue(slow_st, SUFFIX),
MMUSUFFIX)(target_ulong addr,
int mmu_idx,
void *retaddr)
{
- target_phys_addr_t ioaddr;
+ Phys ioaddr;
unsigned long addend;
target_ulong tlb_addr;
int index, i;
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 9d61d45..7f82b80 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -439,7 +439,7 @@ void cpu_alpha_store_fpcr (CPUState *env, uint64_t val);
#ifndef CONFIG_USER_ONLY
void swap_shadow_regs(CPUState *env);
QEMU_NORETURN void cpu_unassigned_access(CPUState *env1,
- target_phys_addr_t addr, int is_write,
+ Phys addr, int is_write,
int is_exec, int unused, int size);
#endif
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index 06d2565..8cc81fa 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -306,7 +306,7 @@ static int get_physical_address(CPUState *env, target_ulong
addr,
return ret;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+Phys cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
target_ulong phys;
int prot, fail;
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index cc102db..5432ea7 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -1330,7 +1330,7 @@ static void QEMU_NORETURN
do_unaligned_access(target_ulong addr, int is_write,
}
void QEMU_NORETURN cpu_unassigned_access(CPUState *env1,
- target_phys_addr_t addr, int is_write,
+ Phys addr, int is_write,
int is_exec, int unused, int size)
{
env = env1;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 65f4fbf..adbf664 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1319,7 +1319,7 @@ int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong
address,
return 1;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+Phys cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
uint32_t phys_addr;
target_ulong page_size;
diff --git a/target-cris/helper.c b/target-cris/helper.c
index 5bc6d81..0ac7332 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -250,7 +250,7 @@ void do_interrupt(CPUState *env)
env->pregs[PR_ERP]);
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
+Phys cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
uint32_t phy = addr;
struct cris_mmu_result res;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 2586aff..a760632 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -579,7 +579,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong
addr,
uint64_t ptep, pte;
target_ulong pde_addr, pte_addr;
int error_code, is_dirty, prot, page_size, is_write, is_user;
- target_phys_addr_t paddr;
+ Phys paddr;
uint32_t page_offset;
target_ulong vaddr, virt_addr;
@@ -863,11 +863,11 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env,
target_ulong addr,
return 1;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+Phys cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
target_ulong pde_addr, pte_addr;
uint64_t pte;
- target_phys_addr_t paddr;
+ Phys paddr;
uint32_t page_offset;
int page_size;
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 04e65c5..bf12a2c 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -220,7 +220,7 @@ static int kvm_get_mce_cap_supported(KVMState *s, uint64_t
*mce_cap,
return -ENOSYS;
}
-static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code)
+static void kvm_mce_inject(CPUState *env, Phys paddr, int code)
{
uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
@@ -248,7 +248,7 @@ static void hardware_memory_error(void)
int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
{
ram_addr_t ram_addr;
- target_phys_addr_t paddr;
+ Phys paddr;
if ((env->mcg_cap & MCG_SER_P) && addr
&& (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
@@ -281,7 +281,7 @@ int kvm_arch_on_sigbus(int code, void *addr)
{
if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
ram_addr_t ram_addr;
- target_phys_addr_t paddr;
+ Phys paddr;
/* Hope we are lucky for AO MCE */
if (qemu_ram_addr_from_host(addr, &ram_addr) ||
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index c89e4a4..2beaacd 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -5077,7 +5077,7 @@ void helper_svm_check_io(uint32_t port, uint32_t param,
}
#else
-static inline void svm_save_seg(target_phys_addr_t addr,
+static inline void svm_save_seg(Phys addr,
const SegmentCache *sc)
{
stw_phys(addr + offsetof(struct vmcb_seg, selector),
@@ -5090,7 +5090,7 @@ static inline void svm_save_seg(target_phys_addr_t addr,
((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00));
}
-static inline void svm_load_seg(target_phys_addr_t addr, SegmentCache *sc)
+static inline void svm_load_seg(Phys addr, SegmentCache *sc)
{
unsigned int flags;
@@ -5101,7 +5101,7 @@ static inline void svm_load_seg(target_phys_addr_t addr,
SegmentCache *sc)
sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
}
-static inline void svm_load_seg_cache(target_phys_addr_t addr,
+static inline void svm_load_seg_cache(Phys addr,
CPUState *env, int seg_reg)
{
SegmentCache sc1, *sc = &sc1;
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index fc0b444..6ff2374 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -42,7 +42,7 @@ int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong
address, int rw,
return 0;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+Phys cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
return addr & TARGET_PAGE_MASK;
}
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 674c8e6..c7be964 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -356,7 +356,7 @@ int cpu_m68k_handle_mmu_fault (CPUState *env, target_ulong
address, int rw,
/* MMU */
/* TODO: This will need fixing once the MMU is implemented. */
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+Phys cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
return addr;
}
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 1a307e3..69c6641 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -348,7 +348,7 @@ static inline void cpu_get_tb_cpu_state(CPUState *env,
target_ulong *pc,
}
#if !defined(CONFIG_USER_ONLY)
-void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUState *env1, Phys addr,
int is_write, int is_exec, int is_asi, int size);
#endif
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 2cf2802..85a657e 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -260,7 +260,7 @@ void do_interrupt(CPUState *env)
}
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
+Phys cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
target_ulong vaddr, paddr = 0;
struct microblaze_mmu_lookup lu;
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 7433cec..d445b10 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -490,7 +490,7 @@ void helper_mmu_write(uint32_t rn, uint32_t v)
mmu_write(env, rn, v);
}
-void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUState *env1, Phys addr,
int is_write, int is_exec, int is_asi, int size)
{
CPUState *saved_env;
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 71cb4e8..7549d96 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -44,7 +44,7 @@ typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
struct CPUMIPSTLBContext {
uint32_t nb_tlb;
uint32_t tlb_in_use;
- int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t
*physical, int *prot, target_ulong address, int rw, int access_type);
+ int (*map_address) (struct CPUMIPSState *env, Phys *physical, int *prot,
target_ulong address, int rw, int access_type);
void (*helper_tlbwi) (void);
void (*helper_tlbwr) (void);
void (*helper_tlbp) (void);
@@ -484,18 +484,18 @@ struct CPUMIPSState {
};
#if !defined(CONFIG_USER_ONLY)
-int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int
*prot,
+int no_mmu_map_address (CPUMIPSState *env, Phys *physical, int *prot,
target_ulong address, int rw, int access_type);
-int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical,
int *prot,
+int fixed_mmu_map_address (CPUMIPSState *env, Phys *physical, int *prot,
target_ulong address, int rw, int access_type);
-int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int
*prot,
+int r4k_map_address (CPUMIPSState *env, Phys *physical, int *prot,
target_ulong address, int rw, int access_type);
void r4k_helper_tlbwi (void);
void r4k_helper_tlbwr (void);
void r4k_helper_tlbp (void);
void r4k_helper_tlbr (void);
-void cpu_unassigned_access(CPUState *env, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUState *env, Phys addr,
int is_write, int is_exec, int unused, int size);
#endif
@@ -653,7 +653,7 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong
address, int rw,
void do_interrupt (CPUState *env);
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
-target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong
address,
+Phys cpu_mips_translate_address (CPUState *env, target_ulong address,
int rw);
#endif
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 7225616..a0a6ee5 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -36,7 +36,7 @@ enum {
#if !defined(CONFIG_USER_ONLY)
/* no MMU emulation */
-int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
+int no_mmu_map_address (CPUState *env, Phys *physical, int *prot,
target_ulong address, int rw, int access_type)
{
*physical = address;
@@ -45,7 +45,7 @@ int no_mmu_map_address (CPUState *env, target_phys_addr_t
*physical, int *prot,
}
/* fixed mapping MMU emulation */
-int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int
*prot,
+int fixed_mmu_map_address (CPUState *env, Phys *physical, int *prot,
target_ulong address, int rw, int access_type)
{
if (address <= (int32_t)0x7FFFFFFFUL) {
@@ -63,7 +63,7 @@ int fixed_mmu_map_address (CPUState *env, target_phys_addr_t
*physical, int *pro
}
/* MIPS32/MIPS64 R4000-style MMU emulation */
-int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
+int r4k_map_address (CPUState *env, Phys *physical, int *prot,
target_ulong address, int rw, int access_type)
{
uint8_t ASID = env->CP0_EntryHi & 0xFF;
@@ -99,7 +99,7 @@ int r4k_map_address (CPUState *env, target_phys_addr_t
*physical, int *prot,
return TLBRET_NOMATCH;
}
-static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
+static int get_physical_address (CPUState *env, Phys *physical,
int *prot, target_ulong address,
int rw, int access_type)
{
@@ -254,9 +254,9 @@ static void raise_mmu_exception(CPUState *env, target_ulong
address,
}
#if !defined(CONFIG_USER_ONLY)
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+Phys cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
- target_phys_addr_t phys_addr;
+ Phys phys_addr;
int prot;
if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
@@ -269,7 +269,7 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong
address, int rw,
int mmu_idx)
{
#if !defined(CONFIG_USER_ONLY)
- target_phys_addr_t physical;
+ Phys physical;
int prot;
int access_type;
#endif
@@ -308,9 +308,9 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong
address, int rw,
}
#if !defined(CONFIG_USER_ONLY)
-target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong
address, int rw)
+Phys cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
{
- target_phys_addr_t physical;
+ Phys physical;
int prot;
int access_type;
int ret = 0;
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index c51b9cb..c84c7a5 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -324,9 +324,9 @@ void helper_dmultu (target_ulong arg1, target_ulong arg2)
#ifndef CONFIG_USER_ONLY
-static inline target_phys_addr_t do_translate_address(target_ulong address,
int rw)
+static inline Phys do_translate_address(target_ulong address, int rw)
{
- target_phys_addr_t lladdr;
+ Phys lladdr;
lladdr = cpu_mips_translate_address(env, address, rw);
@@ -2343,7 +2343,7 @@ void tlb_fill(CPUState *env1, target_ulong addr, int
is_write, int mmu_idx,
env = saved_env;
}
-void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUState *env1, Phys addr,
int is_write, int is_exec, int unused, int size)
{
env = env1;
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 2d67d1f..99a39d0 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -350,7 +350,7 @@ struct ppc6xx_tlb_t {
typedef struct ppcemb_tlb_t ppcemb_tlb_t;
struct ppcemb_tlb_t {
- target_phys_addr_t RPN;
+ Phys RPN;
target_ulong EPN;
target_ulong PID;
target_ulong size;
@@ -936,8 +936,8 @@ struct CPUPPCState {
int slb_nr;
#endif
/* segment registers */
- target_phys_addr_t htab_base;
- target_phys_addr_t htab_mask;
+ Phys htab_base;
+ Phys htab_mask;
target_ulong sr[32];
/* externally stored hash table */
uint8_t *external_htab;
@@ -995,9 +995,9 @@ struct CPUPPCState {
uint64_t insns_flags2;
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
- target_phys_addr_t vpa;
- target_phys_addr_t slb_shadow;
- target_phys_addr_t dispatch_trace_log;
+ Phys vpa;
+ Phys slb_shadow;
+ Phys dispatch_trace_log;
uint32_t dtl_size;
#endif /* TARGET_PPC64 */
@@ -1067,10 +1067,10 @@ do { \
/* Context used internally during MMU translations */
typedef struct mmu_ctx_t mmu_ctx_t;
struct mmu_ctx_t {
- target_phys_addr_t raddr; /* Real address */
- target_phys_addr_t eaddr; /* Effective address */
+ Phys raddr; /* Real address */
+ Phys eaddr; /* Effective address */
int prot; /* Protection bits */
- target_phys_addr_t hash[2]; /* Pagetable hash values */
+ Phys hash[2]; /* Pagetable hash values */
target_ulong ptem; /* Virtual segment ID | API */
int key; /* Access key */
int nx; /* Non-execute area */
@@ -1155,12 +1155,12 @@ void store_40x_sler (CPUPPCState *env, uint32_t val);
void store_booke_tcr (CPUPPCState *env, target_ulong val);
void store_booke_tsr (CPUPPCState *env, target_ulong val);
void booke206_flush_tlb(CPUState *env, int flags, const int check_iprot);
-target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb);
+Phys booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb);
int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
- target_phys_addr_t *raddrp, target_ulong address,
+ Phys *raddrp, target_ulong address,
uint32_t pid, int ext, int i);
int ppcmas_tlb_check(CPUState *env, ppcmas_tlb_t *tlb,
- target_phys_addr_t *raddrp, target_ulong address,
+ Phys *raddrp, target_ulong address,
uint32_t pid);
void ppc_tlb_invalidate_all (CPUPPCState *env);
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 137a494..141c9c1 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -231,7 +231,7 @@ static inline int _pte_check(mmu_ctx_t *ctx, int is_64b,
target_ulong pte0,
pp = pte1 & 0x00000003;
}
if (ptem == ctx->ptem) {
- if (ctx->raddr != (target_phys_addr_t)-1ULL) {
+ if (ctx->raddr != (Phys)-1ULL) {
/* all matches should have equal RPN, WIMG & PP */
if ((ctx->raddr & mmask) != (pte1 & mmask)) {
qemu_log("Bad RPN/WIMG/PP\n");
@@ -567,8 +567,8 @@ static inline int get_bat(CPUState *env, mmu_ctx_t *ctx,
target_ulong virtual,
return ret;
}
-static inline target_phys_addr_t get_pteg_offset(CPUState *env,
- target_phys_addr_t hash,
+static inline Phys get_pteg_offset(CPUState *env,
+ Phys hash,
int pte_size)
{
return (hash * pte_size * 8) & env->htab_mask;
@@ -578,7 +578,7 @@ static inline target_phys_addr_t get_pteg_offset(CPUState
*env,
static inline int _find_pte(CPUState *env, mmu_ctx_t *ctx, int is_64b, int h,
int rw, int type, int target_page_bits)
{
- target_phys_addr_t pteg_off;
+ Phys pteg_off;
target_ulong pte0, pte1;
int i, good = -1;
int ret, r;
@@ -821,7 +821,7 @@ int ppc_load_slb_vsid (CPUPPCState *env, target_ulong rb,
target_ulong *rt)
static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw, int type)
{
- target_phys_addr_t hash;
+ Phys hash;
target_ulong vsid;
int ds, pr, target_page_bits;
int ret, ret2;
@@ -900,7 +900,7 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
ctx->hash[1] = ~hash;
/* Initialize real address with an invalid value */
- ctx->raddr = (target_phys_addr_t)-1ULL;
+ ctx->raddr = (Phys)-1ULL;
if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
/* Software TLB search */
@@ -928,7 +928,7 @@ static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
}
#if defined (DUMP_PAGE_TABLES)
if (qemu_log_enabled()) {
- target_phys_addr_t curaddr;
+ Phys curaddr;
uint32_t a0, a1, a2, a3;
qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
"\n", sdr, mask + 0x80);
@@ -1009,7 +1009,7 @@ static inline int get_segment(CPUState *env, mmu_ctx_t
*ctx,
/* Generic TLB check function for embedded PowerPC implementations */
int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
- target_phys_addr_t *raddrp,
+ Phys *raddrp,
target_ulong address, uint32_t pid, int ext,
int i)
{
@@ -1033,7 +1033,7 @@ int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
#if (TARGET_PHYS_ADDR_BITS >= 36)
if (ext) {
/* Extend the physical address to 36 bits */
- *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
+ *raddrp |= (Phys)(tlb->RPN & 0xF) << 32;
}
#endif
@@ -1044,7 +1044,7 @@ int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
{
ppcemb_tlb_t *tlb;
- target_phys_addr_t raddr;
+ Phys raddr;
int i, ret;
/* Default return value is no match */
@@ -1078,7 +1078,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUState
*env,
{
#if !defined(FLUSH_ALL_TLBS)
ppcemb_tlb_t *tlb;
- target_phys_addr_t raddr;
+ Phys raddr;
target_ulong page, end;
int i;
@@ -1101,11 +1101,11 @@ static int mmu40x_get_physical_address (CPUState *env,
mmu_ctx_t *ctx,
target_ulong address, int rw, int access_type)
{
ppcemb_tlb_t *tlb;
- target_phys_addr_t raddr;
+ Phys raddr;
int i, ret, zsel, zpr, pr;
ret = -1;
- raddr = (target_phys_addr_t)-1ULL;
+ raddr = (Phys)-1ULL;
pr = msr_pr;
for (i = 0; i < env->nb_tlb; i++) {
tlb = &env->tlb.tlbe[i];
@@ -1169,7 +1169,7 @@ void store_40x_sler (CPUPPCState *env, uint32_t val)
}
static inline int mmubooke_check_tlb (CPUState *env, ppcemb_tlb_t *tlb,
- target_phys_addr_t *raddr, int *prot,
+ Phys *raddr, int *prot,
target_ulong address, int rw,
int access_type, int i)
{
@@ -1243,11 +1243,11 @@ static int mmubooke_get_physical_address (CPUState
*env, mmu_ctx_t *ctx,
int access_type)
{
ppcemb_tlb_t *tlb;
- target_phys_addr_t raddr;
+ Phys raddr;
int i, ret;
ret = -1;
- raddr = (target_phys_addr_t)-1ULL;
+ raddr = (Phys)-1ULL;
for (i = 0; i < env->nb_tlb; i++) {
tlb = &env->tlb.tlbe[i];
ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, rw,
@@ -1291,7 +1291,7 @@ void booke206_flush_tlb(CPUState *env, int flags, const
int check_iprot)
tlb_flush(env, 1);
}
-target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb)
+Phys booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb)
{
uint32_t tlbncfg;
int tlbn = booke206_tlbm_to_tlbn(env, tlb);
@@ -1311,7 +1311,7 @@ target_phys_addr_t booke206_tlb_to_page_size(CPUState
*env, ppcmas_tlb_t *tlb)
/* TLB check function for MAS based SoftTLBs */
int ppcmas_tlb_check(CPUState *env, ppcmas_tlb_t *tlb,
- target_phys_addr_t *raddrp,
+ Phys *raddrp,
target_ulong address, uint32_t pid)
{
target_ulong mask;
@@ -1344,7 +1344,7 @@ int ppcmas_tlb_check(CPUState *env, ppcmas_tlb_t *tlb,
}
static int mmubooke206_check_tlb(CPUState *env, ppcmas_tlb_t *tlb,
- target_phys_addr_t *raddr, int *prot,
+ Phys *raddr, int *prot,
target_ulong address, int rw,
int access_type)
{
@@ -1434,11 +1434,11 @@ static int mmubooke206_get_physical_address(CPUState
*env, mmu_ctx_t *ctx,
int access_type)
{
ppcmas_tlb_t *tlb;
- target_phys_addr_t raddr;
+ Phys raddr;
int i, j, ret;
ret = -1;
- raddr = (target_phys_addr_t)-1ULL;
+ raddr = (Phys)-1ULL;
for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
int ways = booke206_tlb_ways(env, i);
@@ -1487,7 +1487,7 @@ static void mmubooke206_dump_one_tlb(FILE *f,
fprintf_function cpu_fprintf,
entry = &env->tlb.tlbm[offset];
for (i = 0; i < tlbsize; i++, entry++) {
- target_phys_addr_t ea, pa, size;
+ Phys ea, pa, size;
int tsize;
if (!(entry->mas1 & MAS1_VALID)) {
@@ -1697,7 +1697,7 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx,
target_ulong eaddr,
return ret;
}
-target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
+Phys cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
{
mmu_ctx_t ctx;
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 6339c95..4dbd770 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -4307,7 +4307,7 @@ void helper_booke206_tlbsx(target_ulong address)
{
ppcmas_tlb_t *tlb = NULL;
int i, j;
- target_phys_addr_t raddr;
+ Phys raddr;
uint32_t spid, sas;
spid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID_MASK) >> MAS6_SPID_SHIFT;
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index b8893b3..d7deda8 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -313,7 +313,7 @@ void s390_add_running_cpu(CPUState *env);
unsigned s390_del_running_cpu(CPUState *env);
/* from s390-virtio-bus */
-extern const target_phys_addr_t virtio_size;
+extern const Phys virtio_size;
#else
static inline void s390_add_running_cpu(CPUState *env)
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 10cc9dd..a93fdfb 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -449,7 +449,7 @@ int cpu_s390x_handle_mmu_fault (CPUState *env, target_ulong
_vaddr, int rw,
return 0;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong vaddr)
+Phys cpu_get_phys_page_debug(CPUState *env, target_ulong vaddr)
{
target_ulong raddr;
int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -503,7 +503,7 @@ static void do_svc_interrupt(CPUState *env)
{
uint64_t mask, addr;
LowCore *lowcore;
- target_phys_addr_t len = TARGET_PAGE_SIZE;
+ Phys len = TARGET_PAGE_SIZE;
lowcore = cpu_physical_memory_map(env->psa, &len, 1);
@@ -523,7 +523,7 @@ static void do_program_interrupt(CPUState *env)
{
uint64_t mask, addr;
LowCore *lowcore;
- target_phys_addr_t len = TARGET_PAGE_SIZE;
+ Phys len = TARGET_PAGE_SIZE;
int ilc = env->int_pgm_ilc;
switch (ilc) {
@@ -566,7 +566,7 @@ static void do_ext_interrupt(CPUState *env)
{
uint64_t mask, addr;
LowCore *lowcore;
- target_phys_addr_t len = TARGET_PAGE_SIZE;
+ Phys len = TARGET_PAGE_SIZE;
ExtQueue *q;
if (!(env->psw.mask & PSW_MASK_EXT)) {
diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
index b8a1a8a..40e586f 100644
--- a/target-s390x/op_helper.c
+++ b/target-s390x/op_helper.c
@@ -104,8 +104,8 @@ void HELPER(exception)(uint32_t excp)
static void mvc_fast_memset(CPUState *env, uint32_t l, uint64_t dest,
uint8_t byte)
{
- target_phys_addr_t dest_phys;
- target_phys_addr_t len = l;
+ Phys dest_phys;
+ Phys len = l;
void *dest_p;
uint64_t asc = env->psw.mask & PSW_MASK_ASC;
int flags;
@@ -126,9 +126,9 @@ static void mvc_fast_memset(CPUState *env, uint32_t l,
uint64_t dest,
static void mvc_fast_memmove(CPUState *env, uint32_t l, uint64_t dest,
uint64_t src)
{
- target_phys_addr_t dest_phys;
- target_phys_addr_t src_phys;
- target_phys_addr_t len = l;
+ Phys dest_phys;
+ Phys src_phys;
+ Phys len = l;
void *dest_p;
void *src_p;
uint64_t asc = env->psw.mask & PSW_MASK_ASC;
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 7d7fdde..b59cbc7 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -202,20 +202,20 @@ void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
#if !defined(CONFIG_USER_ONLY)
void cpu_sh4_invalidate_tlb(CPUSH4State *s);
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
- target_phys_addr_t addr);
-void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+ Phys addr);
+void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, Phys addr,
uint32_t mem_value);
uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
- target_phys_addr_t addr);
-void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, target_phys_addr_t addr,
+ Phys addr);
+void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, Phys addr,
uint32_t mem_value);
uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
- target_phys_addr_t addr);
-void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+ Phys addr);
+void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, Phys addr,
uint32_t mem_value);
uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
- target_phys_addr_t addr);
-void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t addr,
+ Phys addr);
+void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, Phys addr,
uint32_t mem_value);
#endif
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 006d1a9..046587e 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -503,7 +503,7 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong
address, int rw,
return 0;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
+Phys cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
{
target_ulong physical;
int prot;
@@ -574,7 +574,7 @@ void cpu_load_tlb(CPUSH4State * env)
}
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
- target_phys_addr_t addr)
+ Phys addr)
{
int index = (addr & 0x00000300) >> 8;
tlb_t * entry = &s->itlb[index];
@@ -584,7 +584,7 @@ uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
(entry->asid);
}
-void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, Phys addr,
uint32_t mem_value)
{
uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
@@ -604,7 +604,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s,
target_phys_addr_t addr,
}
uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
- target_phys_addr_t addr)
+ Phys addr)
{
int array = (addr & 0x00800000) >> 23;
int index = (addr & 0x00000300) >> 8;
@@ -626,7 +626,7 @@ uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State *s,
}
}
-void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, Phys addr,
uint32_t mem_value)
{
int array = (addr & 0x00800000) >> 23;
@@ -655,7 +655,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s,
target_phys_addr_t addr,
}
uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
- target_phys_addr_t addr)
+ Phys addr)
{
int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index];
@@ -667,7 +667,7 @@ uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State *s,
(entry->asid);
}
-void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, Phys addr,
uint32_t mem_value)
{
int associate = addr & 0x0000080;
@@ -740,7 +740,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s,
target_phys_addr_t addr,
}
uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
- target_phys_addr_t addr)
+ Phys addr)
{
int array = (addr & 0x00800000) >> 23;
int index = (addr & 0x00003f00) >> 8;
@@ -766,7 +766,7 @@ uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s,
}
}
-void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, target_phys_addr_t addr,
+void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, Phys addr,
uint32_t mem_value)
{
int array = (addr & 0x00800000) >> 23;
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 38a7074..5ee8f68 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -575,10 +575,10 @@ static inline int tlb_compare_context(const SparcTLBEntry
*tlb,
/* cpu-exec.c */
#if !defined(CONFIG_USER_ONLY)
-void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUState *env1, Phys addr,
int is_write, int is_exec, int is_asi, int size);
#if defined(TARGET_SPARC64)
-target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
+Phys cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
int mmu_idx);
#endif
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index b59707e..b22998e 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -70,7 +70,7 @@
#define QT1 (env->qt1)
#if !defined(CONFIG_USER_ONLY)
-static void do_unassigned_access(target_phys_addr_t addr, int is_write,
+static void do_unassigned_access(Phys addr, int is_write,
int is_exec, int is_asi, int size);
#else
#ifdef TARGET_SPARC64
@@ -608,21 +608,21 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int
size, int sign)
case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
switch (size) {
case 1:
- ret = ldub_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32));
+ ret = ldub_phys((Phys)addr
+ | ((Phys)(asi & 0xf) << 32));
break;
case 2:
- ret = lduw_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32));
+ ret = lduw_phys((Phys)addr
+ | ((Phys)(asi & 0xf) << 32));
break;
default:
case 4:
- ret = ldl_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32));
+ ret = ldl_phys((Phys)addr
+ | ((Phys)(asi & 0xf) << 32));
break;
case 8:
- ret = ldq_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32));
+ ret = ldq_phys((Phys)addr
+ | ((Phys)(asi & 0xf) << 32));
break;
}
break;
@@ -992,21 +992,21 @@ void helper_st_asi(target_ulong addr, uint64_t val, int
asi, int size)
{
switch (size) {
case 1:
- stb_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32), val);
+ stb_phys((Phys)addr
+ | ((Phys)(asi & 0xf) << 32), val);
break;
case 2:
- stw_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32), val);
+ stw_phys((Phys)addr
+ | ((Phys)(asi & 0xf) << 32), val);
break;
case 4:
default:
- stl_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32), val);
+ stl_phys((Phys)addr
+ | ((Phys)(asi & 0xf) << 32), val);
break;
case 8:
- stq_phys((target_phys_addr_t)addr
- | ((target_phys_addr_t)(asi & 0xf) << 32), val);
+ stq_phys((Phys)addr
+ | ((Phys)(asi & 0xf) << 32), val);
break;
}
}
@@ -2275,7 +2275,7 @@ void helper_stqf(target_ulong addr, int mem_idx)
#ifndef TARGET_SPARC64
#if !defined(CONFIG_USER_ONLY)
-static void do_unassigned_access(target_phys_addr_t addr, int is_write,
+static void do_unassigned_access(Phys addr, int is_write,
int is_exec, int is_asi, int size)
{
int fault_type;
@@ -2340,7 +2340,7 @@ static void do_unassigned_access(target_phys_addr_t addr,
int is_write,
static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
int is_asi, int size)
#else
-static void do_unassigned_access(target_phys_addr_t addr, int is_write,
+static void do_unassigned_access(Phys addr, int is_write,
int is_exec, int is_asi, int size)
#endif
{
@@ -2358,7 +2358,7 @@ static void do_unassigned_access(target_phys_addr_t addr,
int is_write,
#endif
#if !defined(CONFIG_USER_ONLY)
-void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
+void cpu_unassigned_access(CPUState *env1, Phys addr,
int is_write, int is_exec, int is_asi, int size)
{
CPUState *saved_env;
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index bdff1c3..f59413c 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -76,13 +76,13 @@ int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong
address, int rw,
}
};
-static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
+static int get_physical_address(CPUState *env, Phys *physical,
int *prot, int *access_index,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
{
int access_perms = 0;
- target_phys_addr_t pde_ptr;
+ Phys pde_ptr;
uint32_t pde;
int error_code = 0, is_dirty, is_user;
unsigned long page_offset;
@@ -193,7 +193,7 @@ static int get_physical_address(CPUState *env,
target_phys_addr_t *physical,
/* Even if large ptes, we map only one 4KB page in the cache to
avoid filling it too fast */
- *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
+ *physical = ((Phys)(pde & PTE_ADDR_MASK) << 4) + page_offset;
return error_code;
}
@@ -201,7 +201,7 @@ static int get_physical_address(CPUState *env,
target_phys_addr_t *physical,
int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx)
{
- target_phys_addr_t paddr;
+ Phys paddr;
target_ulong vaddr;
target_ulong page_size;
int error_code = 0, prot, access_index;
@@ -246,11 +246,11 @@ int cpu_sparc_handle_mmu_fault(CPUState *env,
target_ulong address, int rw,
target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
{
- target_phys_addr_t pde_ptr;
+ Phys pde_ptr;
uint32_t pde;
/* Context base + context number */
- pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
+ pde_ptr = (Phys)(env->mmuregs[1] << 4) +
(env->mmuregs[2] << 2);
pde = ldl_phys(pde_ptr);
@@ -314,13 +314,13 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf,
CPUState *env)
{
target_ulong va, va1, va2;
unsigned int n, m, o;
- target_phys_addr_t pde_ptr, pa;
+ Phys pde_ptr, pa;
uint32_t pde;
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
pde = ldl_phys(pde_ptr);
(*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
- (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
+ (Phys)env->mmuregs[1] << 4, env->mmuregs[2]);
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
pde = mmu_probe(env, va, 2);
if (pde) {
@@ -433,7 +433,7 @@ int target_memory_rw_debug(CPUState *env, target_ulong addr,
#else /* !TARGET_SPARC64 */
/* 41 bit physical address space */
-static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x)
+static inline Phys ultrasparc_truncate_physical(uint64_t x)
{
return x & 0x1ffffffffffULL;
}
@@ -447,7 +447,7 @@ static inline target_phys_addr_t
ultrasparc_truncate_physical(uint64_t x)
entry size */
static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
uint64_t address, uint64_t context,
- target_phys_addr_t *physical)
+ Phys *physical)
{
uint64_t mask;
@@ -480,7 +480,7 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
}
static int get_physical_address_data(CPUState *env,
- target_phys_addr_t *physical, int *prot,
+ Phys *physical, int *prot,
target_ulong address, int rw, int mmu_idx)
{
unsigned int i;
@@ -599,7 +599,7 @@ static int get_physical_address_data(CPUState *env,
}
static int get_physical_address_code(CPUState *env,
- target_phys_addr_t *physical, int *prot,
+ Phys *physical, int *prot,
target_ulong address, int mmu_idx)
{
unsigned int i;
@@ -667,7 +667,7 @@ static int get_physical_address_code(CPUState *env,
return 1;
}
-static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
+static int get_physical_address(CPUState *env, Phys *physical,
int *prot, int *access_index,
target_ulong address, int rw, int mmu_idx,
target_ulong *page_size)
@@ -705,7 +705,7 @@ int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong
address, int rw,
int mmu_idx)
{
target_ulong virt_addr, vaddr;
- target_phys_addr_t paddr;
+ Phys paddr;
target_ulong page_size;
int error_code = 0, prot, access_index;
@@ -813,7 +813,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf,
CPUState *env)
#endif /* TARGET_SPARC64 */
-static int cpu_sparc_get_phys_page(CPUState *env, target_phys_addr_t *phys,
+static int cpu_sparc_get_phys_page(CPUState *env, Phys *phys,
target_ulong addr, int rw, int mmu_idx)
{
target_ulong page_size;
@@ -824,10 +824,10 @@ static int cpu_sparc_get_phys_page(CPUState *env,
target_phys_addr_t *phys,
}
#if defined(TARGET_SPARC64)
-target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
+Phys cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
int mmu_idx)
{
- target_phys_addr_t phys_addr;
+ Phys phys_addr;
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 4, mmu_idx) != 0) {
return -1;
@@ -836,9 +836,9 @@ target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env,
target_ulong addr,
}
#endif
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+Phys cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
- target_phys_addr_t phys_addr;
+ Phys phys_addr;
int mmu_idx = cpu_mmu_index(env);
MemoryRegionSection section;
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index 2a0cb1a..cf9c840 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -98,7 +98,7 @@ void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
}
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+Phys cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
uint32_t paddr;
uint32_t page_size;
diff --git a/targphys.h b/targphys.h
index 95648d6..4de9a10 100644
--- a/targphys.h
+++ b/targphys.h
@@ -1,18 +1,18 @@
-/* Define target_phys_addr_t if it exists. */
+/* Define Phys if it exists. */
#ifndef TARGPHYS_H
#define TARGPHYS_H
#ifdef TARGET_PHYS_ADDR_BITS
-/* target_phys_addr_t is the type of a physical address (its size can
+/* Phys is the type of a physical address (its size can
be different from 'target_ulong'). */
#if TARGET_PHYS_ADDR_BITS == 32
-typedef uint32_t target_phys_addr_t;
+typedef uint32_t Phys;
#define TARGET_PHYS_ADDR_MAX UINT32_MAX
#define TARGET_FMT_plx "%08x"
#elif TARGET_PHYS_ADDR_BITS == 64
-typedef uint64_t target_phys_addr_t;
+typedef uint64_t Phys;
#define TARGET_PHYS_ADDR_MAX UINT64_MAX
#define TARGET_FMT_plx "%016" PRIx64
#endif
diff --git a/xen-all.c b/xen-all.c
index d58d461..6da752b 100644
--- a/xen-all.c
+++ b/xen-all.c
@@ -61,10 +61,10 @@ static inline uint32_t xen_vcpu_eport(shared_iopage_t
*shared_page, int i)
#define BUFFER_IO_MAX_DELAY 100
typedef struct XenPhysmap {
- target_phys_addr_t start_addr;
+ Phys start_addr;
ram_addr_t size;
MemoryRegion *mr;
- target_phys_addr_t phys_offset;
+ Phys phys_offset;
QLIST_ENTRY(XenPhysmap) list;
} XenPhysmap;
@@ -83,7 +83,7 @@ static inline uint32_t xen_vcpu_eport(shared_iopage_t
*shared_page, int i)
struct xs_handle *xenstore;
MemoryListener memory_listener;
QLIST_HEAD(, XenPhysmap) physmap;
- target_phys_addr_t free_phys_offset;
+ Phys free_phys_offset;
const XenPhysmap *log_for_dirtybit;
Notifier exit;
@@ -211,7 +211,7 @@ void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size,
MemoryRegion *mr)
}
static XenPhysmap *get_physmapping(XenIOState *state,
- target_phys_addr_t start_addr, ram_addr_t
size)
+ Phys start_addr, ram_addr_t size)
{
XenPhysmap *physmap = NULL;
@@ -227,16 +227,16 @@ void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size,
MemoryRegion *mr)
#if CONFIG_XEN_CTRL_INTERFACE_VERSION >= 340
static int xen_add_to_physmap(XenIOState *state,
- target_phys_addr_t start_addr,
+ Phys start_addr,
ram_addr_t size,
MemoryRegion *mr,
- target_phys_addr_t offset_within_region)
+ Phys offset_within_region)
{
unsigned long i = 0;
int rc = 0;
XenPhysmap *physmap = NULL;
- target_phys_addr_t pfn, start_gpfn;
- target_phys_addr_t phys_offset = memory_region_get_ram_addr(mr);
+ Phys pfn, start_gpfn;
+ Phys phys_offset = memory_region_get_ram_addr(mr);
if (get_physmapping(state, start_addr, size)) {
return 0;
@@ -287,13 +287,13 @@ static int xen_add_to_physmap(XenIOState *state,
}
static int xen_remove_from_physmap(XenIOState *state,
- target_phys_addr_t start_addr,
+ Phys start_addr,
ram_addr_t size)
{
unsigned long i = 0;
int rc = 0;
XenPhysmap *physmap = NULL;
- target_phys_addr_t phys_offset = 0;
+ Phys phys_offset = 0;
physmap = get_physmapping(state, start_addr, size);
if (physmap == NULL) {
@@ -332,16 +332,16 @@ static int xen_remove_from_physmap(XenIOState *state,
#else
static int xen_add_to_physmap(XenIOState *state,
- target_phys_addr_t start_addr,
+ Phys start_addr,
ram_addr_t size,
MemoryRegion *mr,
- target_phys_addr_t offset_within_region)
+ Phys offset_within_region)
{
return -ENOSYS;
}
static int xen_remove_from_physmap(XenIOState *state,
- target_phys_addr_t start_addr,
+ Phys start_addr,
ram_addr_t size)
{
return -ENOSYS;
@@ -353,7 +353,7 @@ static void xen_set_memory(struct MemoryListener *listener,
bool add)
{
XenIOState *state = container_of(listener, XenIOState, memory_listener);
- target_phys_addr_t start_addr = section->offset_within_address_space;
+ Phys start_addr = section->offset_within_address_space;
ram_addr_t size = section->size;
bool log_dirty = memory_region_is_logging(section->mr);
hvmmem_type_t mem_type;
@@ -405,10 +405,10 @@ static void xen_region_del(MemoryListener *listener,
}
static int xen_sync_dirty_bitmap(XenIOState *state,
- target_phys_addr_t start_addr,
+ Phys start_addr,
ram_addr_t size)
{
- target_phys_addr_t npages = size >> TARGET_PAGE_BITS;
+ Phys npages = size >> TARGET_PAGE_BITS;
const int width = sizeof(unsigned long) * 8;
unsigned long bitmap[(npages + width - 1) / width];
int rc, i, j;
diff --git a/xen-mapcache.c b/xen-mapcache.c
index 9fecc64..3090a68 100644
--- a/xen-mapcache.c
+++ b/xen-mapcache.c
@@ -51,18 +51,18 @@
#define mapcache_unlock() ((void)0)
typedef struct MapCacheEntry {
- target_phys_addr_t paddr_index;
+ Phys paddr_index;
uint8_t *vaddr_base;
unsigned long *valid_mapping;
uint8_t lock;
- target_phys_addr_t size;
+ Phys size;
struct MapCacheEntry *next;
} MapCacheEntry;
typedef struct MapCacheRev {
uint8_t *vaddr_req;
- target_phys_addr_t paddr_index;
- target_phys_addr_t size;
+ Phys paddr_index;
+ Phys size;
QTAILQ_ENTRY(MapCacheRev) next;
} MapCacheRev;
@@ -72,7 +72,7 @@
QTAILQ_HEAD(map_cache_head, MapCacheRev) locked_entries;
/* For most cases (>99.9%), the page address is the same. */
- target_phys_addr_t last_address_index;
+ Phys last_address_index;
uint8_t *last_address_vaddr;
unsigned long max_mcache_size;
unsigned int mcache_bucket_shift;
@@ -134,14 +134,14 @@ void xen_map_cache_init(void)
}
static void xen_remap_bucket(MapCacheEntry *entry,
- target_phys_addr_t size,
- target_phys_addr_t address_index)
+ Phys size,
+ Phys address_index)
{
uint8_t *vaddr_base;
xen_pfn_t *pfns;
int *err;
unsigned int i;
- target_phys_addr_t nb_pfn = size >> XC_PAGE_SHIFT;
+ Phys nb_pfn = size >> XC_PAGE_SHIFT;
trace_xen_remap_bucket(address_index);
@@ -187,13 +187,13 @@ static void xen_remap_bucket(MapCacheEntry *entry,
g_free(err);
}
-uint8_t *xen_map_cache(target_phys_addr_t phys_addr, target_phys_addr_t size,
+uint8_t *xen_map_cache(Phys phys_addr, Phys size,
uint8_t lock)
{
MapCacheEntry *entry, *pentry = NULL;
- target_phys_addr_t address_index = phys_addr >> MCACHE_BUCKET_SHIFT;
- target_phys_addr_t address_offset = phys_addr & (MCACHE_BUCKET_SIZE - 1);
- target_phys_addr_t __size = size;
+ Phys address_index = phys_addr >> MCACHE_BUCKET_SHIFT;
+ Phys address_offset = phys_addr & (MCACHE_BUCKET_SIZE - 1);
+ Phys __size = size;
trace_xen_map_cache(phys_addr);
@@ -258,8 +258,8 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr)
{
MapCacheEntry *entry = NULL;
MapCacheRev *reventry;
- target_phys_addr_t paddr_index;
- target_phys_addr_t size;
+ Phys paddr_index;
+ Phys size;
int found = 0;
QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) {
@@ -296,8 +296,8 @@ void xen_invalidate_map_cache_entry(uint8_t *buffer)
{
MapCacheEntry *entry = NULL, *pentry = NULL;
MapCacheRev *reventry;
- target_phys_addr_t paddr_index;
- target_phys_addr_t size;
+ Phys paddr_index;
+ Phys size;
int found = 0;
if (mapcache->last_address_vaddr == buffer) {
diff --git a/xen-mapcache.h b/xen-mapcache.h
index da874ca..9971b9b 100644
--- a/xen-mapcache.h
+++ b/xen-mapcache.h
@@ -14,7 +14,7 @@
#ifdef CONFIG_XEN
void xen_map_cache_init(void);
-uint8_t *xen_map_cache(target_phys_addr_t phys_addr, target_phys_addr_t size,
+uint8_t *xen_map_cache(Phys phys_addr, Phys size,
uint8_t lock);
ram_addr_t xen_ram_addr_from_mapcache(void *ptr);
void xen_invalidate_map_cache_entry(uint8_t *buffer);
@@ -26,8 +26,8 @@ static inline void xen_map_cache_init(void)
{
}
-static inline uint8_t *xen_map_cache(target_phys_addr_t phys_addr,
- target_phys_addr_t size,
+static inline uint8_t *xen_map_cache(Phys phys_addr,
+ Phys size,
uint8_t lock)
{
abort();
diff --git a/xtensa-semi.c b/xtensa-semi.c
index ba0e828..d40bad1 100644
--- a/xtensa-semi.c
+++ b/xtensa-semi.c
@@ -74,12 +74,12 @@ void HELPER(simcall)(CPUState *env)
uint32_t len = regs[5];
while (len > 0) {
- target_phys_addr_t paddr =
+ Phys paddr =
cpu_get_phys_page_debug(env, vaddr);
uint32_t page_left =
TARGET_PAGE_SIZE - (vaddr & (TARGET_PAGE_SIZE - 1));
uint32_t io_sz = page_left < len ? page_left : len;
- target_phys_addr_t sz = io_sz;
+ Phys sz = io_sz;
void *buf = cpu_physical_memory_map(paddr, &sz, is_write);
if (buf) {
@@ -200,7 +200,7 @@ void HELPER(simcall)(CPUState *env)
uint32_t sz = regs[5];
while (sz) {
- target_phys_addr_t len = sz;
+ Phys len = sz;
void *buf = cpu_physical_memory_map(base, &len, 1);
if (buf && len) {
--
1.7.7.1