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[Qemu-devel] [PATCH v11 4/6] arm: add secondary cpu book callbacks to ar
From: |
Mark Langsdorf |
Subject: |
[Qemu-devel] [PATCH v11 4/6] arm: add secondary cpu book callbacks to arm_boot.c |
Date: |
Thu, 19 Jan 2012 09:43:42 -0600 |
Create two functions, write_secondary_boot() and secondary_cpu_reset_hook(),
to allow platforms more control of how secondary CPUs are brought up. The
new functions default to NULL and aren't called unless they are populated
so there are no changes to existing platform models.
Signed-off-by: Mark Langsdorf <address@hidden>
---
Changes from v2-v10
Skipped
Changes from v1
Added default versions of the functions
Created checks so that NULL function entries became default versions
Simplified calls to the secondary boot functions
Added comments on the use of these functions
hw/arm-misc.h | 15 +++++++++++++++
hw/arm_boot.c | 38 +++++++++++++++++++++++++++++---------
2 files changed, 44 insertions(+), 9 deletions(-)
diff --git a/hw/arm-misc.h b/hw/arm-misc.h
index 6e8ae6b..9138eab 100644
--- a/hw/arm-misc.h
+++ b/hw/arm-misc.h
@@ -30,12 +30,27 @@ struct arm_boot_info {
const char *kernel_cmdline;
const char *initrd_filename;
target_phys_addr_t loader_start;
+ /* multicore boards that use the default secondary core boot functions
+ * need to put the address of the secondary boot code, the boot reg,
+ * and the GIC address in the next 3 values, respectively. boards that
+ * have their own boot functions can use these values as they want.
+ */
target_phys_addr_t smp_loader_start;
target_phys_addr_t smp_bootreg_addr;
target_phys_addr_t smp_priv_base;
int nb_cpus;
int board_id;
int (*atag_board)(const struct arm_boot_info *info, void *p);
+ /* multicore boards that use the default secondary core boot functions
+ * can ignore these two function calls. If the default functions won't
+ * work, then write_secondary_boot() should mimic the board's boot
+ * loader code, and secondary_cpu_reset_hook() should operate handle any
+ * polling response and reset functions.
+ */
+ void (*write_secondary_boot)(CPUState *env,
+ const struct arm_boot_info *info);
+ void (*secondary_cpu_reset_hook)(CPUState *env,
+ const struct arm_boot_info *info);
/* Used internally by arm_boot.c */
int is_linux;
target_phys_addr_t initrd_size;
diff --git a/hw/arm_boot.c b/hw/arm_boot.c
index bf509a8..8f73a29 100644
--- a/hw/arm_boot.c
+++ b/hw/arm_boot.c
@@ -197,13 +197,32 @@ static void do_cpu_reset(void *opaque)
info->loader_start);
}
} else {
- stl_phys_notdirty(info->smp_bootreg_addr, 0);
- env->regs[15] = info->smp_loader_start;
+ info->secondary_cpu_reset_hook(env, info);
}
}
}
}
+static void default_write_secondary(CPUState *env,
+ const struct arm_boot_info *info)
+{
+ int n;
+ smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
+ smpboot[ARRAY_SIZE(smpboot) - 2] = info->smp_priv_base;
+ for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
+ smpboot[n] = tswap32(smpboot[n]);
+ }
+ rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
+ info->smp_loader_start);
+}
+
+static void default_reset_secondary(CPUState *env,
+ const struct arm_boot_info *info)
+{
+ stl_phys_notdirty(info->smp_bootreg_addr, 0);
+ env->regs[15] = info->smp_loader_start;
+}
+
void arm_load_kernel(CPUState *env, struct arm_boot_info *info)
{
int kernel_size;
@@ -220,6 +239,13 @@ void arm_load_kernel(CPUState *env, struct arm_boot_info
*info)
exit(1);
}
+ if (!info->secondary_cpu_reset_hook) {
+ info->secondary_cpu_reset_hook = default_reset_secondary;
+ }
+ if (!info->write_secondary_boot) {
+ info->write_secondary_boot = default_write_secondary;
+ }
+
if (info->nb_cpus == 0)
info->nb_cpus = 1;
@@ -273,13 +299,7 @@ void arm_load_kernel(CPUState *env, struct arm_boot_info
*info)
rom_add_blob_fixed("bootloader", bootloader, sizeof(bootloader),
info->loader_start);
if (info->nb_cpus > 1) {
- smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr;
- smpboot[ARRAY_SIZE(smpboot) - 2] = info->smp_priv_base;
- for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
- smpboot[n] = tswap32(smpboot[n]);
- }
- rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
- info->smp_loader_start);
+ info->write_secondary_boot(env, info);
}
info->initrd_size = initrd_size;
}
--
1.7.5.4
- Re: [Qemu-devel] [PATCH v11 5/6] arm: SoC model for Calxeda Highbank, (continued)
- Re: [Qemu-devel] [PATCH v11 5/6] arm: SoC model for Calxeda Highbank, Mark Langsdorf, 2012/01/19
- Re: [Qemu-devel] [PATCH v11 5/6] arm: SoC model for Calxeda Highbank, Peter Maydell, 2012/01/19
- Re: [Qemu-devel] [PATCH v11 5/6] arm: SoC model for Calxeda Highbank, Mark Langsdorf, 2012/01/19
- Re: [Qemu-devel] [PATCH v11 5/6] arm: SoC model for Calxeda Highbank, Peter Maydell, 2012/01/19
- Re: [Qemu-devel] [PATCH v11 5/6] arm: SoC model for Calxeda Highbank, Mark Langsdorf, 2012/01/19
- Re: [Qemu-devel] [PATCH v11 5/6] arm: SoC model for Calxeda Highbank, Peter Maydell, 2012/01/19
- Re: [Qemu-devel] [PATCH v11 5/6] arm: SoC model for Calxeda Highbank, Mark Langsdorf, 2012/01/19
- Re: [Qemu-devel] [PATCH v11 5/6] arm: SoC model for Calxeda Highbank, Peter Maydell, 2012/01/19
- [Qemu-devel] [PATCH v11 3/6] ahci: add support for non-PCI based controllers, Mark Langsdorf, 2012/01/19
- [Qemu-devel] [PATCH v11 1/6] Add xgmac ethernet model, Mark Langsdorf, 2012/01/19
- [Qemu-devel] [PATCH v11 4/6] arm: add secondary cpu book callbacks to arm_boot.c,
Mark Langsdorf <=
- Re: [Qemu-devel] [PATCH v11 4/6] arm: add secondary cpu book callbacks to arm_boot.c, Peter Maydell, 2012/01/19
[Qemu-devel] [PATCH v12 0/5] arm: add support for Calxeda Highbank, Mark Langsdorf, 2012/01/19
- [Qemu-devel] [PATCH v12 2/4] ahci: add support for non-PCI based controllers, Mark Langsdorf, 2012/01/19
- [Qemu-devel] [PATCH v12 1/4] Add xgmac ethernet model, Mark Langsdorf, 2012/01/19
- [Qemu-devel] [PATCH v12 3/4] arm: add secondary cpu boot callbacks to arm_boot.c, Mark Langsdorf, 2012/01/19
- [Qemu-devel] [PATCH v12 4/4] arm: SoC model for Calxeda Highbank, Mark Langsdorf, 2012/01/19
- Re: [Qemu-devel] [PATCH v12 4/4] arm: SoC model for Calxeda Highbank, Peter Maydell, 2012/01/19
- Re: [Qemu-devel] [PATCH v12 4/4] arm: SoC model for Calxeda Highbank, Rob Herring, 2012/01/19
- Re: [Qemu-devel] [PATCH v12 4/4] arm: SoC model for Calxeda Highbank, John Williams, 2012/01/19
- Re: [Qemu-devel] [PATCH v12 4/4] arm: SoC model for Calxeda Highbank, Peter Maydell, 2012/01/20