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[Qemu-devel] [PATCH RFC 9/7] target-arm: Move CPU feature flags to class
|
From: |
Andreas Färber |
|
Subject: |
[Qemu-devel] [PATCH RFC 9/7] target-arm: Move CPU feature flags to class |
|
Date: |
Mon, 30 Jan 2012 00:50:51 +0100 |
The internal CPU feature flags were only ever set in
cpu_reset_model_id(). Therefore move them into ARMCPUClass.
The feature flags were saved and loaded as part of CPUState. Keep
writing them so that they can still be loaded in older versions, but
ignore when loading.
Since cpu.h defines ARMCPUState, which has been incorporated into
ARMCPU, and tries to use arm_feature() in cpu_get_tb_cpu_state(),
move arm_feature() to cpu-core.h and add a forward declaration.
Signed-off-by: Andreas Färber <address@hidden>
Cc: Peter Maydell <address@hidden>
---
target-arm/cpu-core.c | 135 +++++++++++++++++++++++++++++++++++++++++++++++++
target-arm/cpu-core.h | 9 +++
target-arm/cpu.h | 9 +---
target-arm/helper.c | 95 ----------------------------------
target-arm/machine.c | 6 ++-
5 files changed, 150 insertions(+), 104 deletions(-)
diff --git a/target-arm/cpu-core.c b/target-arm/cpu-core.c
index cdd049e..15b710b 100644
--- a/target-arm/cpu-core.c
+++ b/target-arm/cpu-core.c
@@ -10,6 +10,16 @@
#include "cpu-core.h"
#include "qemu-common.h"
+static inline void set_feature(ARMCPUClass *klass, int feature)
+{
+ klass->features |= 1u << feature;
+}
+
+static inline int has_feature(ARMCPUClass *klass, int feature)
+{
+ return (klass->features & (1u << feature)) != 0;
+}
+
/* CPU models */
static void arm926_class_init(ObjectClass *klass, void *data)
@@ -17,6 +27,8 @@ static void arm926_class_init(ObjectClass *klass, void *data)
ARMCPUClass *k = ARM_CPU_CLASS(klass);
k->id = 0x41069265;
+ set_feature(k, ARM_FEATURE_V5);
+ set_feature(k, ARM_FEATURE_VFP);
}
static void arm946_class_init(ObjectClass *klass, void *data)
@@ -24,6 +36,8 @@ static void arm946_class_init(ObjectClass *klass, void *data)
ARMCPUClass *k = ARM_CPU_CLASS(klass);
k->id = 0x41059461;
+ set_feature(k, ARM_FEATURE_V5);
+ set_feature(k, ARM_FEATURE_MPU);
}
static void arm1026_class_init(ObjectClass *klass, void *data)
@@ -31,6 +45,9 @@ static void arm1026_class_init(ObjectClass *klass, void *data)
ARMCPUClass *k = ARM_CPU_CLASS(klass);
k->id = 0x4106a262;
+ set_feature(k, ARM_FEATURE_V5);
+ set_feature(k, ARM_FEATURE_VFP);
+ set_feature(k, ARM_FEATURE_AUXCR);
}
static void arm1136_r0_class_init(ObjectClass *klass, void *data)
@@ -38,13 +55,18 @@ static void arm1136_r0_class_init(ObjectClass *klass, void
*data)
ARMCPUClass *k = ARM_CPU_CLASS(klass);
k->id = 0x4107b362;
+ set_feature(k, ARM_FEATURE_V6);
+ set_feature(k, ARM_FEATURE_VFP);
}
static void arm1136_r1_class_init(ObjectClass *klass, void *data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ arm1136_r0_class_init(klass, data);
+
k->id = 0x4117b363;
+ set_feature(k, ARM_FEATURE_V6K);
}
static void arm1176_class_init(ObjectClass *klass, void *data)
@@ -52,6 +74,9 @@ static void arm1176_class_init(ObjectClass *klass, void *data)
ARMCPUClass *k = ARM_CPU_CLASS(klass);
k->id = 0x410fb767;
+ set_feature(k, ARM_FEATURE_V6K);
+ set_feature(k, ARM_FEATURE_VFP);
+ set_feature(k, ARM_FEATURE_VAPA);
}
static void arm11mpcore_class_init(ObjectClass *klass, void *data)
@@ -59,6 +84,9 @@ static void arm11mpcore_class_init(ObjectClass *klass, void
*data)
ARMCPUClass *k = ARM_CPU_CLASS(klass);
k->id = 0x410fb022;
+ set_feature(k, ARM_FEATURE_V6K);
+ set_feature(k, ARM_FEATURE_VFP);
+ set_feature(k, ARM_FEATURE_VAPA);
}
static void cortex_m3_class_init(ObjectClass *klass, void *data)
@@ -66,6 +94,8 @@ static void cortex_m3_class_init(ObjectClass *klass, void
*data)
ARMCPUClass *k = ARM_CPU_CLASS(klass);
k->id = 0x410fc231;
+ set_feature(k, ARM_FEATURE_V7);
+ set_feature(k, ARM_FEATURE_M);
}
static void cortex_a8_class_init(ObjectClass *klass, void *data)
@@ -73,6 +103,10 @@ static void cortex_a8_class_init(ObjectClass *klass, void
*data)
ARMCPUClass *k = ARM_CPU_CLASS(klass);
k->id = 0x410fc080;
+ set_feature(k, ARM_FEATURE_V7);
+ set_feature(k, ARM_FEATURE_VFP3);
+ set_feature(k, ARM_FEATURE_NEON);
+ set_feature(k, ARM_FEATURE_THUMB2EE);
}
static void cortex_a9_class_init(ObjectClass *klass, void *data)
@@ -80,6 +114,16 @@ static void cortex_a9_class_init(ObjectClass *klass, void
*data)
ARMCPUClass *k = ARM_CPU_CLASS(klass);
k->id = 0x410fc090;
+ set_feature(k, ARM_FEATURE_V7);
+ set_feature(k, ARM_FEATURE_VFP3);
+ set_feature(k, ARM_FEATURE_VFP_FP16);
+ set_feature(k, ARM_FEATURE_NEON);
+ set_feature(k, ARM_FEATURE_THUMB2EE);
+ /* Note that A9 supports the MP extensions even for
+ * A9UP and single-core A9MP (which are both different
+ * and valid configurations; we don't model A9UP).
+ */
+ set_feature(k, ARM_FEATURE_V7MP);
}
static void cortex_a15_class_init(ObjectClass *klass, void *data)
@@ -87,6 +131,14 @@ static void cortex_a15_class_init(ObjectClass *klass, void
*data)
ARMCPUClass *k = ARM_CPU_CLASS(klass);
k->id = 0x412fc0f1;
+ set_feature(k, ARM_FEATURE_V7);
+ set_feature(k, ARM_FEATURE_VFP4);
+ set_feature(k, ARM_FEATURE_VFP_FP16);
+ set_feature(k, ARM_FEATURE_NEON);
+ set_feature(k, ARM_FEATURE_THUMB2EE);
+ set_feature(k, ARM_FEATURE_ARM_DIV);
+ set_feature(k, ARM_FEATURE_V7MP);
+ set_feature(k, ARM_FEATURE_GENERIC_TIMER);
}
static void ti925t_class_init(ObjectClass *klass, void *data)
@@ -94,12 +146,21 @@ static void ti925t_class_init(ObjectClass *klass, void
*data)
ARMCPUClass *k = ARM_CPU_CLASS(klass);
k->id = 0x54029252;
+ set_feature(k, ARM_FEATURE_V4T);
+ set_feature(k, ARM_FEATURE_OMAPCP);
+}
+
+static void sa11xx_common_class_init(ARMCPUClass *k, void *data)
+{
+ set_feature(k, ARM_FEATURE_STRONGARM);
}
static void sa1100_class_init(ObjectClass *klass, void *data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ sa11xx_common_class_init(k, data);
+
k->id = 0x4401A11B;
}
@@ -107,6 +168,8 @@ static void sa1110_class_init(ObjectClass *klass, void
*data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ sa11xx_common_class_init(k, data);
+
k->id = 0x6901B119;
}
@@ -115,12 +178,16 @@ static void pxa250_class_init(ObjectClass *klass, void
*data)
ARMCPUClass *k = ARM_CPU_CLASS(klass);
k->id = 0x69052100;
+ set_feature(k, ARM_FEATURE_V5);
+ set_feature(k, ARM_FEATURE_XSCALE);
}
static void pxa255_class_init(ObjectClass *klass, void *data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ pxa250_class_init(klass, data);
+
k->id = 0x69052d00;
}
@@ -128,6 +195,8 @@ static void pxa260_class_init(ObjectClass *klass, void
*data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ pxa250_class_init(klass, data);
+
k->id = 0x69052903;
}
@@ -135,6 +204,8 @@ static void pxa261_class_init(ObjectClass *klass, void
*data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ pxa250_class_init(klass, data);
+
k->id = 0x69052d05;
}
@@ -142,13 +213,24 @@ static void pxa262_class_init(ObjectClass *klass, void
*data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ pxa250_class_init(klass, data);
+
k->id = 0x69052d06;
}
+static void pxa270_common_class_init(ARMCPUClass *k, void *data)
+{
+ set_feature(k, ARM_FEATURE_V5);
+ set_feature(k, ARM_FEATURE_XSCALE);
+ set_feature(k, ARM_FEATURE_IWMMXT);
+}
+
static void pxa270_a0_class_init(ObjectClass *klass, void *data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ pxa270_common_class_init(k, data);
+
k->id = 0x69054110;
}
@@ -156,6 +238,8 @@ static void pxa270_a1_class_init(ObjectClass *klass, void
*data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ pxa270_common_class_init(k, data);
+
k->id = 0x69054111;
}
@@ -163,6 +247,8 @@ static void pxa270_b0_class_init(ObjectClass *klass, void
*data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ pxa270_common_class_init(k, data);
+
k->id = 0x69054112;
}
@@ -170,6 +256,8 @@ static void pxa270_b1_class_init(ObjectClass *klass, void
*data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ pxa270_common_class_init(k, data);
+
k->id = 0x69054113;
}
@@ -177,6 +265,8 @@ static void pxa270_c0_class_init(ObjectClass *klass, void
*data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ pxa270_common_class_init(k, data);
+
k->id = 0x69054114;
}
@@ -184,6 +274,8 @@ static void pxa270_c5_class_init(ObjectClass *klass, void
*data)
{
ARMCPUClass *k = ARM_CPU_CLASS(klass);
+ pxa270_common_class_init(k, data);
+
k->id = 0x69054117;
}
@@ -192,6 +284,13 @@ static void arm_any_cpu_class_init(ObjectClass *klass,
void *data)
ARMCPUClass *k = ARM_CPU_CLASS(klass);
k->id = 0xffffffff;
+ set_feature(k, ARM_FEATURE_V7);
+ set_feature(k, ARM_FEATURE_VFP4);
+ set_feature(k, ARM_FEATURE_VFP_FP16);
+ set_feature(k, ARM_FEATURE_NEON);
+ set_feature(k, ARM_FEATURE_THUMB2EE);
+ set_feature(k, ARM_FEATURE_ARM_DIV);
+ set_feature(k, ARM_FEATURE_V7MP);
}
struct ARMCPUDef {
@@ -248,9 +347,45 @@ static void arm_cpu_realize(Object *obj)
static void arm_cpu_class_init(ObjectClass *klass, void *data)
{
+ ARMCPUClass *k = ARM_CPU_CLASS(klass);
const struct ARMCPUDef *d = data;
(*d->class_init)(klass, NULL);
+
+ /* Some features automatically imply others: */
+ if (has_feature(k, ARM_FEATURE_V7)) {
+ set_feature(k, ARM_FEATURE_VAPA);
+ set_feature(k, ARM_FEATURE_THUMB2);
+ if (!has_feature(k, ARM_FEATURE_M)) {
+ set_feature(k, ARM_FEATURE_V6K);
+ } else {
+ set_feature(k, ARM_FEATURE_V6);
+ }
+ }
+ if (has_feature(k, ARM_FEATURE_V6K)) {
+ set_feature(k, ARM_FEATURE_V6);
+ }
+ if (has_feature(k, ARM_FEATURE_V6)) {
+ set_feature(k, ARM_FEATURE_V5);
+ if (!has_feature(k, ARM_FEATURE_M)) {
+ set_feature(k, ARM_FEATURE_AUXCR);
+ }
+ }
+ if (has_feature(k, ARM_FEATURE_V5)) {
+ set_feature(k, ARM_FEATURE_V4T);
+ }
+ if (has_feature(k, ARM_FEATURE_M)) {
+ set_feature(k, ARM_FEATURE_THUMB_DIV);
+ }
+ if (has_feature(k, ARM_FEATURE_ARM_DIV)) {
+ set_feature(k, ARM_FEATURE_THUMB_DIV);
+ }
+ if (has_feature(k, ARM_FEATURE_VFP4)) {
+ set_feature(k, ARM_FEATURE_VFP3);
+ }
+ if (has_feature(k, ARM_FEATURE_VFP3)) {
+ set_feature(k, ARM_FEATURE_VFP);
+ }
}
static void cpu_register(const struct ARMCPUDef *def)
diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index 08b6b2b..80141a1 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -24,6 +24,9 @@ typedef struct ARMCPUClass {
CPUClass parent_class;
uint32_t id;
+
+ /* Internal CPU feature flags. */
+ uint32_t features;
} ARMCPUClass;
typedef struct ARMCPU {
@@ -36,5 +39,11 @@ typedef struct ARMCPU {
#define ENV_GET_OBJECT(e) \
(Object *)((void *)(e) - offsetof(ARMCPU, env))
+static inline int arm_feature(CPUARMState *env, int feature)
+{
+ ARMCPUClass *k = ARM_CPU_GET_CLASS(ENV_GET_OBJECT(env));
+ return (k->features & (1u << feature)) != 0;
+}
+
#endif
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 0d9b39c..b595e48 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -170,9 +170,6 @@ typedef struct CPUARMState {
uint32_t teecr;
uint32_t teehbr;
- /* Internal CPU feature flags. */
- uint32_t features;
-
/* VFP coprocessor state. */
struct {
float64 regs[32];
@@ -385,10 +382,7 @@ enum arm_features {
ARM_FEATURE_GENERIC_TIMER,
};
-static inline int arm_feature(CPUARMState *env, int feature)
-{
- return (env->features & (1u << feature)) != 0;
-}
+static inline int arm_feature(CPUARMState *env, int feature);
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
@@ -476,6 +470,7 @@ static inline void cpu_clone_regs(CPUState *env,
target_ulong newsp)
#endif
#include "cpu-all.h"
+#include "cpu-core.h"
/* Bit usage in the TB flags field: */
#define ARM_TBFLAG_THUMB_SHIFT 0
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1ffd7ba..535e49d 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -52,47 +52,32 @@ static uint32_t arm1176_cp15_c0_c1[8] =
static uint32_t arm1176_cp15_c0_c2[8] =
{ 0x0140011, 0x12002111, 0x11231121, 0x01102131, 0x01141, 0, 0, 0 };
-static inline void set_feature(CPUARMState *env, int feature)
-{
- env->features |= 1u << feature;
-}
-
static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
{
env->cp15.c0_cpuid = id;
switch (id) {
case ARM_CPUID_ARM926:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_VFP);
env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM946:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_MPU);
env->cp15.c0_cachetype = 0x0f004006;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_VFP);
- set_feature(env, ARM_FEATURE_AUXCR);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
env->cp15.c0_cachetype = 0x1dd20d2;
env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM1136:
/* This is the 1136 r1, which is a v6K core */
- set_feature(env, ARM_FEATURE_V6K);
/* Fall through */
case ARM_CPUID_ARM1136_R2:
/* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
* older core than plain "arm1136". In particular this does not
* have the v6K features.
*/
- set_feature(env, ARM_FEATURE_V6);
- set_feature(env, ARM_FEATURE_VFP);
/* These ID register values are correct for 1136 but may be wrong
* for 1136_r2 (in particular r0p2 does not actually implement most
* of the ID registers).
@@ -106,9 +91,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
- set_feature(env, ARM_FEATURE_V6K);
- set_feature(env, ARM_FEATURE_VFP);
- set_feature(env, ARM_FEATURE_VAPA);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
@@ -118,9 +100,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
- set_feature(env, ARM_FEATURE_V6K);
- set_feature(env, ARM_FEATURE_VFP);
- set_feature(env, ARM_FEATURE_VAPA);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
@@ -129,10 +108,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
env->cp15.c0_cachetype = 0x1dd20d2;
break;
case ARM_CPUID_CORTEXA8:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP3);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
@@ -146,16 +121,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP3);
- set_feature(env, ARM_FEATURE_VFP_FP16);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
- /* Note that A9 supports the MP extensions even for
- * A9UP and single-core A9MP (which are both different
- * and valid configurations; we don't model A9UP).
- */
- set_feature(env, ARM_FEATURE_V7MP);
env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
@@ -168,14 +133,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA15:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP4);
- set_feature(env, ARM_FEATURE_VFP_FP16);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
- set_feature(env, ARM_FEATURE_ARM_DIV);
- set_feature(env, ARM_FEATURE_V7MP);
- set_feature(env, ARM_FEATURE_GENERIC_TIMER);
env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
@@ -189,22 +146,11 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXM3:
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_M);
break;
case ARM_CPUID_ANY: /* For userspace emulation. */
- set_feature(env, ARM_FEATURE_V7);
- set_feature(env, ARM_FEATURE_VFP4);
- set_feature(env, ARM_FEATURE_VFP_FP16);
- set_feature(env, ARM_FEATURE_NEON);
- set_feature(env, ARM_FEATURE_THUMB2EE);
- set_feature(env, ARM_FEATURE_ARM_DIV);
- set_feature(env, ARM_FEATURE_V7MP);
break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
- set_feature(env, ARM_FEATURE_V4T);
- set_feature(env, ARM_FEATURE_OMAPCP);
env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
env->cp15.c0_cachetype = 0x5109149;
env->cp15.c1_sys = 0x00000070;
@@ -216,8 +162,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
case ARM_CPUID_PXA260:
case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_XSCALE);
/* JTAG_ID is ((id << 28) | 0x09265013) */
env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
@@ -228,58 +172,19 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
case ARM_CPUID_PXA270_B1:
case ARM_CPUID_PXA270_C0:
case ARM_CPUID_PXA270_C5:
- set_feature(env, ARM_FEATURE_V5);
- set_feature(env, ARM_FEATURE_XSCALE);
/* JTAG_ID is ((id << 28) | 0x09265013) */
- set_feature(env, ARM_FEATURE_IWMMXT);
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
env->cp15.c0_cachetype = 0xd172172;
env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_SA1100:
case ARM_CPUID_SA1110:
- set_feature(env, ARM_FEATURE_STRONGARM);
env->cp15.c1_sys = 0x00000070;
break;
default:
cpu_abort(env, "Bad CPU ID: %x\n", id);
break;
}
-
- /* Some features automatically imply others: */
- if (arm_feature(env, ARM_FEATURE_V7)) {
- set_feature(env, ARM_FEATURE_VAPA);
- set_feature(env, ARM_FEATURE_THUMB2);
- if (!arm_feature(env, ARM_FEATURE_M)) {
- set_feature(env, ARM_FEATURE_V6K);
- } else {
- set_feature(env, ARM_FEATURE_V6);
- }
- }
- if (arm_feature(env, ARM_FEATURE_V6K)) {
- set_feature(env, ARM_FEATURE_V6);
- }
- if (arm_feature(env, ARM_FEATURE_V6)) {
- set_feature(env, ARM_FEATURE_V5);
- if (!arm_feature(env, ARM_FEATURE_M)) {
- set_feature(env, ARM_FEATURE_AUXCR);
- }
- }
- if (arm_feature(env, ARM_FEATURE_V5)) {
- set_feature(env, ARM_FEATURE_V4T);
- }
- if (arm_feature(env, ARM_FEATURE_M)) {
- set_feature(env, ARM_FEATURE_THUMB_DIV);
- }
- if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
- set_feature(env, ARM_FEATURE_THUMB_DIV);
- }
- if (arm_feature(env, ARM_FEATURE_VFP4)) {
- set_feature(env, ARM_FEATURE_VFP3);
- }
- if (arm_feature(env, ARM_FEATURE_VFP3)) {
- set_feature(env, ARM_FEATURE_VFP);
- }
}
void cpu_reset(CPUARMState *env)
diff --git a/target-arm/machine.c b/target-arm/machine.c
index f66b8df..8d2fbd8 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -61,7 +61,8 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, env->cp15.c15_diagnostic);
qemu_put_be32(f, env->cp15.c15_power_diagnostic);
- qemu_put_be32(f, env->features);
+ /* Write internal CPU feature flags for backward compatibility. */
+ qemu_put_be32(f, ARM_CPU_GET_CLASS(ENV_GET_OBJECT(env))->features);
if (arm_feature(env, ARM_FEATURE_VFP)) {
for (i = 0; i < 16; i++) {
@@ -179,7 +180,8 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
env->cp15.c15_diagnostic = qemu_get_be32(f);
env->cp15.c15_power_diagnostic = qemu_get_be32(f);
- env->features = qemu_get_be32(f);
+ /* Ignore internal CPU feature flags (moved to ARMCPUClass). */
+ qemu_get_be32(f);
if (arm_feature(env, ARM_FEATURE_VFP)) {
for (i = 0; i < 16; i++) {
--
1.7.7
- Re: [Qemu-devel] [PATCH RFC 4/7] qom: Introduce CPU class, (continued)