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[Qemu-devel] [PATCH 6/7] add Westmere as a qemu cpu model (v2)
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PATCH 6/7] add Westmere as a qemu cpu model (v2) |
Date: |
Fri, 17 Feb 2012 14:41:24 -0200 |
Version 1 of this patch was:
Message-Id: <address@hidden
http://marc.info/?l=qemu-devel&m=130704415919346
This version doesn't have the duplicate feature bits on extfeature_edx, though,
as they are being removed from the Intel models (as they are reserved bits on
Intel CPUs).
Version 1 patch description:
This patch adds Westmere as a qemu cpu model. The only
additional guest visible feature of a Westmere relative
to Nehalem is the inclusion of AES instructions. However
as other non-ABI visible modifications exist along with
fabrication changes, the CPUID data of the corresponding
deployed silicon was altered slightly to reflect this.
We've seen isolated cases where apparently unrelated yet
slightly incoherent CPUID data has caused problems, most
notably during guest boot. Providing Westmere as a
model separate fro Nehalem allows us to more easily address
such quirks.
[ehabkost: edited commit message to have a better Subject line]
Signed-off-by: john cooper <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
Changes version 1 -> version 2:
- Remove the duplicate feature bits on extfeature_edx, that are
reserved on Intel CPUs
- Reorder feature flags
- Remove x2apic from the definition because x2apic requires some fixes
that have to be resubmitted
Signed-off-by: Eduardo Habkost <address@hidden>
---
sysconfigs/target/target-x86_64.conf | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/sysconfigs/target/target-x86_64.conf
b/sysconfigs/target/target-x86_64.conf
index 96e32e0..dc1a3ea 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -43,6 +43,20 @@
model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
[cpudef]
+ name = "Westmere"
+ level = "11"
+ vendor = "GenuineIntel"
+ family = "6"
+ model = "44"
+ stepping = "1"
+ feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep
apic cx8 mce pae msr tsc pse de fpu"
+ feature_ecx = "aes popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
+ extfeature_edx = "i64 syscall xd"
+ extfeature_ecx = "lahf_lm"
+ xlevel = "0x8000000A"
+ model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)"
+
+[cpudef]
name = "Opteron_G1"
level = "5"
vendor = "AuthenticAMD"
--
1.7.3.2
- [Qemu-devel] [PATCH 0/7] cpu model bug fixes and definition corrections (v3), Eduardo Habkost, 2012/02/17
- [Qemu-devel] [PATCH 6/7] add Westmere as a qemu cpu model (v2),
Eduardo Habkost <=
- [Qemu-devel] [PATCH 7/7] cpu defs: uncomment empty extfeatures_ecx definition for Opteron_G1 (v2), Eduardo Habkost, 2012/02/17
- [Qemu-devel] [PATCH 3/7] cpu defs: use Intel flag names for Intel models (v2), Eduardo Habkost, 2012/02/17
- [Qemu-devel] [PATCH 4/7] cpu defs: add pse36, mca, mtrr to AMD CPU definitions (v2), Eduardo Habkost, 2012/02/17
- [Qemu-devel] [PATCH 2/7] cpu flags: aliases: pclmuldq|pclmulqdq and ffxsr|fxsr_opt, Eduardo Habkost, 2012/02/17
- [Qemu-devel] [PATCH 1/7] cpu models: reorder flag list to match bit order, Eduardo Habkost, 2012/02/17
- [Qemu-devel] [PATCH 5/7] cpu defs: remove replicated flags from Intel (v2), Eduardo Habkost, 2012/02/17
- Re: [Qemu-devel] [PATCH 0/7] cpu model bug fixes and definition corrections (v3), Anthony Liguori, 2012/02/24