Re: [Qemu-devel] [PATCH v1 1/1] mips: properly compute hflags and fcr0 on cpu reset

[Meador Inge]

On 03/03/2012 10:45 AM, Andreas Färber wrote:

> Am 02.03.2012 22:03, schrieb Meador Inge:
>> Currently 'cpu_reset' doesn't fully compute all of the needed
>> HFLAGs and fails to setup fcr0 after clearing the CPU state.
>> This can cause instruction exceptions.  For example, using
>> 'madd.d' on machines that should support it is kindly greeted
>> with:
>>
>> qemu: uncaught target signal 4 (Illegal instruction) - core dumped
>> Illegal instruction (core dumped)
>>
>> because fcr0 is bogus and MIPS_HFLAG_COP1X is not correcly set in hflags.
>>
>> This is fixed by modifying 'cpu_reset' to use 'compute_hflags' and
>> initializing 'fcr0' from the current CPU model.
> 
> fcr0 issue has also been
> 
> Reported-by: Khansa Butt <address@hidden>
> 
> e.g., http://patchwork.ozlabs.org/patch/133974/

Ah, thanks.  The fcr0 fix had been sitting in our local tree for a while and I
just forgot to check upstream patch submissions.  I need to get in the habit of
looking at patchwork first.

> Your use of compute_hflags() looks more future-proof.
> 
>>
>> Signed-off-by: Maciej W. Rozycki <address@hidden>
>> Signed-off-by: Nathan Froyd <address@hidden>
>> Signed-off-by: Meador Inge <address@hidden>
>> ---
>>  target-mips/cpu.h       |   49 
>> +++++++++++++++++++++++++++++++++++++++++++++++
>>  target-mips/op_helper.c |   49 
>> -----------------------------------------------
>>  target-mips/translate.c |   17 +++------------
>>  3 files changed, 53 insertions(+), 62 deletions(-)
>>
>> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
>> index 71cb4e8..fc65348 100644
>> --- a/target-mips/cpu.h
>> +++ b/target-mips/cpu.h
>> @@ -737,4 +737,53 @@ static inline void cpu_pc_from_tb(CPUState *env, 
>> TranslationBlock *tb)
>>      env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
>>  }
>>  
>> +static inline void compute_hflags(CPUState *env)
>> +{
> 
> Moving helper functions like these to cpu.h has proven troublesome for
> QOM'ification (when they need access to MIPSCPU[Class] in addition to
> CPUMIPSState) but it'll do for now.

Okay, I will keep that in mind for the future.  Thanks for the review.

> Reviewed-by: Andreas Färber <address@hidden>
> 
> Andreas
> 


-- 
Meador Inge
CodeSourcery / Mentor Embedded
http://www.mentor.com/embedded-software