[Qemu-devel] [PATCH 2/6] acpi_piix4: Only allow writes to PCI hotplug eject register

[Alex Williamson]

This is never read.  We can also derive bus from the write handler,
which later makes this easier to call directly.  Note that pciej_write
was actually called with (PCIBus *)dev->bus, which is cast as a void*
allowing us to pretend it's a BusState*.  Fix this so we don't depend
on the BusState location within PCIBus.

Signed-off-by: Alex Williamson <address@hidden>
---

 hw/acpi_piix4.c |   13 ++++---------
 1 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index 5960b7f..4d88e23 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -489,15 +489,11 @@ static uint32_t pci_updown_read(void *opaque, uint32_t 
addr)
     return val;
 }
 
-static uint32_t pciej_read(void *opaque, uint32_t addr)
-{
-    PIIX4_DPRINTF("pciej read %x\n", addr);
-    return 0;
-}
-
 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 {
-    BusState *bus = opaque;
+    PIIX4PMState *s = opaque;
+    PCIDevice *dev = &s->dev;
+    BusState *bus = qdev_get_parent_bus(&dev->qdev);
     DeviceState *qdev, *next;
     int slot = ffs(val) - 1;
 
@@ -548,8 +544,7 @@ static void piix4_acpi_system_hot_add_init(PCIBus *bus, 
PIIX4PMState *s)
 
     register_ioport_read(PCI_UP_BASE, 8, 4, pci_updown_read, s);
 
-    register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
-    register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
+    register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s);
 
     register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
     register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);