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[Qemu-devel] [PATCH v5 01/43] PPC: 405: Use proper CPU reset
From: |
Andreas Färber |
Subject: |
[Qemu-devel] [PATCH v5 01/43] PPC: 405: Use proper CPU reset |
Date: |
Wed, 14 Mar 2012 22:42:14 +0100 |
From: Alexander Graf <address@hidden>
On ppc405ep there is a register that allows for software to reset the
core, but not the whole system. Implement this reset using a reset
interrupt.
This gets rid of a bunch of #if 0'ed code.
Reported-by: Andreas Färber <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
---
cpu-exec.c | 2 --
hw/ppc.c | 13 ++-----------
hw/ppc405_uc.c | 16 ++--------------
target-ppc/cpu.h | 3 +++
4 files changed, 7 insertions(+), 27 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 2c2d24e..3d28053 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -339,11 +339,9 @@ int cpu_exec(CPUState *env)
}
}
#elif defined(TARGET_PPC)
-#if 0
if ((interrupt_request & CPU_INTERRUPT_RESET)) {
cpu_reset(env);
}
-#endif
if (interrupt_request & CPU_INTERRUPT_HARD) {
ppc_hw_interrupt(env);
if (env->pending_interrupts == 0)
diff --git a/hw/ppc.c b/hw/ppc.c
index 59882e2..a9516f1 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -131,13 +131,7 @@ static void ppc6xx_set_irq (void *opaque, int pin, int
level)
/* Level sensitive - active low */
if (level) {
LOG_IRQ("%s: reset the CPU\n", __func__);
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
- /* XXX: TOFIX */
-#if 0
- cpu_reset(env);
-#else
- qemu_system_reset_request();
-#endif
+ cpu_interrupt(env, CPU_INTERRUPT_RESET);
}
break;
case PPC6xx_INPUT_SRESET:
@@ -214,10 +208,7 @@ static void ppc970_set_irq (void *opaque, int pin, int
level)
case PPC970_INPUT_HRESET:
/* Level sensitive - active low */
if (level) {
-#if 0 // XXX: TOFIX
- LOG_IRQ("%s: reset the CPU\n", __func__);
- cpu_reset(env);
-#endif
+ cpu_interrupt(env, CPU_INTERRUPT_RESET);
}
break;
case PPC970_INPUT_SRESET:
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 98079fa..951b389 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -1769,13 +1769,7 @@ void ppc40x_core_reset (CPUState *env)
target_ulong dbsr;
printf("Reset PowerPC core\n");
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
- /* XXX: TOFIX */
-#if 0
- cpu_reset(env);
-#else
- qemu_system_reset_request();
-#endif
+ cpu_interrupt(env, CPU_INTERRUPT_RESET);
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;
dbsr |= 0x00000100;
@@ -1787,13 +1781,7 @@ void ppc40x_chip_reset (CPUState *env)
target_ulong dbsr;
printf("Reset PowerPC chip\n");
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
- /* XXX: TOFIX */
-#if 0
- cpu_reset(env);
-#else
- qemu_system_reset_request();
-#endif
+ cpu_interrupt(env, CPU_INTERRUPT_RESET);
/* XXX: TODO reset all internal peripherals */
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index fbcf488..ac753f3 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2051,6 +2051,9 @@ enum {
PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
};
+/* CPU should be reset next, restart from scratch afterwards */
+#define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0
+
/*****************************************************************************/
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
--
1.7.7
- [Qemu-devel] [PATCH v5 14/43] target-cris: Don't overuse CPUState, (continued)
- [Qemu-devel] [PATCH v5 14/43] target-cris: Don't overuse CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 16/43] target-lm32: Don't overuse CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 17/43] target-m68k: Don't overuse CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 15/43] target-i386: Don't overuse CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 18/43] target-microblaze: Don't overuse CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 22/43] target-sh4: Don't overuse CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 06/43] target-sparc: Typedef struct CPUSPARCState early, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 20/43] target-ppc: Don't overuse CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 05/43] target-lm32/microblaze: Typedef struct CPU{MB, LM32}State, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 13/43] target-arm: Don't overuse CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 01/43] PPC: 405: Use proper CPU reset,
Andreas Färber <=
- [Qemu-devel] [PATCH v5 24/43] target-unicore32: Don't overuse CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 26/43] arm-semi: Don't use CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 21/43] target-s390x: Don't overuse CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 27/43] m68k-semi: Don't use CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 28/43] xtensa-semi: Don't use CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 29/43] alpha hw/: Don't use CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 07/43] target-unicore32: Rename to CPUUniCore32State, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 33/43] lm32 hw/: Don't use CPUState, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 08/43] hw/mc146818: Drop unneeded #includes, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH v5 25/43] target-xtensa: Don't overuse CPUState, Andreas Färber, 2012/03/14