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[Qemu-devel] [PATCH V4 03/11] Add MIPS DSP Branch instruction Support
From: |
Jia Liu |
Subject: |
[Qemu-devel] [PATCH V4 03/11] Add MIPS DSP Branch instruction Support |
Date: |
Fri, 30 Mar 2012 11:17:04 +0800 |
Add MIPS DSP Branch instruction Support.
Signed-off-by: Jia Liu <address@hidden>
---
target-mips/translate.c | 21 +++++++++++++++++++--
1 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index f869146..8f8daf2 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -331,6 +331,11 @@ enum {
OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
};
+/* MIPS DSP REGIMM opcodes */
+enum {
+ OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM,
+};
+
/* Coprocessor 0 (rs field) */
#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
@@ -2755,6 +2760,12 @@ static void gen_compute_branch (DisasContext *ctx,
uint32_t opc,
}
btgt = ctx->pc + insn_bytes + offset;
break;
+ case OPC_BPOSGE32:
+ t0 = cpu_dspctrl;
+ tcg_gen_andi_i32(t0, t0, 0x3F);
+ bcond_compute = 1;
+ btgt = ctx->pc + insn_bytes + offset;
+ break;
case OPC_J:
case OPC_JAL:
case OPC_JALX:
@@ -2943,6 +2954,10 @@ static void gen_compute_branch (DisasContext *ctx,
uint32_t opc,
tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
goto likely;
+ case OPC_BPOSGE32:
+ tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32);
+ MIPS_DEBUG("bposge32 %s, " TARGET_FMT_lx, t0, btgt);
+ goto not_likely;
case OPC_BLTZALS:
case OPC_BLTZAL:
ctx->hflags |= (opc == OPC_BLTZALS
@@ -11180,8 +11195,6 @@ static void decode_micromips32_opc (CPUMIPSState *env,
DisasContext *ctx,
*is_branch = 1;
break;
case BPOSGE64:
- case BPOSGE32:
- /* MIPS DSP: not implemented */
/* Fall through */
default:
MIPS_INVAL("pool32i");
@@ -12091,6 +12104,10 @@ static void decode_opc (CPUMIPSState *env,
DisasContext *ctx, int *is_branch)
check_insn(env, ctx, ISA_MIPS32R2);
/* Treat as NOP. */
break;
+ case OPC_BPOSGE32: /* MIPS DSP branch */
+ gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2);
+ *is_branch = 1;
+ break;
default: /* Invalid */
MIPS_INVAL("regimm");
generate_exception(ctx, EXCP_RI);
--
1.7.5.4
- [Qemu-devel] [PATCH V4 00/11] Qemu MIPS ASE DSP Sup port, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 01/11] Add MIPS DSP internal functions, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 02/11] Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 03/11] Add MIPS DSP Branch instruction Support,
Jia Liu <=
- [Qemu-devel] [PATCH V4 04/11] Add MIPS DSP Load instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 05/11] Add MIPS DSP Arithmetic instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 06/11] Add MIPS DSP GPR-Based Shift instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 07/11] Add MIPS DSP Multiply instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 08/11] Add MIPS DSP Bit/Manipulation instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 09/11] Add MIPS DSP Compare-Pick instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 10/11] Add MIPS DSP Accumulator and DSPControl Access instructions Support, Jia Liu, 2012/03/29