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[Qemu-devel] [PATCH V4 05/11] Add MIPS DSP Arithmetic instructions Suppo
|
From: |
Jia Liu |
|
Subject: |
[Qemu-devel] [PATCH V4 05/11] Add MIPS DSP Arithmetic instructions Support |
|
Date: |
Fri, 30 Mar 2012 11:17:06 +0800 |
Add MIPS DSP Arithmetic instructions Support.
Signed-off-by: Jia Liu <address@hidden>
---
target-mips/dsp_helper.c | 876 ++++++++++++++++++++++++++++++++++++++++++++++
target-mips/helper.h | 55 +++
target-mips/translate.c | 288 +++++++++++++++-
3 files changed, 1218 insertions(+), 1 deletions(-)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 4137e49..5dbddc1 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -971,3 +971,879 @@ static inline uint8_t mipsdsp_satu8_sub(CPUMIPSState
*env, uint8_t a, uint8_t b)
return result;
}
/*** MIPS DSP internal functions end ***/
+
+#define MIPSDSP_LHI 0xFFFFFFFF00000000ull
+#define MIPSDSP_LLO 0x00000000FFFFFFFFull
+#define MIPSDSP_HI 0xFFFF0000
+#define MIPSDSP_LO 0x0000FFFF
+#define MIPSDSP_Q3 0xFF000000
+#define MIPSDSP_Q2 0x00FF0000
+#define MIPSDSP_Q1 0x0000FF00
+#define MIPSDSP_Q0 0x000000FF
+
+/** DSP Arithmetic Sub-class insns **/
+uint32_t helper_addq_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rsl, rth, rtl, temph, templ;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ temph = mipsdsp_add_i16(env, rsh, rth);
+ templ = mipsdsp_add_i16(env, rsl, rtl);
+ rd = ((unsigned int)temph << 16) | ((unsigned int)templ & 0xFFFF);
+
+ return rd;
+}
+
+uint32_t helper_addq_s_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ int16_t rsh, rsl, rth, rtl, temph, templ;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ temph = mipsdsp_sat_add_i16(env, rsh, rth);
+ templ = mipsdsp_sat_add_i16(env, rsl, rtl);
+ rd = ((uint32_t)temph << 16) | ((uint32_t)templ & 0xFFFF);
+
+ return rd;
+}
+
+uint32_t helper_addq_s_w(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+ rd = mipsdsp_sat_add_i32(env, rs, rt);
+ return rd;
+}
+
+uint32_t helper_addu_qb(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+ uint8_t rs0, rs1, rs2, rs3;
+ uint8_t rt0, rt1, rt2, rt3;
+ uint8_t temp0, temp1, temp2, temp3;
+
+ rs0 = rs & MIPSDSP_Q0;
+ rs1 = (rs & MIPSDSP_Q1) >> 8;
+ rs2 = (rs & MIPSDSP_Q2) >> 16;
+ rs3 = (rs & MIPSDSP_Q3) >> 24;
+
+ rt0 = rt & MIPSDSP_Q0;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+
+ temp0 = mipsdsp_add_u8(env, rs0, rt0);
+ temp1 = mipsdsp_add_u8(env, rs1, rt1);
+ temp2 = mipsdsp_add_u8(env, rs2, rt2);
+ temp3 = mipsdsp_add_u8(env, rs3, rt3);
+
+ rd = (((uint32_t)temp3 << 24) & MIPSDSP_Q3) | \
+ (((uint32_t)temp2 << 16) & MIPSDSP_Q2) | \
+ (((uint32_t)temp1 << 8) & MIPSDSP_Q1) | \
+ ((uint32_t)temp0 & MIPSDSP_Q0);
+
+ return rd;
+}
+
+uint32_t helper_addu_s_qb(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+ uint8_t rs0, rs1, rs2, rs3;
+ uint8_t rt0, rt1, rt2, rt3;
+ uint8_t temp0, temp1, temp2, temp3;
+
+ rs0 = rs & MIPSDSP_Q0;
+ rs1 = (rs & MIPSDSP_Q1) >> 8;
+ rs2 = (rs & MIPSDSP_Q2) >> 16;
+ rs3 = (rs & MIPSDSP_Q3) >> 24;
+
+ rt0 = rt & MIPSDSP_Q0;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+
+ temp0 = mipsdsp_sat_add_u8(env, rs0, rt0);
+ temp1 = mipsdsp_sat_add_u8(env, rs1, rt1);
+ temp2 = mipsdsp_sat_add_u8(env, rs2, rt2);
+ temp3 = mipsdsp_sat_add_u8(env, rs3, rt3);
+
+ rd = (((uint8_t)temp3 << 24) & MIPSDSP_Q3) | \
+ (((uint8_t)temp2 << 16) & MIPSDSP_Q2) | \
+ (((uint8_t)temp1 << 8) & MIPSDSP_Q1) | \
+ ((uint8_t)temp0 & MIPSDSP_Q0);
+
+ return rd;
+}
+
+uint32_t helper_adduh_qb(uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+ uint8_t rs0, rs1, rs2, rs3;
+ uint8_t rt0, rt1, rt2, rt3;
+ uint8_t temp0, temp1, temp2, temp3;
+
+ rs0 = rs & MIPSDSP_Q0;
+ rs1 = (rs & MIPSDSP_Q1) >> 8;
+ rs2 = (rs & MIPSDSP_Q2) >> 16;
+ rs3 = (rs & MIPSDSP_Q3) >> 24;
+
+ rt0 = rt & MIPSDSP_Q0;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+
+ temp0 = mipsdsp_rshift1_add_u8(rs0, rt0);
+ temp1 = mipsdsp_rshift1_add_u8(rs1, rt1);
+ temp2 = mipsdsp_rshift1_add_u8(rs2, rt2);
+ temp3 = mipsdsp_rshift1_add_u8(rs3, rt3);
+
+ rd = (((uint32_t)temp3 << 24) & MIPSDSP_Q3) | \
+ (((uint32_t)temp2 << 16) & MIPSDSP_Q2) | \
+ (((uint32_t)temp1 << 8) & MIPSDSP_Q1) | \
+ ((uint32_t)temp0 & MIPSDSP_Q0);
+
+ return rd;
+}
+
+uint32_t helper_adduh_r_qb(uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+ uint8_t rs0, rs1, rs2, rs3;
+ uint8_t rt0, rt1, rt2, rt3;
+ uint8_t temp0, temp1, temp2, temp3;
+
+ rs0 = rs & MIPSDSP_Q0;
+ rs1 = (rs & MIPSDSP_Q1) >> 8;
+ rs2 = (rs & MIPSDSP_Q2) >> 16;
+ rs3 = (rs & MIPSDSP_Q3) >> 24;
+
+ rt0 = rt & MIPSDSP_Q0;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+
+ temp0 = mipsdsp_rrshift1_add_u8(rs0, rt0);
+ temp1 = mipsdsp_rrshift1_add_u8(rs1, rt1);
+ temp2 = mipsdsp_rrshift1_add_u8(rs2, rt2);
+ temp3 = mipsdsp_rrshift1_add_u8(rs3, rt3);
+
+ rd = (((uint32_t)temp3 << 24) & MIPSDSP_Q3) | \
+ (((uint32_t)temp2 << 16) & MIPSDSP_Q2) | \
+ (((uint32_t)temp1 << 8) & MIPSDSP_Q1) | \
+ ((uint32_t)temp0 & MIPSDSP_Q0);
+
+ return rd;
+}
+
+uint32_t helper_addu_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl, rth, rtl, temph, templ;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ temph = mipsdsp_add_u16(env, rsh, rth);
+ templ = mipsdsp_add_u16(env, rsl, rtl);
+ rd = ((uint32_t)temph << 16) | ((uint32_t)templ & MIPSDSP_LO);
+
+ return rd;
+}
+
+uint32_t helper_addu_s_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl, rth, rtl, temph, templ;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ temph = mipsdsp_sat_add_u16(env, rsh, rth);
+ templ = mipsdsp_sat_add_u16(env, rsl, rtl);
+ rd = ((uint32_t)temph << 16) | ((uint32_t)templ & MIPSDSP_LO);
+
+ return rd;
+}
+
+uint32_t helper_addqh_ph(uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+ int16_t rsh, rsl, rth, rtl, temph, templ;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ temph = mipsdsp_rshift1_add_q16(rsh, rth);
+ templ = mipsdsp_rshift1_add_q16(rsl, rtl);
+ rd = ((uint32_t)temph << 16) | ((uint32_t)templ & MIPSDSP_LO);
+
+ return rd;
+}
+
+uint32_t helper_addqh_r_ph(uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+ int16_t rsh, rsl, rth, rtl, temph, templ;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ temph = mipsdsp_rrshift1_add_q16(rsh, rth);
+ templ = mipsdsp_rrshift1_add_q16(rsl, rtl);
+ rd = ((uint32_t)temph << 16) | ((uint32_t)templ & MIPSDSP_LO);
+
+ return rd;
+}
+
+uint32_t helper_addqh_w(uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+
+ rd = mipsdsp_rshift1_add_q32(rs, rt);
+
+ return rd;
+}
+
+uint32_t helper_addqh_r_w(uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+
+ rd = mipsdsp_rrshift1_add_q32(rs, rt);
+
+ return rd;
+}
+
+uint32_t helper_subq_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl;
+ uint16_t rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = mipsdsp_sub_i16(env, rsh, rth);
+ tempA = mipsdsp_sub_i16(env, rsl, rtl);
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_subq_s_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl;
+ uint16_t rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = mipsdsp_sat16_sub(env, rsh, rth);
+ tempA = mipsdsp_sat16_sub(env, rsl, rtl);
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_subq_s_w(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+
+ rd = mipsdsp_sat32_sub(env, rs, rt);
+
+ return rd;
+}
+
+uint32_t helper_subu_qb(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint8_t rs3, rs2, rs1, rs0;
+ uint8_t rt3, rt2, rt1, rt0;
+ uint8_t tempD, tempC, tempB, tempA;
+ uint32_t rd;
+
+ rs3 = (rs & MIPSDSP_Q3) >> 24;
+ rs2 = (rs & MIPSDSP_Q2) >> 16;
+ rs1 = (rs & MIPSDSP_Q1) >> 8;
+ rs0 = rs & MIPSDSP_Q0;
+
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+
+ tempD = mipsdsp_sub_u8(env, rs3, rt3);
+ tempC = mipsdsp_sub_u8(env, rs2, rt2);
+ tempB = mipsdsp_sub_u8(env, rs1, rt1);
+ tempA = mipsdsp_sub_u8(env, rs0, rt0);
+
+ rd = ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
+ ((uint32_t)tempB << 8) | (uint32_t)tempA;
+ return rd;
+}
+
+uint32_t helper_subu_s_qb(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint8_t rs3, rs2, rs1, rs0;
+ uint8_t rt3, rt2, rt1, rt0;
+ uint8_t tempD, tempC, tempB, tempA;
+ uint32_t rd;
+
+ rs3 = (rs & MIPSDSP_Q3) >> 24;
+ rs2 = (rs & MIPSDSP_Q2) >> 16;
+ rs1 = (rs & MIPSDSP_Q1) >> 8;
+ rs0 = rs & MIPSDSP_Q0;
+
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+
+ tempD = mipsdsp_satu8_sub(env, rs3, rt3);
+ tempC = mipsdsp_satu8_sub(env, rs2, rt2);
+ tempB = mipsdsp_satu8_sub(env, rs1, rt1);
+ tempA = mipsdsp_satu8_sub(env, rs0, rt0);
+
+ rd = ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
+ ((uint32_t)tempB << 8) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_subuh_qb(uint32_t rs, uint32_t rt)
+{
+ uint8_t rs3, rs2, rs1, rs0;
+ uint8_t rt3, rt2, rt1, rt0;
+ uint8_t tempD, tempC, tempB, tempA;
+ uint32_t rd;
+
+ rs3 = (rs & MIPSDSP_Q3) >> 24;
+ rs2 = (rs & MIPSDSP_Q2) >> 16;
+ rs1 = (rs & MIPSDSP_Q1) >> 8;
+ rs0 = rs & MIPSDSP_Q0;
+
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+
+ tempD = ((uint16_t)rs3 - (uint16_t)rt3) >> 1;
+ tempC = ((uint16_t)rs2 - (uint16_t)rt2) >> 1;
+ tempB = ((uint16_t)rs1 - (uint16_t)rt1) >> 1;
+ tempA = ((uint16_t)rs0 - (uint16_t)rt0) >> 1;
+
+ rd = ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
+ ((uint32_t)tempB << 8) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_subuh_r_qb(uint32_t rs, uint32_t rt)
+{
+ uint8_t rs3, rs2, rs1, rs0;
+ uint8_t rt3, rt2, rt1, rt0;
+ uint8_t tempD, tempC, tempB, tempA;
+ uint32_t rd;
+
+ rs3 = (rs & MIPSDSP_Q3) >> 24;
+ rs2 = (rs & MIPSDSP_Q2) >> 16;
+ rs1 = (rs & MIPSDSP_Q1) >> 8;
+ rs0 = rs & MIPSDSP_Q0;
+
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+
+ tempD = ((uint16_t)rs3 - (uint16_t)rt3 + 1) >> 1;
+ tempC = ((uint16_t)rs2 - (uint16_t)rt2 + 1) >> 1;
+ tempB = ((uint16_t)rs1 - (uint16_t)rt1 + 1) >> 1;
+ tempA = ((uint16_t)rs0 - (uint16_t)rt0 + 1) >> 1;
+
+ rd = ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
+ ((uint32_t)tempB << 8) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_subu_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl, rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = mipsdsp_sub_u16_u16(env, rth, rsh);
+ tempA = mipsdsp_sub_u16_u16(env, rtl, rsl);
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+ return rd;
+}
+
+uint32_t helper_subu_s_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl, rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempB = mipsdsp_satu16_sub_u16_u16(env, rth, rsh);
+ tempA = mipsdsp_satu16_sub_u16_u16(env, rtl, rsl);
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_subqh_ph(uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl;
+ uint16_t rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ tempB = mipsdsp_rshift1_sub_q16(rsh, rth);
+ tempA = mipsdsp_rshift1_sub_q16(rsl, rtl);
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_subqh_r_ph(uint32_t rs, uint32_t rt)
+{
+ uint16_t rsh, rsl;
+ uint16_t rth, rtl;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+ tempB = mipsdsp_rrshift1_sub_q16(rsh, rth);
+ tempA = mipsdsp_rrshift1_sub_q16(rsl, rtl);
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_subqh_w(uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+
+ rd = mipsdsp_rshift1_sub_q32(rs, rt);
+
+ return rd;
+}
+
+uint32_t helper_subqh_r_w(uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+
+ rd = mipsdsp_rrshift1_sub_q32(rs, rt);
+
+ return rd;
+}
+
+uint32_t helper_addsc(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+ uint64_t temp, tempRs, tempRt;
+ int32_t flag;
+
+ tempRs = (uint64_t)rs & MIPSDSP_LLO;
+ tempRt = (uint64_t)rt & MIPSDSP_LLO;
+
+ temp = tempRs + tempRt;
+ flag = (temp & 0x0100000000ull) >> 32;
+ set_DSPControl_carryflag(env, flag);
+ rd = temp & MIPSDSP_LLO;
+
+ return rd;
+}
+
+uint32_t helper_addwc(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint32_t rd;
+ int32_t temp32, temp31;
+ int64_t rsL, rtL, tempL;
+
+ rsL = (int32_t)rs;
+ rtL = (int32_t)rt;
+ tempL = rsL + rtL + get_DSPControl_carryflag(env);
+ temp31 = (tempL >> 31) & 0x01;
+ temp32 = (tempL >> 32) & 0x01;
+
+ if (temp31 != temp32) {
+ set_DSPControl_overflow_flag(env, 1, 20);
+ }
+
+ rd = tempL & MIPSDSP_LLO;
+
+ return rd;
+}
+
+uint32_t helper_modsub(uint32_t rs, uint32_t rt)
+{
+ int32_t decr;
+ uint16_t lastindex;
+ uint32_t rd;
+
+ decr = rt & MIPSDSP_Q0;
+ lastindex = (rt >> 8) & MIPSDSP_LO;
+
+ if (rs == 0x00000000) {
+ rd = (uint32_t)lastindex;
+ } else {
+ rd = rs - decr;
+ }
+
+ return rd;
+}
+
+uint32_t helper_raddu_w_qb(uint32_t rs)
+{
+ uint8_t rs3, rs2, rs1, rs0;
+ uint16_t temp;
+ uint32_t rd;
+
+ rs3 = (rs & MIPSDSP_Q3) >> 24;
+ rs2 = (rs & MIPSDSP_Q2) >> 16;
+ rs1 = (rs & MIPSDSP_Q1) >> 8;
+ rs0 = rs & MIPSDSP_Q0;
+
+ temp = (uint16_t)rs3 + (uint16_t)rs2 + (uint16_t)rs1 + (uint16_t)rs0;
+ rd = temp;
+
+ return rd;
+}
+
+uint32_t helper_absq_s_qb(CPUMIPSState *env, uint32_t rt)
+{
+ uint32_t rd;
+ int8_t tempD, tempC, tempB, tempA;
+
+ tempD = (rt & MIPSDSP_Q3) >> 24;
+ tempC = (rt & MIPSDSP_Q2) >> 16;
+ tempB = (rt & MIPSDSP_Q1) >> 8;
+ tempA = rt & MIPSDSP_Q0;
+
+ rd = (((uint32_t)mipsdsp_sat_abs_u8 (env, tempD) << 24) & MIPSDSP_Q3) | \
+ (((uint32_t)mipsdsp_sat_abs_u8 (env, tempC) << 16) & MIPSDSP_Q2) | \
+ (((uint32_t)mipsdsp_sat_abs_u8 (env, tempB) << 8) & MIPSDSP_Q1) | \
+ ((uint32_t)mipsdsp_sat_abs_u8 (env, tempA) & MIPSDSP_Q0);
+
+ return rd;
+}
+
+uint32_t helper_absq_s_ph(CPUMIPSState *env, uint32_t rt)
+{
+ uint32_t rd;
+ int16_t tempA, tempB;
+
+ tempA = (rt & MIPSDSP_HI) >> 16;
+ tempB = rt & MIPSDSP_LO;
+
+ rd = ((uint32_t)mipsdsp_sat_abs_u16 (env, tempA) << 16) | \
+ ((uint32_t)(mipsdsp_sat_abs_u16 (env, tempB)) & 0xFFFF);
+
+ return rd;
+}
+
+uint32_t helper_absq_s_w(CPUMIPSState *env, uint32_t rt)
+{
+ uint32_t rd;
+ int32_t temp;
+
+ temp = rt;
+ rd = mipsdsp_sat_abs_u32(env, temp);
+
+ return rd;
+}
+
+uint32_t helper_precr_qb_ph(uint32_t rs, uint32_t rt)
+{
+ uint8_t rs2, rs0, rt2, rt0;
+ uint32_t rd;
+
+ rs2 = (rs & MIPSDSP_Q2) >> 16;
+ rs0 = rs & MIPSDSP_Q0;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt0 = rt & MIPSDSP_Q0;
+ rd = ((uint32_t)rs2 << 24) | ((uint32_t)rs0 << 16) | \
+ ((uint32_t)rt2 << 8) | (uint32_t)rt0;
+
+ return rd;
+}
+
+uint32_t helper_precrq_qb_ph(uint32_t rs, uint32_t rt)
+{
+ uint8_t tempD, tempC, tempB, tempA;
+ uint32_t rd;
+
+ tempD = (rs & MIPSDSP_Q3) >> 24;
+ tempC = (rs & MIPSDSP_Q1) >> 8;
+ tempB = (rt & MIPSDSP_Q3) >> 24;
+ tempA = (rt & MIPSDSP_Q1) >> 8;
+
+ rd = ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
+ ((uint32_t)tempB << 8) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_precr_sra_ph_w(int sa, uint32_t rs, uint32_t rt)
+{
+ uint16_t tempB, tempA;
+
+ if (sa == 0) {
+ tempB = rt & MIPSDSP_LO;
+ tempA = rs & MIPSDSP_LO;
+ } else {
+ tempB = ((int32_t)rt >> sa) & MIPSDSP_LO;
+ tempA = ((int32_t)rs >> sa) & MIPSDSP_LO;
+ }
+ rt = ((uint32_t)tempB << 16) | ((uint32_t)tempA & MIPSDSP_LO);
+
+ return rt;
+}
+
+uint32_t helper_precr_sra_r_ph_w(int sa, uint32_t rs, uint32_t rt)
+{
+ uint64_t tempB, tempA;
+
+ if (sa == 0) {
+ tempB = (rt & MIPSDSP_LO) << 1;
+ tempA = (rs & MIPSDSP_LO) << 1;
+ } else {
+ tempB = ((int32_t)rt >> (sa - 1)) + 1;
+ tempA = ((int32_t)rs >> (sa - 1)) + 1;
+ }
+ rt = (((tempB >> 1) & MIPSDSP_LO) << 16) | ((tempA >> 1) & MIPSDSP_LO);
+
+ return rt;
+}
+
+uint32_t helper_precrq_ph_w(uint32_t rs, uint32_t rt)
+{
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ tempB = (rs & MIPSDSP_HI) >> 16;
+ tempA = (rt & MIPSDSP_HI) >> 16;
+ rd = ((uint32_t)tempB << 16) | ((uint32_t)tempA & MIPSDSP_LO);
+
+ return rd;
+}
+
+uint32_t helper_precrq_rs_ph_w(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ tempB = mipsdsp_trunc16_sat16_round(env, rs);
+ tempA = mipsdsp_trunc16_sat16_round(env, rt);
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_precrqu_s_qb_ph(CPUMIPSState *env, uint32_t rs, uint32_t rt)
+{
+ uint8_t tempD, tempC, tempB, tempA;
+ uint16_t rsh, rsl, rth, rtl;
+ uint32_t rd;
+
+ rsh = (rs & MIPSDSP_HI) >> 16;
+ rsl = rs & MIPSDSP_LO;
+ rth = (rt & MIPSDSP_HI) >> 16;
+ rtl = rt & MIPSDSP_LO;
+
+ tempD = mipsdsp_sat8_reduce_precision(env, rsh);
+ tempC = mipsdsp_sat8_reduce_precision(env, rsl);
+ tempB = mipsdsp_sat8_reduce_precision(env, rth);
+ tempA = mipsdsp_sat8_reduce_precision(env, rtl);
+
+ rd = ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
+ ((uint32_t)tempB << 8) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_preceq_w_phl(uint32_t rt)
+{
+ uint32_t rd;
+
+ rd = rt & MIPSDSP_HI;
+
+ return rd;
+}
+
+uint32_t helper_preceq_w_phr(uint32_t rt)
+{
+ uint16_t rtl;
+ uint32_t rd;
+
+ rtl = rt & MIPSDSP_LO;
+ rd = rtl << 16;
+
+ return rd;
+}
+
+uint32_t helper_precequ_ph_qbl(uint32_t rt)
+{
+ uint8_t rt3, rt2;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+
+ tempB = (uint16_t)rt3 << 7;
+ tempA = (uint16_t)rt2 << 7;
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_precequ_ph_qbr(uint32_t rt)
+{
+ uint8_t rt1, rt0;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+ tempB = (uint16_t)rt1 << 7;
+ tempA = (uint16_t)rt0 << 7;
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_precequ_ph_qbla(uint32_t rt)
+{
+ uint8_t rt3, rt1;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+
+ tempB = (uint16_t)rt3 << 7;
+ tempA = (uint16_t)rt1 << 7;
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_precequ_ph_qbra(uint32_t rt)
+{
+ uint8_t rt2, rt0;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt0 = rt & MIPSDSP_Q0;
+ tempB = (uint16_t)rt2 << 7;
+ tempA = (uint16_t)rt0 << 7;
+ rd = ((uint32_t)tempB << 16) | (uint32_t)tempA;
+
+ return rd;
+}
+
+uint32_t helper_preceu_ph_qbl(uint32_t rt)
+{
+ uint8_t rt3, rt2;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ tempB = (uint16_t) rt3;
+ tempA = (uint16_t) rt2;
+ rd = ((uint32_t)tempB << 16) | ((uint32_t)tempA & MIPSDSP_LO);
+
+ return rd;
+}
+
+uint32_t helper_preceu_ph_qbr(uint32_t rt)
+{
+ uint8_t rt1, rt0;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ rt0 = rt & MIPSDSP_Q0;
+ tempB = (uint16_t) rt1;
+ tempA = (uint16_t) rt0;
+ rd = ((uint32_t)tempB << 16) | ((uint32_t)tempA & MIPSDSP_LO);
+ return rd;
+}
+
+uint32_t helper_preceu_ph_qbla(uint32_t rt)
+{
+ uint8_t rt3, rt1;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rt3 = (rt & MIPSDSP_Q3) >> 24;
+ rt1 = (rt & MIPSDSP_Q1) >> 8;
+ tempB = (uint16_t) rt3;
+ tempA = (uint16_t) rt1;
+ rd = ((uint32_t)tempB << 16) | ((uint32_t)tempA & MIPSDSP_LO);
+
+ return rd;
+}
+
+uint32_t helper_preceu_ph_qbra(uint32_t rt)
+{
+ uint8_t rt2, rt0;
+ uint16_t tempB, tempA;
+ uint32_t rd;
+
+ rt2 = (rt & MIPSDSP_Q2) >> 16;
+ rt0 = rt & MIPSDSP_Q0;
+ tempB = (uint16_t)rt2;
+ tempA = (uint16_t)rt0;
+ rd = ((uint32_t)tempB << 16) | ((uint32_t)tempA & MIPSDSP_LO);
+ return rd;
+}
+
+#undef MIPSDSP_LHI
+#undef MIPSDSP_LLO
+#undef MIPSDSP_HI
+#undef MIPSDSP_LO
+#undef MIPSDSP_Q0
+#undef MIPSDSP_Q1
+#undef MIPSDSP_Q2
+#undef MIPSDSP_Q3
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 76fb451..2c4b5e7 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -297,4 +297,59 @@ DEF_HELPER_0(rdhwr_ccres, tl)
DEF_HELPER_1(pmon, void, int)
DEF_HELPER_0(wait, void)
+/*** MIPS DSP ***/
+/* DSP Arithmetic Sub-class insns */
+DEF_HELPER_FLAGS_3(addq_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(addq_s_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(addq_s_w, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(addu_qb, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(addu_s_qb, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_2(adduh_qb, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(adduh_r_qb, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_3(addu_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(addu_s_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_2(addqh_ph, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(addqh_r_ph, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(addqh_w, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(addqh_r_w, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_3(subq_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(subq_s_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(subq_s_w, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(subu_qb, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(subu_s_qb, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_2(subuh_qb, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(subuh_r_qb, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_3(subu_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(subu_s_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_2(subqh_ph, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(subqh_r_ph, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(subqh_w, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(subqh_r_w, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_3(addsc, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(addwc, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_2(modsub, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_1(raddu_w_qb, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
+DEF_HELPER_FLAGS_2(absq_s_qb, 0, i32, env, i32)
+DEF_HELPER_FLAGS_2(absq_s_ph, 0, i32, env, i32)
+DEF_HELPER_FLAGS_2(absq_s_w, 0, i32, env, i32)
+DEF_HELPER_FLAGS_2(precr_qb_ph, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_2(precrq_qb_ph, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_3(precr_sra_ph_w, TCG_CALL_CONST | TCG_CALL_PURE,
+ i32, int, i32, i32)
+DEF_HELPER_FLAGS_3(precr_sra_r_ph_w, TCG_CALL_CONST | TCG_CALL_PURE,
+ i32, int, i32, i32)
+DEF_HELPER_FLAGS_2(precrq_ph_w, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32, i32)
+DEF_HELPER_FLAGS_3(precrq_rs_ph_w, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_3(precrqu_s_qb_ph, 0, i32, env, i32, i32)
+DEF_HELPER_FLAGS_1(preceq_w_phl, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
+DEF_HELPER_FLAGS_1(preceq_w_phr, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
+DEF_HELPER_FLAGS_1(precequ_ph_qbl, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
+DEF_HELPER_FLAGS_1(precequ_ph_qbr, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
+DEF_HELPER_FLAGS_1(precequ_ph_qbla, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
+DEF_HELPER_FLAGS_1(precequ_ph_qbra, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
+DEF_HELPER_FLAGS_1(preceu_ph_qbl, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
+DEF_HELPER_FLAGS_1(preceu_ph_qbr, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
+DEF_HELPER_FLAGS_1(preceu_ph_qbla, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
+DEF_HELPER_FLAGS_1(preceu_ph_qbra, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
+
#include "def-helper.h"
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 608f6de..e3fe966 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -315,7 +315,12 @@ enum {
/* MIPS DSP Load */
OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
-
+ /* MIPS DSP Arithmetic */
+ OPC_ADDU_QB_DSP = 0x10 | OPC_SPECIAL3,
+ OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3,
+ /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */
+ /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */
+ OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
};
/* BSHFL opcodes */
@@ -348,6 +353,77 @@ enum {
OPC_LWX = (0x00 << 6) | OPC_LX_DSP,
};
+#define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
+enum {
+ /* MIPS DSP Arithmetic Sub-class */
+ OPC_ADDQ_PH = (0x0A << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDQ_S_PH = (0x0E << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDQ_S_W = (0x16 << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDU_QB = (0x00 << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDU_S_QB = (0x04 << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDU_PH = (0x08 << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDU_S_PH = (0x0C << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBQ_PH = (0x0B << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBQ_S_PH = (0x0F << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBQ_S_W = (0x17 << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBU_QB = (0x01 << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBU_S_QB = (0x05 << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBU_PH = (0x09 << 6) | OPC_ADDU_QB_DSP,
+ OPC_SUBU_S_PH = (0x0D << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDSC = (0x10 << 6) | OPC_ADDU_QB_DSP,
+ OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP,
+ OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP,
+ OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP,
+};
+
+#define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
+#define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
+enum {
+ /* MIPS DSP Arithmetic Sub-class */
+ OPC_ADDUH_QB = (0x00 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_ADDQH_PH = (0x08 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP,
+ OPC_ADDQH_W = (0x10 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_ADDQH_R_W = (0x12 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_SUBUH_QB = (0x01 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_SUBQH_PH = (0x09 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP,
+ OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP,
+ OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP,
+};
+
+#define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
+enum {
+ /* MIPS DSP Arithmetic Sub-class */
+ OPC_ABSQ_S_QB = (0x01 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_ABSQ_S_PH = (0x09 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_ABSQ_S_W = (0x11 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEQ_W_PHL = (0x0C << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEQ_W_PHR = (0x0D << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEQU_PH_QBL = (0x04 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEQU_PH_QBR = (0x05 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEU_PH_QBL = (0x1C << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP,
+ OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP,
+};
+
+#define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
+enum {
+ /* MIPS DSP Arithmetic Sub-class */
+ OPC_PRECR_QB_PH = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PRECRQ_QB_PH = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PRECR_SRA_PH_W = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP,
+ OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP,
+};
+
/* Coprocessor 0 (rs field) */
#define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
@@ -12070,6 +12146,60 @@ static void decode_opc (CPUMIPSState *env,
DisasContext *ctx, int *is_branch)
break;
case OPC_DIV_G_2E ... OPC_DIVU_G_2E:
case OPC_MULT_G_2E ... OPC_MULTU_G_2E:
+ /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
+ * the same mask and op1. */
+ if (op1 == OPC_MULT_G_2E) {
+ int is_mult_g_2e = 0;
+ op2 = MASK_ADDUH_QB(ctx->opcode);
+ switch (op2) {
+ case OPC_ADDUH_QB:
+ gen_helper_adduh_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDUH_R_QB:
+ gen_helper_adduh_r_qb(cpu_gpr[rd],
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDQH_PH:
+ gen_helper_addqh_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDQH_R_PH:
+ gen_helper_addqh_r_ph(cpu_gpr[rd], cpu_gpr[rs],
+ cpu_gpr[rt]);
+ break;
+ case OPC_ADDQH_W:
+ gen_helper_addqh_w(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDQH_R_W:
+ gen_helper_addqh_r_w(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ case OPC_SUBUH_QB:
+ gen_helper_subuh_qb(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBUH_R_QB:
+ gen_helper_subuh_r_qb(cpu_gpr[rd],
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBQH_PH:
+ gen_helper_subqh_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBQH_R_PH:
+ gen_helper_subqh_r_ph(cpu_gpr[rd],
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBQH_W:
+ gen_helper_subqh_w(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBQH_R_W:
+ gen_helper_subqh_r_w(cpu_gpr[rd], cpu_gpr[rs],
cpu_gpr[rt]);
+ break;
+ default:
+ is_mult_g_2e = 1;
+ break;
+ }
+ if (is_mult_g_2e == 0) {
+ break;
+ }
+ }
case OPC_MOD_G_2E ... OPC_MODU_G_2E:
check_insn(env, ctx, INSN_LOONGSON2E);
gen_loongson_integer(ctx, op1, rd, rs, rt);
@@ -12109,6 +12239,162 @@ static void decode_opc (CPUMIPSState *env,
DisasContext *ctx, int *is_branch)
}
}
break;
+ case OPC_ABSQ_S_PH_DSP:
+ op2 = MASK_ABSQ_S_PH(ctx->opcode);
+ switch (op2) {
+ case OPC_ABSQ_S_QB:
+ gen_helper_absq_s_qb(cpu_gpr[rd], cpu_env, cpu_gpr[rt]);
+ break;
+ case OPC_ABSQ_S_PH:
+ gen_helper_absq_s_ph(cpu_gpr[rd], cpu_env, cpu_gpr[rt]);
+ break;
+ case OPC_ABSQ_S_W:
+ gen_helper_absq_s_w(cpu_gpr[rd], cpu_env, cpu_gpr[rt]);
+ break;
+ case OPC_PRECEQ_W_PHL:
+ gen_helper_preceq_w_phl(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEQ_W_PHR:
+ gen_helper_preceq_w_phr(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEQU_PH_QBL:
+ gen_helper_precequ_ph_qbl(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEQU_PH_QBR:
+ gen_helper_precequ_ph_qbr(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEQU_PH_QBLA:
+ gen_helper_precequ_ph_qbla(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEQU_PH_QBRA:
+ gen_helper_precequ_ph_qbra(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEU_PH_QBL:
+ gen_helper_preceu_ph_qbl(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEU_PH_QBR:
+ gen_helper_preceu_ph_qbr(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEU_PH_QBLA:
+ gen_helper_preceu_ph_qbla(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ case OPC_PRECEU_PH_QBRA:
+ gen_helper_preceu_ph_qbra(cpu_gpr[rd], cpu_gpr[rt]);
+ break;
+ }
+ break;
+ case OPC_ADDU_QB_DSP:
+ op2 = MASK_ADDU_QB(ctx->opcode);
+ switch (op2) {
+ case OPC_ADDQ_PH:
+ gen_helper_addq_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDQ_S_PH:
+ gen_helper_addq_s_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDQ_S_W:
+ gen_helper_addq_s_w(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDU_QB:
+ gen_helper_addu_qb(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDU_S_QB:
+ gen_helper_addu_s_qb(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDU_PH:
+ gen_helper_addu_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDU_S_PH:
+ gen_helper_addu_s_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBQ_PH:
+ gen_helper_subq_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBQ_S_PH:
+ gen_helper_subq_s_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBQ_S_W:
+ gen_helper_subq_s_w(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBU_QB:
+ gen_helper_subu_qb(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBU_S_QB:
+ gen_helper_subu_s_qb(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBU_PH:
+ gen_helper_subu_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_SUBU_S_PH:
+ gen_helper_subu_s_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDSC:
+ gen_helper_addsc(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_ADDWC:
+ gen_helper_addwc(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_MODSUB:
+ gen_helper_modsub(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_RADDU_W_QB:
+ gen_helper_raddu_w_qb(cpu_gpr[rd], cpu_gpr[rs]);
+ break;
+ }
+ break;
+ case OPC_CMPU_EQ_QB_DSP:
+ op2 = MASK_CMPU_EQ_QB(ctx->opcode);
+ switch (op2) {
+ case OPC_PRECR_QB_PH:
+ gen_helper_precr_qb_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_PRECRQ_QB_PH:
+ gen_helper_precrq_qb_ph(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_PRECR_SRA_PH_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_precr_sra_ph_w(cpu_gpr[rt], temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ tcg_temp_free(temp_rd);
+ break;
+ }
+ case OPC_PRECR_SRA_R_PH_W:
+ {
+ TCGv temp_rd = tcg_const_i32(rd);
+ gen_helper_precr_sra_r_ph_w(cpu_gpr[rt], temp_rd,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ }
+ case OPC_PRECRQ_PH_W:
+ gen_helper_precrq_ph_w(cpu_gpr[rd], cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_PRECRQ_RS_PH_W:
+ gen_helper_precrq_rs_ph_w(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ case OPC_PRECRQU_S_QB_PH:
+ gen_helper_precrqu_s_qb_ph(cpu_gpr[rd], cpu_env,
+ cpu_gpr[rs], cpu_gpr[rt]);
+ break;
+ }
+ break;
#if defined(TARGET_MIPS64)
case OPC_DEXTM ... OPC_DEXT:
case OPC_DINSM ... OPC_DINS:
--
1.7.5.4
- [Qemu-devel] [PATCH V4 00/11] Qemu MIPS ASE DSP Sup port, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 01/11] Add MIPS DSP internal functions, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 02/11] Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 03/11] Add MIPS DSP Branch instruction Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 04/11] Add MIPS DSP Load instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 05/11] Add MIPS DSP Arithmetic instructions Support,
Jia Liu <=
- [Qemu-devel] [PATCH V4 06/11] Add MIPS DSP GPR-Based Shift instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 07/11] Add MIPS DSP Multiply instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 08/11] Add MIPS DSP Bit/Manipulation instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 09/11] Add MIPS DSP Compare-Pick instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 10/11] Add MIPS DSP Accumulator and DSPControl Access instructions Support, Jia Liu, 2012/03/29
- [Qemu-devel] [PATCH V4 11/11] Add MIPS DSP Testcases, Jia Liu, 2012/03/30
- Re: [Qemu-devel] [PATCH V4 00/11] Qemu MIPS ASE DSP Support, Richard Henderson, 2012/03/30